[people/ms/u-boot.git] / include / configs / MVBC_P.h

/*
 * (C) Copyright 2003-2004
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2004-2008
 * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <version.h>

#define CONFIG_MPC5xxx	1
#define CONFIG_MPC5200 	1

#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE	0xFF800000
#endif

#define CONFIG_SYS_MPC5XXX_CLKIN	33000000

#define CONFIG_MISC_INIT_R	1

#define CONFIG_SYS_CACHELINE_SIZE	32
#ifdef CONFIG_CMD_KGDB
#define CONFIG_SYS_CACHELINE_SHIFT	5
#endif

#define CONFIG_PSC_CONSOLE	1
#define CONFIG_BAUDRATE		115200
#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200, 230400}

#define CONFIG_PCI		1
#define CONFIG_PCI_PNP		1
#undef	CONFIG_PCI_SCAN_SHOW
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1

#define CONFIG_PCI_MEM_BUS	0x40000000
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x10000000

#define CONFIG_PCI_IO_BUS	0x50000000
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x01000000

#define CONFIG_SYS_XLB_PIPELINING	1
#define CONFIG_HIGH_BATS	1

#define MV_CI			mvBlueCOUGAR-P
#define MV_VCI			mvBlueCOUGAR-P
#define MV_FPGA_DATA		0xff860000
#define MV_FPGA_SIZE		0
#define MV_KERNEL_ADDR		0xffd00000
#define MV_INITRD_ADDR		0xff900000
#define MV_INITRD_LENGTH	0x00400000
#define MV_SCRATCH_ADDR		0x00000000
#define MV_SCRATCH_LENGTH	MV_INITRD_LENGTH
#define MV_SCRIPT_ADDR		0xff840000
#define MV_SCRIPT_ADDR2		0xff850000
#define MV_DTB_ADDR		0xfffc0000

#define CONFIG_SHOW_BOOT_PROGRESS 1

#define MV_KERNEL_ADDR_RAM	0x00100000
#define MV_DTB_ADDR_RAM		0x00600000
#define MV_INITRD_ADDR_RAM	0x01000000

/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT	1
#define CONFIG_OF_BOARD_SETUP	1

#define OF_CPU			"PowerPC,5200@0"
#define OF_SOC			"soc5200@f0000000"
#define OF_TBCLK		(bd->bi_busfreq / 4)
#define MV_DTB_NAME		mvbc-p.dtb
#define CONFIG_OF_STDOUT_VIA_ALIAS	1

/*
 * Supported commands
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_CACHE
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_PCI
#define CONFIG_CMD_FPGA
#define CONFIG_CMD_I2C

#undef CONFIG_WATCHDOG

#define CONFIG_BOOTP_VENDOREX
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_NTPSERVER
#define CONFIG_BOOTP_RANDOM_DELAY
#define CONFIG_BOOTP_SEND_HOSTNAME

/*
 * Autoboot
 */
#define CONFIG_BOOTDELAY		2
#define CONFIG_AUTOBOOT_KEYED
#define CONFIG_AUTOBOOT_STOP_STR 	"s"
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_RESET_TO_RETRY		1000

#define CONFIG_BOOTCOMMAND	"if imi ${script_addr}; \
					then source ${script_addr};	\
					else source ${script_addr2};	\
				fi;"

#define CONFIG_BOOTARGS		"root=/dev/ram ro rootfstype=squashfs"
#define CONFIG_ENV_OVERWRITE

#define XMK_STR(x)      #x
#define MK_STR(x)       XMK_STR(x)

#define CONFIG_EXTRA_ENV_SETTINGS				\
	"console_nr=0\0"					\
	"console=yes\0"						\
	"stdin=serial\0"					\
	"stdout=serial\0"					\
	"stderr=serial\0"					\
	"fpga=0\0"						\
	"fpgadata=" MK_STR(MV_FPGA_DATA) "\0"			\
	"fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0"		\
	"script_addr=" MK_STR(MV_SCRIPT_ADDR) "\0"		\
	"script_addr2=" MK_STR(MV_SCRIPT_ADDR2) "\0"		\
	"mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0"		\
	"mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0"	\
	"mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0"		\
	"mv_initrd_addr_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0"	\
	"mv_initrd_length=" MK_STR(MV_INITRD_LENGTH) "\0"	\
	"mv_dtb_addr=" MK_STR(MV_DTB_ADDR) "\0"			\
	"mv_dtb_addr_ram=" MK_STR(MV_DTB_ADDR_RAM) "\0"		\
	"dtb_name=" MK_STR(MV_DTB_NAME) "\0"			\
	"mv_scratch_addr=" MK_STR(MV_SCRATCH_ADDR) "\0"		\
	"mv_scratch_length=" MK_STR(MV_SCRATCH_LENGTH) "\0"	\
	"mv_version=" U_BOOT_VERSION "\0"			\
	"dhcp_client_id=" MK_STR(MV_CI) "\0"			\
	"dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0"	\
	"netretry=no\0"						\
	"use_static_ipaddr=no\0"				\
	"static_ipaddr=192.168.90.10\0"				\
	"static_netmask=255.255.255.0\0"			\
	"static_gateway=0.0.0.0\0"				\
	"initrd_name=uInitrd.mvbc-p-rfs\0"			\
	"zcip=no\0"						\
	"netboot=yes\0"						\
	"mvtest=Ff\0"						\
	"tried_bootfromflash=no\0"				\
	"tried_bootfromnet=no\0"				\
	"use_dhcp=yes\0"					\
	"gev_start=yes\0"					\
	"mvbcdma_debug=0\0"					\
	"mvbcia_debug=0\0"					\
	"propdev_debug=0\0"					\
	"gevss_debug=0\0"					\
	"watchdog=1\0"						\
	"sensor_cnt=1\0"					\
	""

#undef XMK_STR
#undef MK_STR

/*
 * IPB Bus clocking configuration.
 */
#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2

/*
 * Flash configuration
 */
#undef 	CONFIG_FLASH_16BIT
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
#define CONFIG_SYS_FLASH_EMPTY_INFO

#define CONFIG_SYS_FLASH_ERASE_TOUT	50000
#define CONFIG_SYS_FLASH_WRITE_TOUT	1000

#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_MAX_FLASH_SECT	256

#define CONFIG_SYS_LOWBOOT
#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_FLASH_SIZE		0x00800000

/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_FLASH
#undef	CONFIG_SYS_FLASH_PROTECTION

#define CONFIG_ENV_ADDR		0xFFFE0000
#define CONFIG_ENV_SIZE		0x10000
#define CONFIG_ENV_SECT_SIZE	0x10000
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE

/*
 * Memory map
 */
#define CONFIG_SYS_MBAR		0xF0000000
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_DEFAULT_MBAR	0x80000000

#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE

#define CONFIG_SYS_GBL_DATA_SIZE	128
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT		1
#endif

/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
#define CONFIG_SYS_MONITOR_LEN		(512 << 10)
#define CONFIG_SYS_MALLOC_LEN		(512 << 10)
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)

/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1
#define CONFIG_SYS_I2C_MODULE	1
#define CONFIG_SYS_I2C_SPEED	86000
#define CONFIG_SYS_I2C_SLAVE	0x7F

/*
 * Ethernet configuration
 */
#define CONFIG_NET_MULTI
#define CONFIG_NET_RETRY_COUNT 5

#define CONFIG_E1000
#define CONFIG_E1000_FALLBACK_MAC	{ 0xb6, 0xb4, 0x45, 0xeb, 0xfb, 0xc0 }
#undef CONFIG_MPC5xxx_FEC
#undef CONFIG_PHY_ADDR
#define CONFIG_NETDEV		eth0

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_PROMPT_HUSH_PS2 	"> "
#undef 	CONFIG_SYS_LONGHELP
#define CONFIG_SYS_PROMPT		"=> "
#ifdef CONFIG_CMD_KGDB
#define CONFIG_SYS_CBSIZE		1024
#else
#define CONFIG_SYS_CBSIZE		256
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS		16
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE

#define CONFIG_SYS_MEMTEST_START	0x00800000
#define CONFIG_SYS_MEMTEST_END		0x02f00000

#define CONFIG_SYS_HZ			1000

/* default load address */
#define CONFIG_SYS_LOAD_ADDR		0x02000000
/* default location for tftp and bootm */
#define CONFIG_LOADADDR 	0x00200000

/*
 * Various low-level settings
 */
#define CONFIG_SYS_GPS_PORT_CONFIG	0x20000004

#define CONFIG_SYS_HID0_INIT		(HID0_ICE | HID0_ICFI)
#define CONFIG_SYS_HID0_FINAL		HID0_ICE

#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_CFG		0x00047800
#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE

#define CONFIG_SYS_CS_BURST		0x000000f0
#define CONFIG_SYS_CS_DEADCYCLE	0x33333303

#define CONFIG_SYS_RESET_ADDRESS	0x00000100

#undef FPGA_DEBUG
#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
#define CONFIG_FPGA		CONFIG_SYS_ALTERA_CYCLON2
#define CONFIG_FPGA_ALTERA	1
#define CONFIG_FPGA_CYCLON2	1
#define CONFIG_FPGA_COUNT	1

#endif
Commit	Line	Data
5e0de0e2 AS	1	/*
	2	* (C) Copyright 2003-2004
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* (C) Copyright 2004-2008
	6	* Matrix-Vision GmbH, andre.schwarz@matrix-vision.de
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#ifndef __CONFIG_H
	28	#define __CONFIG_H
	29
	30	#include <version.h>
	31
	32	#define CONFIG_MPC5xxx 1
	33	#define CONFIG_MPC5200 1
	34
2ae18241 WD	35	#ifndef CONFIG_SYS_TEXT_BASE
	36	#define CONFIG_SYS_TEXT_BASE 0xFF800000
	37	#endif
	38
6d0f6bcf	39	#define CONFIG_SYS_MPC5XXX_CLKIN 33000000
5e0de0e2	40
5e0de0e2 AS	41	#define CONFIG_MISC_INIT_R 1
5e0de0e2 AS	42
6d0f6bcf	43	#define CONFIG_SYS_CACHELINE_SIZE 32
17e900b8	44	#ifdef CONFIG_CMD_KGDB
6d0f6bcf	45	#define CONFIG_SYS_CACHELINE_SHIFT 5
5e0de0e2 AS	46	#endif
	47
	48	#define CONFIG_PSC_CONSOLE 1
	49	#define CONFIG_BAUDRATE 115200
6d0f6bcf	50	#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200, 230400}
5e0de0e2 AS	51
	52	#define CONFIG_PCI 1
	53	#define CONFIG_PCI_PNP 1
	54	#undef CONFIG_PCI_SCAN_SHOW
	55	#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
	56
	57	#define CONFIG_PCI_MEM_BUS 0x40000000
	58	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	59	#define CONFIG_PCI_MEM_SIZE 0x10000000
	60
	61	#define CONFIG_PCI_IO_BUS 0x50000000
	62	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	63	#define CONFIG_PCI_IO_SIZE 0x01000000
	64
6d0f6bcf	65	#define CONFIG_SYS_XLB_PIPELINING 1
5e0de0e2 AS	66	#define CONFIG_HIGH_BATS 1
	67
	68	#define MV_CI mvBlueCOUGAR-P
	69	#define MV_VCI mvBlueCOUGAR-P
	70	#define MV_FPGA_DATA 0xff860000
28887d83	71	#define MV_FPGA_SIZE 0
e3b39f84	72	#define MV_KERNEL_ADDR 0xffd00000
5e0de0e2	73	#define MV_INITRD_ADDR 0xff900000
e3b39f84	74	#define MV_INITRD_LENGTH 0x00400000
5e0de0e2 AS	75	#define MV_SCRATCH_ADDR 0x00000000
5e0de0e2 AS	76	#define MV_SCRATCH_LENGTH MV_INITRD_LENGTH
3202d331 PT	77	#define MV_SCRIPT_ADDR 0xff840000
3202d331 PT	78	#define MV_SCRIPT_ADDR2 0xff850000
5e0de0e2 AS	79	#define MV_DTB_ADDR 0xfffc0000
	80
	81	#define CONFIG_SHOW_BOOT_PROGRESS 1
	82
	83	#define MV_KERNEL_ADDR_RAM 0x00100000
	84	#define MV_DTB_ADDR_RAM 0x00600000
	85	#define MV_INITRD_ADDR_RAM 0x01000000
	86
	87	/* pass open firmware flat tree */
	88	#define CONFIG_OF_LIBFDT 1
	89	#define CONFIG_OF_BOARD_SETUP 1
	90
	91	#define OF_CPU "PowerPC,5200@0"
	92	#define OF_SOC "soc5200@f0000000"
	93	#define OF_TBCLK (bd->bi_busfreq / 4)
	94	#define MV_DTB_NAME mvbc-p.dtb
	95	#define CONFIG_OF_STDOUT_VIA_ALIAS 1
	96
	97	/*
	98	* Supported commands
	99	*/
	100	#include <config_cmd_default.h>
	101
	102	#define CONFIG_CMD_CACHE
	103	#define CONFIG_CMD_NET
	104	#define CONFIG_CMD_PING
	105	#define CONFIG_CMD_DHCP
	106	#define CONFIG_CMD_SDRAM
	107	#define CONFIG_CMD_PCI
	108	#define CONFIG_CMD_FPGA
e3b39f84	109	#define CONFIG_CMD_I2C
5e0de0e2 AS	110
	111	#undef CONFIG_WATCHDOG
	112
	113	#define CONFIG_BOOTP_VENDOREX
	114	#define CONFIG_BOOTP_SUBNETMASK
	115	#define CONFIG_BOOTP_GATEWAY
	116	#define CONFIG_BOOTP_DNS
	117	#define CONFIG_BOOTP_DNS2
	118	#define CONFIG_BOOTP_HOSTNAME
	119	#define CONFIG_BOOTP_BOOTFILESIZE
	120	#define CONFIG_BOOTP_BOOTPATH
	121	#define CONFIG_BOOTP_NTPSERVER
	122	#define CONFIG_BOOTP_RANDOM_DELAY
	123	#define CONFIG_BOOTP_SEND_HOSTNAME
	124
	125	/*
	126	* Autoboot
	127	*/
	128	#define CONFIG_BOOTDELAY 2
	129	#define CONFIG_AUTOBOOT_KEYED
	130	#define CONFIG_AUTOBOOT_STOP_STR "s"
	131	#define CONFIG_ZERO_BOOTDELAY_CHECK
	132	#define CONFIG_RESET_TO_RETRY 1000
	133
3202d331 PT	134	#define CONFIG_BOOTCOMMAND "if imi ${script_addr}; \
	135	then source ${script_addr}; \
	136	else source ${script_addr2}; \
5e0de0e2 AS	137	fi;"
	138
	139	#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs"
	140	#define CONFIG_ENV_OVERWRITE
	141
	142	#define XMK_STR(x) #x
	143	#define MK_STR(x) XMK_STR(x)
	144
	145	#define CONFIG_EXTRA_ENV_SETTINGS \
	146	"console_nr=0\0" \
	147	"console=yes\0" \
	148	"stdin=serial\0" \
	149	"stdout=serial\0" \
	150	"stderr=serial\0" \
	151	"fpga=0\0" \
	152	"fpgadata=" MK_STR(MV_FPGA_DATA) "\0" \
	153	"fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0" \
3202d331 PT	154	"script_addr=" MK_STR(MV_SCRIPT_ADDR) "\0" \
3202d331 PT	155	"script_addr2=" MK_STR(MV_SCRIPT_ADDR2) "\0" \
5e0de0e2 AS	156	"mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0" \
	157	"mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0" \
	158	"mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0" \
	159	"mv_initrd_addr_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0" \
	160	"mv_initrd_length=" MK_STR(MV_INITRD_LENGTH) "\0" \
	161	"mv_dtb_addr=" MK_STR(MV_DTB_ADDR) "\0" \
	162	"mv_dtb_addr_ram=" MK_STR(MV_DTB_ADDR_RAM) "\0" \
	163	"dtb_name=" MK_STR(MV_DTB_NAME) "\0" \
	164	"mv_scratch_addr=" MK_STR(MV_SCRATCH_ADDR) "\0" \
	165	"mv_scratch_length=" MK_STR(MV_SCRATCH_LENGTH) "\0" \
	166	"mv_version=" U_BOOT_VERSION "\0" \
	167	"dhcp_client_id=" MK_STR(MV_CI) "\0" \
	168	"dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0" \
	169	"netretry=no\0" \
	170	"use_static_ipaddr=no\0" \
	171	"static_ipaddr=192.168.90.10\0" \
	172	"static_netmask=255.255.255.0\0" \
	173	"static_gateway=0.0.0.0\0" \
	174	"initrd_name=uInitrd.mvbc-p-rfs\0" \
	175	"zcip=no\0" \
	176	"netboot=yes\0" \
	177	"mvtest=Ff\0" \
	178	"tried_bootfromflash=no\0" \
	179	"tried_bootfromnet=no\0" \
	180	"use_dhcp=yes\0" \
	181	"gev_start=yes\0" \
	182	"mvbcdma_debug=0\0" \
	183	"mvbcia_debug=0\0" \
	184	"propdev_debug=0\0" \
	185	"gevss_debug=0\0" \
	186	"watchdog=1\0" \
e3b39f84	187	"sensor_cnt=1\0" \
5e0de0e2 AS	188	""
	189
	190	#undef XMK_STR
	191	#undef MK_STR
	192
	193	/*
	194	* IPB Bus clocking configuration.
	195	*/
6d0f6bcf JCPV	196	#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
6d0f6bcf JCPV	197	#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
5e0de0e2 AS	198
	199	/*
	200	* Flash configuration
	201	*/
	202	#undef CONFIG_FLASH_16BIT
6d0f6bcf	203	#define CONFIG_SYS_FLASH_CFI
00b1883a	204	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	205	#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
6d0f6bcf JCPV	206	#define CONFIG_SYS_FLASH_EMPTY_INFO
5e0de0e2	207
6d0f6bcf JCPV	208	#define CONFIG_SYS_FLASH_ERASE_TOUT 50000
6d0f6bcf JCPV	209	#define CONFIG_SYS_FLASH_WRITE_TOUT 1000
5e0de0e2	210
6d0f6bcf JCPV	211	#define CONFIG_SYS_MAX_FLASH_BANKS 1
6d0f6bcf JCPV	212	#define CONFIG_SYS_MAX_FLASH_SECT 256
5e0de0e2	213
6d0f6bcf	214	#define CONFIG_SYS_LOWBOOT
14d0a02a	215	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf	216	#define CONFIG_SYS_FLASH_SIZE 0x00800000
5e0de0e2 AS	217
	218	/*
	219	* Environment settings
	220	*/
5a1aceb0	221	#define CONFIG_ENV_IS_IN_FLASH
6d0f6bcf	222	#undef CONFIG_SYS_FLASH_PROTECTION
5e0de0e2	223
0e8d1586 JCPV	224	#define CONFIG_ENV_ADDR 0xFFFE0000
	225	#define CONFIG_ENV_SIZE 0x10000
	226	#define CONFIG_ENV_SECT_SIZE 0x10000
	227	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
	228	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
5e0de0e2 AS	229
	230	/*
	231	* Memory map
	232	*/
6d0f6bcf JCPV	233	#define CONFIG_SYS_MBAR 0xF0000000
	234	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	235	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
5e0de0e2	236
6d0f6bcf	237	#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
553f0982	238	#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
5e0de0e2	239
6d0f6bcf	240	#define CONFIG_SYS_GBL_DATA_SIZE 128
553f0982	241	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
6d0f6bcf	242	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
5e0de0e2	243
14d0a02a	244	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	245	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	246	#define CONFIG_SYS_RAMBOOT 1
5e0de0e2 AS	247	#endif
5e0de0e2 AS	248
6d0f6bcf JCPV	249	/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
	250	#define CONFIG_SYS_MONITOR_LEN (512 << 10)
	251	#define CONFIG_SYS_MALLOC_LEN (512 << 10)
	252	#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
5e0de0e2	253
e3b39f84 AS	254	/*
	255	* I2C configuration
	256	*/
	257	#define CONFIG_HARD_I2C 1
	258	#define CONFIG_SYS_I2C_MODULE 1
	259	#define CONFIG_SYS_I2C_SPEED 86000
	260	#define CONFIG_SYS_I2C_SLAVE 0x7F
	261
5e0de0e2 AS	262	/*
	263	* Ethernet configuration
	264	*/
	265	#define CONFIG_NET_MULTI
	266	#define CONFIG_NET_RETRY_COUNT 5
	267
	268	#define CONFIG_E1000
c4ec6db0	269	#define CONFIG_E1000_FALLBACK_MAC { 0xb6, 0xb4, 0x45, 0xeb, 0xfb, 0xc0 }
5e0de0e2 AS	270	#undef CONFIG_MPC5xxx_FEC
	271	#undef CONFIG_PHY_ADDR
	272	#define CONFIG_NETDEV eth0
	273
	274	/*
	275	* Miscellaneous configurable options
	276	*/
6d0f6bcf	277	#define CONFIG_SYS_HUSH_PARSER
5e0de0e2	278	#define CONFIG_CMDLINE_EDITING
6d0f6bcf JCPV	279	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
	280	#undef CONFIG_SYS_LONGHELP
	281	#define CONFIG_SYS_PROMPT "=> "
17e900b8	282	#ifdef CONFIG_CMD_KGDB
6d0f6bcf	283	#define CONFIG_SYS_CBSIZE 1024
5e0de0e2	284	#else
6d0f6bcf	285	#define CONFIG_SYS_CBSIZE 256
5e0de0e2	286	#endif
6d0f6bcf JCPV	287	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
	288	#define CONFIG_SYS_MAXARGS 16
	289	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
5e0de0e2	290
6d0f6bcf JCPV	291	#define CONFIG_SYS_MEMTEST_START 0x00800000
6d0f6bcf JCPV	292	#define CONFIG_SYS_MEMTEST_END 0x02f00000
5e0de0e2	293
6d0f6bcf	294	#define CONFIG_SYS_HZ 1000
5e0de0e2 AS	295
5e0de0e2 AS	296	/* default load address */
6d0f6bcf	297	#define CONFIG_SYS_LOAD_ADDR 0x02000000
5e0de0e2 AS	298	/* default location for tftp and bootm */
	299	#define CONFIG_LOADADDR 0x00200000
	300
	301	/*
	302	* Various low-level settings
	303	*/
6d0f6bcf	304	#define CONFIG_SYS_GPS_PORT_CONFIG 0x20000004
5e0de0e2	305
6d0f6bcf JCPV	306	#define CONFIG_SYS_HID0_INIT (HID0_ICE \| HID0_ICFI)
6d0f6bcf JCPV	307	#define CONFIG_SYS_HID0_FINAL HID0_ICE
5e0de0e2	308
6d0f6bcf JCPV	309	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
	310	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	311	#define CONFIG_SYS_BOOTCS_CFG 0x00047800
	312	#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
	313	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
5e0de0e2	314
6d0f6bcf JCPV	315	#define CONFIG_SYS_CS_BURST 0x000000f0
6d0f6bcf JCPV	316	#define CONFIG_SYS_CS_DEADCYCLE 0x33333303
5e0de0e2	317
6d0f6bcf	318	#define CONFIG_SYS_RESET_ADDRESS 0x00000100
5e0de0e2 AS	319
5e0de0e2 AS	320	#undef FPGA_DEBUG
6d0f6bcf JCPV	321	#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
6d0f6bcf JCPV	322	#define CONFIG_FPGA CONFIG_SYS_ALTERA_CYCLON2
5e0de0e2 AS	323	#define CONFIG_FPGA_ALTERA 1
	324	#define CONFIG_FPGA_CYCLON2 1
	325	#define CONFIG_FPGA_COUNT 1
	326
	327	#endif