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c2042f59 | 1 | /* |
2 | * Configuation settings for the Renesas Solutions Migo-R board | |
3 | * | |
4 | * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
c2042f59 | 7 | */ |
8 | ||
9 | #ifndef __MIGO_R_H | |
10 | #define __MIGO_R_H | |
11 | ||
c2042f59 | 12 | #define CONFIG_CPU_SH7722 1 |
13 | #define CONFIG_MIGO_R 1 | |
14 | ||
18a40e84 | 15 | #define CONFIG_DISPLAY_BOARDINFO |
c2042f59 | 16 | #undef CONFIG_SHOW_BOOT_PROGRESS |
17 | ||
18 | /* SMC9111 */ | |
7194ab80 | 19 | #define CONFIG_SMC91111 |
c2042f59 | 20 | #define CONFIG_SMC91111_BASE (0xB0000000) |
21 | ||
22 | /* MEMORY */ | |
23 | #define MIGO_R_SDRAM_BASE (0x8C000000) | |
24 | #define MIGO_R_FLASH_BASE_1 (0xA0000000) | |
25 | #define MIGO_R_FLASH_BANK_SIZE (64 * 1024 * 1024) | |
26 | ||
8cd7379e | 27 | #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 |
6d0f6bcf | 28 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
6d0f6bcf | 29 | #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ |
6d0f6bcf JCPV |
30 | #define CONFIG_SYS_BARGSIZE 512 /* Buffer size for Boot Arguments passed to kernel */ |
31 | #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */ | |
c2042f59 | 32 | |
33 | /* SCIF */ | |
c2042f59 | 34 | #define CONFIG_CONS_SCIF0 1 |
c2042f59 | 35 | |
6d0f6bcf JCPV |
36 | #define CONFIG_SYS_MEMTEST_START (MIGO_R_SDRAM_BASE) |
37 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) | |
c2042f59 | 38 | |
39 | /* Enable alternate, more extensive, memory test */ | |
6d0f6bcf | 40 | #undef CONFIG_SYS_ALT_MEMTEST |
c2042f59 | 41 | /* Scratch address used by the alternate memory test */ |
6d0f6bcf | 42 | #undef CONFIG_SYS_MEMTEST_SCRATCH |
c2042f59 | 43 | |
44 | /* Enable temporary baudrate change while serial download */ | |
6d0f6bcf | 45 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE |
c2042f59 | 46 | |
6d0f6bcf | 47 | #define CONFIG_SYS_SDRAM_BASE (MIGO_R_SDRAM_BASE) |
c2042f59 | 48 | /* maybe more, but if so u-boot doesn't know about it... */ |
6d0f6bcf | 49 | #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) |
c2042f59 | 50 | /* default load address for scripts ?!? */ |
6d0f6bcf | 51 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) |
c2042f59 | 52 | |
53 | /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */ | |
6d0f6bcf | 54 | #define CONFIG_SYS_MONITOR_BASE (MIGO_R_FLASH_BASE_1) |
c2042f59 | 55 | /* Monitor size */ |
6d0f6bcf | 56 | #define CONFIG_SYS_MONITOR_LEN (128 * 1024) |
c2042f59 | 57 | /* Size of DRAM reserved for malloc() use */ |
6d0f6bcf | 58 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) |
6d0f6bcf | 59 | #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) |
c2042f59 | 60 | |
61 | /* FLASH */ | |
6d0f6bcf | 62 | #define CONFIG_SYS_FLASH_CFI |
00b1883a | 63 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf | 64 | #undef CONFIG_SYS_FLASH_QUIET_TEST |
c2042f59 | 65 | /* print 'E' for empty sector on flinfo */ |
6d0f6bcf | 66 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
c2042f59 | 67 | /* Physical start address of Flash memory */ |
6d0f6bcf | 68 | #define CONFIG_SYS_FLASH_BASE (MIGO_R_FLASH_BASE_1) |
c2042f59 | 69 | /* Max number of sectors on each Flash chip */ |
6d0f6bcf | 70 | #define CONFIG_SYS_MAX_FLASH_SECT 512 |
c2042f59 | 71 | |
72 | /* if you use all NOR Flash , you change dip-switch. Please see MIGO_R01 Manual. */ | |
6d0f6bcf JCPV |
73 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
74 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * MIGO_R_FLASH_BANK_SIZE) } | |
c2042f59 | 75 | |
76 | /* Timeout for Flash erase operations (in ms) */ | |
6d0f6bcf | 77 | #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) |
c2042f59 | 78 | /* Timeout for Flash write operations (in ms) */ |
6d0f6bcf | 79 | #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) |
c2042f59 | 80 | /* Timeout for Flash set sector lock bit operations (in ms) */ |
6d0f6bcf | 81 | #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) |
c2042f59 | 82 | /* Timeout for Flash clear lock bit operations (in ms) */ |
6d0f6bcf | 83 | #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) |
c2042f59 | 84 | |
85 | /* Use hardware flash sectors protection instead of U-Boot software protection */ | |
6d0f6bcf JCPV |
86 | #undef CONFIG_SYS_FLASH_PROTECTION |
87 | #undef CONFIG_SYS_DIRECT_FLASH_TFTP | |
c2042f59 | 88 | |
89 | /* ENV setting */ | |
c2042f59 | 90 | #define CONFIG_ENV_OVERWRITE 1 |
0e8d1586 JCPV |
91 | #define CONFIG_ENV_SECT_SIZE (128 * 1024) |
92 | #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) | |
6d0f6bcf JCPV |
93 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) |
94 | /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ | |
95 | #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) | |
0e8d1586 | 96 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) |
c2042f59 | 97 | |
98 | /* Board Clock */ | |
99 | #define CONFIG_SYS_CLK_FREQ 33333333 | |
684a501e NI |
100 | #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ |
101 | #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ | |
be45c632 | 102 | #define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */ |
c2042f59 | 103 | |
104 | #endif /* __MIGO_R_H */ |