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Commit | Line | Data |
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ee52b188 YS |
1 | /* |
2 | * Copyright 2011-2012 Freescale Semiconductor, Inc. | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
ee52b188 YS |
5 | */ |
6 | ||
7 | /* | |
8 | * T4240 QDS board configuration file | |
9 | */ | |
1cb19fbb YS |
10 | #ifndef __CONFIG_H |
11 | #define __CONFIG_H | |
12 | ||
ee52b188 | 13 | #define CONFIG_T4240QDS |
ee52b188 YS |
14 | |
15 | #define CONFIG_FSL_SATA_V2 | |
16 | #define CONFIG_PCIE4 | |
737537ef | 17 | #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ |
ee52b188 YS |
18 | |
19 | #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ | |
20 | ||
1cb19fbb | 21 | #ifdef CONFIG_RAMBOOT_PBL |
e4536f8e MY |
22 | #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg |
23 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_rcw.cfg | |
b6036993 SX |
24 | #if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD) |
25 | #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE | |
26 | #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc | |
27 | #else | |
b6036993 | 28 | #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT |
b6036993 SX |
29 | #define CONFIG_SPL_SERIAL_SUPPORT |
30 | #define CONFIG_SPL_FLUSH_IMAGE | |
31 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
b6036993 SX |
32 | #define CONFIG_FSL_LAW /* Use common FSL init code */ |
33 | #define CONFIG_SYS_TEXT_BASE 0x00201000 | |
34 | #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 | |
35 | #define CONFIG_SPL_PAD_TO 0x40000 | |
36 | #define CONFIG_SPL_MAX_SIZE 0x28000 | |
37 | #define RESET_VECTOR_OFFSET 0x27FFC | |
38 | #define BOOT_PAGE_OFFSET 0x27000 | |
39 | ||
40 | #ifdef CONFIG_NAND | |
41 | #define CONFIG_SPL_NAND_SUPPORT | |
42 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) | |
43 | #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 | |
44 | #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 | |
45 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) | |
46 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" | |
47 | #define CONFIG_SPL_NAND_BOOT | |
48 | #endif | |
49 | ||
50 | #ifdef CONFIG_SDCARD | |
51 | #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC | |
b6036993 SX |
52 | #define CONFIG_SPL_MMC_MINIMAL |
53 | #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) | |
54 | #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 | |
55 | #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 | |
56 | #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) | |
57 | #ifndef CONFIG_SPL_BUILD | |
58 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
59 | #endif | |
60 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" | |
61 | #define CONFIG_SPL_MMC_BOOT | |
62 | #endif | |
63 | ||
64 | #ifdef CONFIG_SPL_BUILD | |
65 | #define CONFIG_SPL_SKIP_RELOCATE | |
66 | #define CONFIG_SPL_COMMON_INIT_DDR | |
67 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE | |
68 | #define CONFIG_SYS_NO_FLASH | |
69 | #endif | |
70 | ||
1cb19fbb | 71 | #endif |
b6036993 | 72 | #endif /* CONFIG_RAMBOOT_PBL */ |
1cb19fbb YS |
73 | |
74 | #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE | |
75 | /* Set 1M boot space */ | |
76 | #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) | |
77 | #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ | |
78 | (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) | |
79 | #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc | |
80 | #define CONFIG_SYS_NO_FLASH | |
81 | #endif | |
82 | ||
83 | #define CONFIG_SRIO_PCIE_BOOT_MASTER | |
84 | #define CONFIG_DDR_ECC | |
85 | ||
ee52b188 | 86 | #include "t4qds.h" |
1cb19fbb YS |
87 | |
88 | #ifdef CONFIG_SYS_NO_FLASH | |
89 | #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) | |
90 | #define CONFIG_ENV_IS_NOWHERE | |
91 | #endif | |
92 | #else | |
93 | #define CONFIG_FLASH_CFI_DRIVER | |
94 | #define CONFIG_SYS_FLASH_CFI | |
95 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
96 | #endif | |
97 | ||
98 | #if defined(CONFIG_SPIFLASH) | |
99 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
100 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
101 | #define CONFIG_ENV_SPI_BUS 0 | |
102 | #define CONFIG_ENV_SPI_CS 0 | |
103 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 | |
104 | #define CONFIG_ENV_SPI_MODE 0 | |
105 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ | |
106 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ | |
107 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
108 | #elif defined(CONFIG_SDCARD) | |
109 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
110 | #define CONFIG_ENV_IS_IN_MMC | |
111 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
112 | #define CONFIG_ENV_SIZE 0x2000 | |
b6036993 | 113 | #define CONFIG_ENV_OFFSET (512 * 0x800) |
1cb19fbb YS |
114 | #elif defined(CONFIG_NAND) |
115 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
116 | #define CONFIG_ENV_IS_IN_NAND | |
b6036993 SX |
117 | #define CONFIG_ENV_SIZE 0x2000 |
118 | #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) | |
1cb19fbb YS |
119 | #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) |
120 | #define CONFIG_ENV_IS_IN_REMOTE | |
121 | #define CONFIG_ENV_ADDR 0xffe20000 | |
122 | #define CONFIG_ENV_SIZE 0x2000 | |
123 | #elif defined(CONFIG_ENV_IS_NOWHERE) | |
124 | #define CONFIG_ENV_SIZE 0x2000 | |
125 | #else | |
126 | #define CONFIG_ENV_IS_IN_FLASH | |
127 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
128 | #define CONFIG_ENV_SIZE 0x2000 | |
129 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
130 | #endif | |
131 | ||
132 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() | |
133 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() | |
134 | ||
135 | #ifndef __ASSEMBLY__ | |
136 | unsigned long get_board_sys_clk(void); | |
137 | unsigned long get_board_ddr_clk(void); | |
138 | #endif | |
139 | ||
140 | /* EEPROM */ | |
141 | #define CONFIG_ID_EEPROM | |
142 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
143 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
144 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
145 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
146 | ||
147 | /* | |
148 | * DDR Setup | |
149 | */ | |
150 | #define CONFIG_SYS_SPD_BUS_NUM 0 | |
151 | #define SPD_EEPROM_ADDRESS1 0x51 | |
152 | #define SPD_EEPROM_ADDRESS2 0x52 | |
153 | #define SPD_EEPROM_ADDRESS3 0x53 | |
154 | #define SPD_EEPROM_ADDRESS4 0x54 | |
155 | #define SPD_EEPROM_ADDRESS5 0x55 | |
156 | #define SPD_EEPROM_ADDRESS6 0x56 | |
157 | #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ | |
158 | #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ | |
159 | ||
160 | /* | |
161 | * IFC Definitions | |
162 | */ | |
163 | #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) | |
164 | #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ | |
165 | + 0x8000000) | \ | |
166 | CSPR_PORT_SIZE_16 | \ | |
167 | CSPR_MSEL_NOR | \ | |
168 | CSPR_V) | |
169 | #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) | |
170 | #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
171 | CSPR_PORT_SIZE_16 | \ | |
172 | CSPR_MSEL_NOR | \ | |
173 | CSPR_V) | |
174 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) | |
175 | /* NOR Flash Timing Params */ | |
176 | #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 | |
177 | ||
178 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ | |
179 | FTIM0_NOR_TEADC(0x5) | \ | |
180 | FTIM0_NOR_TEAHC(0x5)) | |
181 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ | |
182 | FTIM1_NOR_TRAD_NOR(0x1A) |\ | |
183 | FTIM1_NOR_TSEQRAD_NOR(0x13)) | |
184 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ | |
185 | FTIM2_NOR_TCH(0x4) | \ | |
186 | FTIM2_NOR_TWPH(0x0E) | \ | |
187 | FTIM2_NOR_TWP(0x1c)) | |
188 | #define CONFIG_SYS_NOR_FTIM3 0x0 | |
189 | ||
190 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
191 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
192 | ||
193 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
194 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
195 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
196 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
197 | ||
198 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
199 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ | |
200 | + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} | |
201 | ||
202 | #define CONFIG_FSL_QIXIS /* use common QIXIS code */ | |
203 | #define QIXIS_BASE 0xffdf0000 | |
204 | #define QIXIS_LBMAP_SWITCH 6 | |
205 | #define QIXIS_LBMAP_MASK 0x0f | |
206 | #define QIXIS_LBMAP_SHIFT 0 | |
207 | #define QIXIS_LBMAP_DFLTBANK 0x00 | |
208 | #define QIXIS_LBMAP_ALTBANK 0x04 | |
209 | #define QIXIS_RST_CTL_RESET 0x83 | |
c63e1370 | 210 | #define QIXIS_RST_FORCE_MEM 0x1 |
1cb19fbb YS |
211 | #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 |
212 | #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 | |
213 | #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 | |
f7e27cc5 HZ |
214 | #define QIXIS_BRDCFG5 0x55 |
215 | #define QIXIS_MUX_SDHC 2 | |
d47e3d27 | 216 | #define QIXIS_MUX_SDHC_WIDTH8 1 |
1cb19fbb YS |
217 | #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) |
218 | ||
219 | #define CONFIG_SYS_CSPR3_EXT (0xf) | |
220 | #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ | |
221 | | CSPR_PORT_SIZE_8 \ | |
222 | | CSPR_MSEL_GPCM \ | |
223 | | CSPR_V) | |
224 | #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) | |
225 | #define CONFIG_SYS_CSOR3 0x0 | |
226 | /* QIXIS Timing parameters for IFC CS3 */ | |
227 | #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ | |
228 | FTIM0_GPCM_TEADC(0x0e) | \ | |
229 | FTIM0_GPCM_TEAHC(0x0e)) | |
230 | #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ | |
231 | FTIM1_GPCM_TRAD(0x3f)) | |
232 | #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ | |
de519163 | 233 | FTIM2_GPCM_TCH(0x8) | \ |
1cb19fbb YS |
234 | FTIM2_GPCM_TWP(0x1f)) |
235 | #define CONFIG_SYS_CS3_FTIM3 0x0 | |
236 | ||
237 | /* NAND Flash on IFC */ | |
238 | #define CONFIG_NAND_FSL_IFC | |
239 | #define CONFIG_SYS_NAND_BASE 0xff800000 | |
240 | #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) | |
241 | ||
242 | #define CONFIG_SYS_NAND_CSPR_EXT (0xf) | |
243 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
244 | | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | |
245 | | CSPR_MSEL_NAND /* MSEL = NAND */ \ | |
246 | | CSPR_V) | |
247 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) | |
248 | ||
249 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | |
250 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
251 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
252 | | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ | |
253 | | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ | |
254 | | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ | |
255 | | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ | |
256 | ||
257 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
258 | ||
259 | /* ONFI NAND Flash mode0 Timing Params */ | |
260 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ | |
261 | FTIM0_NAND_TWP(0x18) | \ | |
262 | FTIM0_NAND_TWCHT(0x07) | \ | |
263 | FTIM0_NAND_TWH(0x0a)) | |
264 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ | |
265 | FTIM1_NAND_TWBE(0x39) | \ | |
266 | FTIM1_NAND_TRR(0x0e) | \ | |
267 | FTIM1_NAND_TRP(0x18)) | |
268 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ | |
269 | FTIM2_NAND_TREH(0x0a) | \ | |
270 | FTIM2_NAND_TWHRE(0x1e)) | |
271 | #define CONFIG_SYS_NAND_FTIM3 0x0 | |
272 | ||
273 | #define CONFIG_SYS_NAND_DDR_LAW 11 | |
274 | ||
275 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
276 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
1cb19fbb YS |
277 | #define CONFIG_CMD_NAND |
278 | ||
279 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
68ec9c85 PK |
280 | #define CONFIG_SYS_NAND_MAX_OOBFREE 2 |
281 | #define CONFIG_SYS_NAND_MAX_ECCPOS 256 | |
1cb19fbb YS |
282 | |
283 | #if defined(CONFIG_NAND) | |
284 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT | |
285 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR | |
286 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
287 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
288 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
289 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
290 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
291 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
b6036993 SX |
292 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT |
293 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR | |
294 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
295 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
296 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
297 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
298 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
299 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
300 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT | |
301 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR | |
1cb19fbb YS |
302 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK |
303 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR | |
304 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
305 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
306 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
307 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
308 | #else | |
309 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
310 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR | |
311 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
312 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
313 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
314 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
315 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
316 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
b6036993 SX |
317 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT |
318 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR | |
319 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
320 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
321 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
322 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
323 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
324 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
1cb19fbb YS |
325 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT |
326 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR | |
327 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK | |
328 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR | |
329 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
330 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
331 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
332 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
333 | #endif | |
1cb19fbb YS |
334 | |
335 | #if defined(CONFIG_RAMBOOT_PBL) | |
336 | #define CONFIG_SYS_RAMBOOT | |
337 | #endif | |
338 | ||
1cb19fbb YS |
339 | /* I2C */ |
340 | #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ | |
341 | #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ | |
342 | #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ | |
343 | #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ | |
344 | ||
345 | #define I2C_MUX_CH_DEFAULT 0x8 | |
346 | #define I2C_MUX_CH_VOL_MONITOR 0xa | |
347 | #define I2C_MUX_CH_VSC3316_FS 0xc | |
348 | #define I2C_MUX_CH_VSC3316_BS 0xd | |
349 | ||
350 | /* Voltage monitor on channel 2*/ | |
351 | #define I2C_VOL_MONITOR_ADDR 0x40 | |
352 | #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 | |
353 | #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 | |
354 | #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 | |
355 | ||
356 | /* VSC Crossbar switches */ | |
357 | #define CONFIG_VSC_CROSSBAR | |
358 | #define VSC3316_FSM_TX_ADDR 0x70 | |
359 | #define VSC3316_FSM_RX_ADDR 0x71 | |
360 | ||
361 | /* | |
362 | * RapidIO | |
363 | */ | |
364 | ||
365 | /* | |
366 | * for slave u-boot IMAGE instored in master memory space, | |
367 | * PHYS must be aligned based on the SIZE | |
368 | */ | |
e4911815 LG |
369 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull |
370 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull | |
371 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ | |
372 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull | |
1cb19fbb YS |
373 | /* |
374 | * for slave UCODE and ENV instored in master memory space, | |
375 | * PHYS must be aligned based on the SIZE | |
376 | */ | |
e4911815 | 377 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull |
1cb19fbb YS |
378 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull |
379 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ | |
380 | ||
381 | /* slave core release by master*/ | |
382 | #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 | |
383 | #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ | |
384 | ||
385 | /* | |
386 | * SRIO_PCIE_BOOT - SLAVE | |
387 | */ | |
388 | #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE | |
389 | #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 | |
390 | #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ | |
391 | (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) | |
392 | #endif | |
393 | /* | |
394 | * eSPI - Enhanced SPI | |
395 | */ | |
1cb19fbb YS |
396 | #define CONFIG_SF_DEFAULT_SPEED 10000000 |
397 | #define CONFIG_SF_DEFAULT_MODE 0 | |
398 | ||
1cb19fbb YS |
399 | /* Qman/Bman */ |
400 | #ifndef CONFIG_NOBQFMAN | |
401 | #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ | |
402 | #define CONFIG_SYS_BMAN_NUM_PORTALS 50 | |
403 | #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 | |
404 | #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull | |
405 | #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 | |
3fa66db4 JL |
406 | #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 |
407 | #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 | |
408 | #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE | |
409 | #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
410 | #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ | |
411 | CONFIG_SYS_BMAN_CENA_SIZE) | |
412 | #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
413 | #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 | |
1cb19fbb YS |
414 | #define CONFIG_SYS_QMAN_NUM_PORTALS 50 |
415 | #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 | |
416 | #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull | |
417 | #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 | |
3fa66db4 JL |
418 | #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 |
419 | #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 | |
420 | #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE | |
421 | #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
422 | #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ | |
423 | CONFIG_SYS_QMAN_CENA_SIZE) | |
424 | #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
425 | #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 | |
1cb19fbb YS |
426 | |
427 | #define CONFIG_SYS_DPAA_FMAN | |
428 | #define CONFIG_SYS_DPAA_PME | |
429 | #define CONFIG_SYS_PMAN | |
430 | #define CONFIG_SYS_DPAA_DCE | |
0795eff3 | 431 | #define CONFIG_SYS_DPAA_RMAN |
1cb19fbb YS |
432 | #define CONFIG_SYS_INTERLAKEN |
433 | ||
434 | /* Default address of microcode for the Linux Fman driver */ | |
435 | #if defined(CONFIG_SPIFLASH) | |
436 | /* | |
437 | * env is stored at 0x100000, sector size is 0x10000, ucode is stored after | |
438 | * env, so we got 0x110000. | |
439 | */ | |
440 | #define CONFIG_SYS_QE_FW_IN_SPIFLASH | |
dcf1d774 | 441 | #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 |
1cb19fbb YS |
442 | #elif defined(CONFIG_SDCARD) |
443 | /* | |
444 | * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is | |
b6036993 SX |
445 | * about 1MB (2048 blocks), Env is stored after the image, and the env size is |
446 | * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. | |
1cb19fbb YS |
447 | */ |
448 | #define CONFIG_SYS_QE_FMAN_FW_IN_MMC | |
b6036993 | 449 | #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) |
1cb19fbb YS |
450 | #elif defined(CONFIG_NAND) |
451 | #define CONFIG_SYS_QE_FMAN_FW_IN_NAND | |
b6036993 | 452 | #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) |
1cb19fbb YS |
453 | #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) |
454 | /* | |
455 | * Slave has no ucode locally, it can fetch this from remote. When implementing | |
456 | * in two corenet boards, slave's ucode could be stored in master's memory | |
457 | * space, the address can be mapped from slave TLB->slave LAW-> | |
458 | * slave SRIO or PCIE outbound window->master inbound window-> | |
459 | * master LAW->the ucode address in master's memory space. | |
460 | */ | |
461 | #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE | |
dcf1d774 | 462 | #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 |
1cb19fbb YS |
463 | #else |
464 | #define CONFIG_SYS_QE_FMAN_FW_IN_NOR | |
dcf1d774 | 465 | #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 |
1cb19fbb YS |
466 | #endif |
467 | #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 | |
468 | #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) | |
469 | #endif /* CONFIG_NOBQFMAN */ | |
470 | ||
471 | #ifdef CONFIG_SYS_DPAA_FMAN | |
472 | #define CONFIG_FMAN_ENET | |
473 | #define CONFIG_PHYLIB_10G | |
474 | #define CONFIG_PHY_VITESSE | |
475 | #define CONFIG_PHY_TERANETICS | |
476 | #define SGMII_CARD_PORT1_PHY_ADDR 0x1C | |
477 | #define SGMII_CARD_PORT2_PHY_ADDR 0x1D | |
478 | #define SGMII_CARD_PORT3_PHY_ADDR 0x1E | |
479 | #define SGMII_CARD_PORT4_PHY_ADDR 0x1F | |
480 | #define FM1_10GEC1_PHY_ADDR 0x0 | |
481 | #define FM1_10GEC2_PHY_ADDR 0x1 | |
482 | #define FM2_10GEC1_PHY_ADDR 0x2 | |
483 | #define FM2_10GEC2_PHY_ADDR 0x3 | |
484 | #endif | |
485 | ||
1cb19fbb YS |
486 | /* SATA */ |
487 | #ifdef CONFIG_FSL_SATA_V2 | |
488 | #define CONFIG_LIBATA | |
489 | #define CONFIG_FSL_SATA | |
490 | ||
491 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 | |
492 | #define CONFIG_SATA1 | |
493 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR | |
494 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
495 | #define CONFIG_SATA2 | |
496 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR | |
497 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
498 | ||
499 | #define CONFIG_LBA48 | |
500 | #define CONFIG_CMD_SATA | |
501 | #define CONFIG_DOS_PARTITION | |
1cb19fbb YS |
502 | #endif |
503 | ||
504 | #ifdef CONFIG_FMAN_ENET | |
505 | #define CONFIG_MII /* MII PHY management */ | |
506 | #define CONFIG_ETHPRIME "FM1@DTSEC1" | |
507 | #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ | |
508 | #endif | |
509 | ||
737537ef RG |
510 | /* Hash command with SHA acceleration supported in hardware */ |
511 | #ifdef CONFIG_FSL_CAAM | |
512 | #define CONFIG_CMD_HASH | |
513 | #define CONFIG_SHA_HW_ACCEL | |
514 | #endif | |
515 | ||
1cb19fbb YS |
516 | /* |
517 | * USB | |
518 | */ | |
1cb19fbb YS |
519 | #define CONFIG_USB_EHCI |
520 | #define CONFIG_USB_EHCI_FSL | |
521 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
1cb19fbb YS |
522 | #define CONFIG_HAS_FSL_DR_USB |
523 | ||
524 | #define CONFIG_MMC | |
525 | ||
526 | #ifdef CONFIG_MMC | |
527 | #define CONFIG_FSL_ESDHC | |
528 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
529 | #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT | |
1cb19fbb | 530 | #define CONFIG_GENERIC_MMC |
1cb19fbb | 531 | #define CONFIG_DOS_PARTITION |
ef38f3ff | 532 | #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 |
f7e27cc5 HZ |
533 | #define CONFIG_ESDHC_DETECT_QUIRK \ |
534 | (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \ | |
535 | IS_SVR_REV(get_svr(), 1, 0)) | |
d47e3d27 HZ |
536 | #define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \ |
537 | (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8)) | |
1cb19fbb YS |
538 | #endif |
539 | ||
1cb19fbb YS |
540 | |
541 | #define __USB_PHY_TYPE utmi | |
542 | ||
543 | /* | |
544 | * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be | |
545 | * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way | |
546 | * interleaving. It can be cacheline, page, bank, superbank. | |
547 | * See doc/README.fsl-ddr for details. | |
548 | */ | |
549 | #ifdef CONFIG_PPC_T4240 | |
550 | #define CTRL_INTLV_PREFERED 3way_4KB | |
551 | #else | |
552 | #define CTRL_INTLV_PREFERED cacheline | |
553 | #endif | |
554 | ||
555 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
556 | "hwconfig=fsl_ddr:" \ | |
557 | "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ | |
558 | "bank_intlv=auto;" \ | |
559 | "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ | |
560 | "netdev=eth0\0" \ | |
561 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ | |
562 | "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ | |
563 | "tftpflash=tftpboot $loadaddr $uboot && " \ | |
564 | "protect off $ubootaddr +$filesize && " \ | |
565 | "erase $ubootaddr +$filesize && " \ | |
566 | "cp.b $loadaddr $ubootaddr $filesize && " \ | |
567 | "protect on $ubootaddr +$filesize && " \ | |
568 | "cmp.b $loadaddr $ubootaddr $filesize\0" \ | |
569 | "consoledev=ttyS0\0" \ | |
570 | "ramdiskaddr=2000000\0" \ | |
571 | "ramdiskfile=t4240qds/ramdisk.uboot\0" \ | |
b24a4f62 | 572 | "fdtaddr=1e00000\0" \ |
1cb19fbb | 573 | "fdtfile=t4240qds/t4240qds.dtb\0" \ |
3246584d | 574 | "bdev=sda3\0" |
1cb19fbb YS |
575 | |
576 | #define CONFIG_HVBOOT \ | |
577 | "setenv bootargs config-addr=0x60000000; " \ | |
578 | "bootm 0x01000000 - 0x00f00000" | |
579 | ||
580 | #define CONFIG_ALU \ | |
581 | "setenv bootargs root=/dev/$bdev rw " \ | |
582 | "console=$consoledev,$baudrate $othbootargs;" \ | |
583 | "cpu 1 release 0x01000000 - - -;" \ | |
584 | "cpu 2 release 0x01000000 - - -;" \ | |
585 | "cpu 3 release 0x01000000 - - -;" \ | |
586 | "cpu 4 release 0x01000000 - - -;" \ | |
587 | "cpu 5 release 0x01000000 - - -;" \ | |
588 | "cpu 6 release 0x01000000 - - -;" \ | |
589 | "cpu 7 release 0x01000000 - - -;" \ | |
590 | "go 0x01000000" | |
591 | ||
592 | #define CONFIG_LINUX \ | |
593 | "setenv bootargs root=/dev/ram rw " \ | |
594 | "console=$consoledev,$baudrate $othbootargs;" \ | |
595 | "setenv ramdiskaddr 0x02000000;" \ | |
596 | "setenv fdtaddr 0x00c00000;" \ | |
597 | "setenv loadaddr 0x1000000;" \ | |
598 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
599 | ||
600 | #define CONFIG_HDBOOT \ | |
601 | "setenv bootargs root=/dev/$bdev rw " \ | |
602 | "console=$consoledev,$baudrate $othbootargs;" \ | |
603 | "tftp $loadaddr $bootfile;" \ | |
604 | "tftp $fdtaddr $fdtfile;" \ | |
605 | "bootm $loadaddr - $fdtaddr" | |
606 | ||
607 | #define CONFIG_NFSBOOTCOMMAND \ | |
608 | "setenv bootargs root=/dev/nfs rw " \ | |
609 | "nfsroot=$serverip:$rootpath " \ | |
610 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
611 | "console=$consoledev,$baudrate $othbootargs;" \ | |
612 | "tftp $loadaddr $bootfile;" \ | |
613 | "tftp $fdtaddr $fdtfile;" \ | |
614 | "bootm $loadaddr - $fdtaddr" | |
615 | ||
616 | #define CONFIG_RAMBOOTCOMMAND \ | |
617 | "setenv bootargs root=/dev/ram rw " \ | |
618 | "console=$consoledev,$baudrate $othbootargs;" \ | |
619 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
620 | "tftp $loadaddr $bootfile;" \ | |
621 | "tftp $fdtaddr $fdtfile;" \ | |
622 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
623 | ||
624 | #define CONFIG_BOOTCOMMAND CONFIG_LINUX | |
625 | ||
1cb19fbb | 626 | #include <asm/fsl_secure_boot.h> |
1cb19fbb YS |
627 | |
628 | #endif /* __CONFIG_H */ |