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0b2e13d9 CL |
1 | /* |
2 | * Copyright 2014 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | /* | |
8 | * T4240 RDB board configuration file | |
9 | */ | |
10 | #ifndef __CONFIG_H | |
11 | #define __CONFIG_H | |
12 | ||
13 | #define CONFIG_T4240RDB | |
9a509cf6 | 14 | #define CONFIG_DISPLAY_BOARDINFO |
0b2e13d9 CL |
15 | |
16 | #define CONFIG_FSL_SATA_V2 | |
17 | #define CONFIG_PCIE4 | |
18 | ||
19 | #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ | |
20 | ||
21 | #ifdef CONFIG_RAMBOOT_PBL | |
0b2e13d9 CL |
22 | #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg |
23 | #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_rcw.cfg | |
373762c3 CL |
24 | #ifndef CONFIG_SDCARD |
25 | #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE | |
26 | #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc | |
27 | #else | |
28 | #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT | |
373762c3 CL |
29 | #define CONFIG_SPL_SERIAL_SUPPORT |
30 | #define CONFIG_SPL_FLUSH_IMAGE | |
31 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
373762c3 CL |
32 | #define CONFIG_FSL_LAW /* Use common FSL init code */ |
33 | #define CONFIG_SYS_TEXT_BASE 0x00201000 | |
34 | #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 | |
35 | #define CONFIG_SPL_PAD_TO 0x40000 | |
36 | #define CONFIG_SPL_MAX_SIZE 0x28000 | |
37 | #define RESET_VECTOR_OFFSET 0x27FFC | |
38 | #define BOOT_PAGE_OFFSET 0x27000 | |
39 | ||
40 | #ifdef CONFIG_SDCARD | |
41 | #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC | |
373762c3 CL |
42 | #define CONFIG_SPL_MMC_MINIMAL |
43 | #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) | |
44 | #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 | |
45 | #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 | |
46 | #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) | |
47 | #ifndef CONFIG_SPL_BUILD | |
48 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
49 | #endif | |
50 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" | |
51 | #define CONFIG_SPL_MMC_BOOT | |
52 | #endif | |
53 | ||
54 | #ifdef CONFIG_SPL_BUILD | |
55 | #define CONFIG_SPL_SKIP_RELOCATE | |
56 | #define CONFIG_SPL_COMMON_INIT_DDR | |
57 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE | |
58 | #define CONFIG_SYS_NO_FLASH | |
59 | #endif | |
60 | ||
0b2e13d9 | 61 | #endif |
373762c3 | 62 | #endif /* CONFIG_RAMBOOT_PBL */ |
0b2e13d9 CL |
63 | |
64 | #define CONFIG_DDR_ECC | |
65 | ||
66 | #define CONFIG_CMD_REGINFO | |
67 | ||
68 | /* High Level Configuration Options */ | |
69 | #define CONFIG_BOOKE | |
70 | #define CONFIG_E500 /* BOOKE e500 family */ | |
71 | #define CONFIG_E500MC /* BOOKE e500mc family */ | |
72 | #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ | |
73 | #define CONFIG_MP /* support multiple processors */ | |
74 | ||
75 | #ifndef CONFIG_SYS_TEXT_BASE | |
76 | #define CONFIG_SYS_TEXT_BASE 0xeff40000 | |
77 | #endif | |
78 | ||
79 | #ifndef CONFIG_RESET_VECTOR_ADDRESS | |
80 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
81 | #endif | |
82 | ||
83 | #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ | |
84 | #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS | |
85 | #define CONFIG_FSL_IFC /* Enable IFC Support */ | |
737537ef | 86 | #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ |
0b2e13d9 | 87 | #define CONFIG_PCI /* Enable PCI/PCIE */ |
b38eaec5 RD |
88 | #define CONFIG_PCIE1 /* PCIE controller 1 */ |
89 | #define CONFIG_PCIE2 /* PCIE controller 2 */ | |
90 | #define CONFIG_PCIE3 /* PCIE controller 3 */ | |
0b2e13d9 CL |
91 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ |
92 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ | |
93 | ||
94 | #define CONFIG_FSL_LAW /* Use common FSL init code */ | |
95 | ||
96 | #define CONFIG_ENV_OVERWRITE | |
97 | ||
98 | /* | |
99 | * These can be toggled for performance analysis, otherwise use default. | |
100 | */ | |
101 | #define CONFIG_SYS_CACHE_STASHING | |
102 | #define CONFIG_BTB /* toggle branch predition */ | |
103 | #ifdef CONFIG_DDR_ECC | |
104 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
105 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
106 | #endif | |
107 | ||
108 | #define CONFIG_ENABLE_36BIT_PHYS | |
109 | ||
110 | #define CONFIG_ADDR_MAP | |
111 | #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ | |
112 | ||
113 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ | |
114 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
115 | #define CONFIG_SYS_ALT_MEMTEST | |
116 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ | |
117 | ||
118 | /* | |
119 | * Config the L3 Cache as L3 SRAM | |
120 | */ | |
373762c3 CL |
121 | #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 |
122 | #define CONFIG_SYS_L3_SIZE (512 << 10) | |
123 | #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) | |
124 | #ifdef CONFIG_RAMBOOT_PBL | |
125 | #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) | |
126 | #endif | |
127 | #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) | |
128 | #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) | |
129 | #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) | |
130 | #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) | |
0b2e13d9 CL |
131 | |
132 | #define CONFIG_SYS_DCSRBAR 0xf0000000 | |
133 | #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull | |
134 | ||
135 | /* | |
136 | * DDR Setup | |
137 | */ | |
138 | #define CONFIG_VERY_BIG_RAM | |
139 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
140 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
141 | ||
142 | /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ | |
143 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
144 | #define CONFIG_CHIP_SELECTS_PER_CTRL 4 | |
145 | #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE | |
146 | ||
147 | #define CONFIG_DDR_SPD | |
148 | #define CONFIG_SYS_FSL_DDR3 | |
149 | ||
0b2e13d9 CL |
150 | /* |
151 | * IFC Definitions | |
152 | */ | |
153 | #define CONFIG_SYS_FLASH_BASE 0xe0000000 | |
154 | #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) | |
155 | ||
373762c3 CL |
156 | #ifdef CONFIG_SPL_BUILD |
157 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE | |
158 | #else | |
0b2e13d9 | 159 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
373762c3 | 160 | #endif |
0b2e13d9 CL |
161 | |
162 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ | |
163 | #define CONFIG_MISC_INIT_R | |
164 | ||
165 | #define CONFIG_HWCONFIG | |
166 | ||
167 | /* define to use L1 as initial stack */ | |
168 | #define CONFIG_L1_INIT_RAM | |
169 | #define CONFIG_SYS_INIT_RAM_LOCK | |
170 | #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ | |
171 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf | |
b3142e2c | 172 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 |
0b2e13d9 CL |
173 | /* The assembler doesn't like typecast */ |
174 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ | |
175 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ | |
176 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) | |
177 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 | |
178 | ||
179 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ | |
180 | GENERATED_GBL_DATA_SIZE) | |
181 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
182 | ||
373762c3 | 183 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
0b2e13d9 CL |
184 | #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) |
185 | ||
186 | /* Serial Port - controlled on board with jumper J8 | |
187 | * open - index 2 | |
188 | * shorted - index 1 | |
189 | */ | |
190 | #define CONFIG_CONS_INDEX 1 | |
0b2e13d9 CL |
191 | #define CONFIG_SYS_NS16550_SERIAL |
192 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
193 | #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) | |
194 | ||
195 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
196 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
197 | ||
198 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) | |
199 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) | |
200 | #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) | |
201 | #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) | |
202 | ||
0b2e13d9 CL |
203 | /* I2C */ |
204 | #define CONFIG_SYS_I2C | |
205 | #define CONFIG_SYS_I2C_FSL | |
206 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
207 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 | |
208 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
209 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 | |
210 | ||
211 | /* | |
212 | * General PCI | |
213 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
214 | */ | |
215 | ||
216 | /* controller 1, direct to uli, tgtid 3, Base address 20000 */ | |
217 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 | |
218 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 | |
219 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull | |
220 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ | |
221 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 | |
222 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
223 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull | |
224 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
225 | ||
226 | /* controller 2, Slot 2, tgtid 2, Base address 201000 */ | |
227 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 | |
228 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 | |
229 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull | |
230 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ | |
231 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 | |
232 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
233 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull | |
234 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
235 | ||
236 | /* controller 3, Slot 1, tgtid 1, Base address 202000 */ | |
237 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 | |
238 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 | |
239 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull | |
240 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ | |
241 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 | |
242 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 | |
243 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull | |
244 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ | |
245 | ||
246 | /* controller 4, Base address 203000 */ | |
247 | #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 | |
248 | #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull | |
249 | #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ | |
250 | #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 | |
251 | #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull | |
252 | #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ | |
253 | ||
254 | #ifdef CONFIG_PCI | |
255 | #define CONFIG_PCI_INDIRECT_BRIDGE | |
0b2e13d9 | 256 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
0b2e13d9 CL |
257 | |
258 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
259 | #define CONFIG_DOS_PARTITION | |
260 | #endif /* CONFIG_PCI */ | |
261 | ||
262 | /* SATA */ | |
263 | #ifdef CONFIG_FSL_SATA_V2 | |
264 | #define CONFIG_LIBATA | |
265 | #define CONFIG_FSL_SATA | |
266 | ||
267 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 | |
268 | #define CONFIG_SATA1 | |
269 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR | |
270 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
271 | #define CONFIG_SATA2 | |
272 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR | |
273 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
274 | ||
275 | #define CONFIG_LBA48 | |
276 | #define CONFIG_CMD_SATA | |
277 | #define CONFIG_DOS_PARTITION | |
0b2e13d9 CL |
278 | #endif |
279 | ||
280 | #ifdef CONFIG_FMAN_ENET | |
281 | #define CONFIG_MII /* MII PHY management */ | |
282 | #define CONFIG_ETHPRIME "FM1@DTSEC1" | |
283 | #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ | |
284 | #endif | |
285 | ||
286 | /* | |
287 | * Environment | |
288 | */ | |
289 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
290 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
291 | ||
292 | /* | |
293 | * Command line configuration. | |
294 | */ | |
0b2e13d9 | 295 | #define CONFIG_CMD_ERRATA |
0b2e13d9 | 296 | #define CONFIG_CMD_IRQ |
0b2e13d9 CL |
297 | |
298 | #ifdef CONFIG_PCI | |
299 | #define CONFIG_CMD_PCI | |
0b2e13d9 CL |
300 | #endif |
301 | ||
302 | /* | |
303 | * Miscellaneous configurable options | |
304 | */ | |
305 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
306 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
307 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
308 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
309 | #ifdef CONFIG_CMD_KGDB | |
310 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
311 | #else | |
312 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
313 | #endif | |
314 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
315 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
316 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ | |
317 | ||
318 | /* | |
319 | * For booting Linux, the board info and command line data | |
320 | * have to be in the first 64 MB of memory, since this is | |
321 | * the maximum mapped by the Linux kernel during initialization. | |
322 | */ | |
323 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ | |
324 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
325 | ||
326 | #ifdef CONFIG_CMD_KGDB | |
327 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
328 | #endif | |
329 | ||
330 | /* | |
331 | * Environment Configuration | |
332 | */ | |
333 | #define CONFIG_ROOTPATH "/opt/nfsroot" | |
334 | #define CONFIG_BOOTFILE "uImage" | |
335 | #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ | |
336 | ||
337 | /* default location for tftp and bootm */ | |
338 | #define CONFIG_LOADADDR 1000000 | |
339 | ||
0b2e13d9 CL |
340 | #define CONFIG_BAUDRATE 115200 |
341 | ||
342 | #define CONFIG_HVBOOT \ | |
343 | "setenv bootargs config-addr=0x60000000; " \ | |
344 | "bootm 0x01000000 - 0x00f00000" | |
345 | ||
346 | #ifdef CONFIG_SYS_NO_FLASH | |
347 | #ifndef CONFIG_RAMBOOT_PBL | |
348 | #define CONFIG_ENV_IS_NOWHERE | |
349 | #endif | |
350 | #else | |
351 | #define CONFIG_FLASH_CFI_DRIVER | |
352 | #define CONFIG_SYS_FLASH_CFI | |
353 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
354 | #endif | |
355 | ||
356 | #if defined(CONFIG_SPIFLASH) | |
357 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
358 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
359 | #define CONFIG_ENV_SPI_BUS 0 | |
360 | #define CONFIG_ENV_SPI_CS 0 | |
361 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 | |
362 | #define CONFIG_ENV_SPI_MODE 0 | |
363 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ | |
364 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ | |
365 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
366 | #elif defined(CONFIG_SDCARD) | |
367 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
368 | #define CONFIG_ENV_IS_IN_MMC | |
369 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
370 | #define CONFIG_ENV_SIZE 0x2000 | |
373762c3 | 371 | #define CONFIG_ENV_OFFSET (512 * 0x800) |
0b2e13d9 CL |
372 | #elif defined(CONFIG_NAND) |
373 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
374 | #define CONFIG_ENV_IS_IN_NAND | |
375 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE | |
376 | #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) | |
377 | #elif defined(CONFIG_ENV_IS_NOWHERE) | |
378 | #define CONFIG_ENV_SIZE 0x2000 | |
379 | #else | |
380 | #define CONFIG_ENV_IS_IN_FLASH | |
381 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
382 | #define CONFIG_ENV_SIZE 0x2000 | |
383 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
384 | #endif | |
385 | ||
386 | #define CONFIG_SYS_CLK_FREQ 66666666 | |
387 | #define CONFIG_DDR_CLK_FREQ 133333333 | |
388 | ||
389 | #ifndef __ASSEMBLY__ | |
390 | unsigned long get_board_sys_clk(void); | |
391 | unsigned long get_board_ddr_clk(void); | |
392 | #endif | |
393 | ||
394 | /* | |
395 | * DDR Setup | |
396 | */ | |
397 | #define CONFIG_SYS_SPD_BUS_NUM 0 | |
398 | #define SPD_EEPROM_ADDRESS1 0x52 | |
399 | #define SPD_EEPROM_ADDRESS2 0x54 | |
400 | #define SPD_EEPROM_ADDRESS3 0x56 | |
401 | #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ | |
402 | #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ | |
403 | ||
404 | /* | |
405 | * IFC Definitions | |
406 | */ | |
407 | #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) | |
408 | #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ | |
409 | + 0x8000000) | \ | |
410 | CSPR_PORT_SIZE_16 | \ | |
411 | CSPR_MSEL_NOR | \ | |
412 | CSPR_V) | |
413 | #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) | |
414 | #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
415 | CSPR_PORT_SIZE_16 | \ | |
416 | CSPR_MSEL_NOR | \ | |
417 | CSPR_V) | |
418 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) | |
419 | /* NOR Flash Timing Params */ | |
420 | #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 | |
421 | ||
422 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ | |
423 | FTIM0_NOR_TEADC(0x5) | \ | |
424 | FTIM0_NOR_TEAHC(0x5)) | |
425 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ | |
426 | FTIM1_NOR_TRAD_NOR(0x1A) |\ | |
427 | FTIM1_NOR_TSEQRAD_NOR(0x13)) | |
428 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ | |
429 | FTIM2_NOR_TCH(0x4) | \ | |
430 | FTIM2_NOR_TWPH(0x0E) | \ | |
431 | FTIM2_NOR_TWP(0x1c)) | |
432 | #define CONFIG_SYS_NOR_FTIM3 0x0 | |
433 | ||
434 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
435 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
436 | ||
437 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
438 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
439 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
440 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
441 | ||
442 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
443 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ | |
444 | + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} | |
445 | ||
446 | /* NAND Flash on IFC */ | |
447 | #define CONFIG_NAND_FSL_IFC | |
448 | #define CONFIG_SYS_NAND_MAX_ECCPOS 256 | |
449 | #define CONFIG_SYS_NAND_MAX_OOBFREE 2 | |
450 | #define CONFIG_SYS_NAND_BASE 0xff800000 | |
451 | #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) | |
452 | ||
453 | #define CONFIG_SYS_NAND_CSPR_EXT (0xf) | |
454 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
455 | | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | |
456 | | CSPR_MSEL_NAND /* MSEL = NAND */ \ | |
457 | | CSPR_V) | |
458 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) | |
459 | ||
460 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | |
461 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
462 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
463 | | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ | |
464 | | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ | |
465 | | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ | |
466 | | CSOR_NAND_PB(128)) /*Page Per Block = 128*/ | |
467 | ||
468 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
469 | ||
470 | /* ONFI NAND Flash mode0 Timing Params */ | |
471 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ | |
472 | FTIM0_NAND_TWP(0x18) | \ | |
473 | FTIM0_NAND_TWCHT(0x07) | \ | |
474 | FTIM0_NAND_TWH(0x0a)) | |
475 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ | |
476 | FTIM1_NAND_TWBE(0x39) | \ | |
477 | FTIM1_NAND_TRR(0x0e) | \ | |
478 | FTIM1_NAND_TRP(0x18)) | |
479 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ | |
480 | FTIM2_NAND_TREH(0x0a) | \ | |
481 | FTIM2_NAND_TWHRE(0x1e)) | |
482 | #define CONFIG_SYS_NAND_FTIM3 0x0 | |
483 | ||
484 | #define CONFIG_SYS_NAND_DDR_LAW 11 | |
485 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
486 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
0b2e13d9 CL |
487 | #define CONFIG_CMD_NAND |
488 | ||
489 | #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) | |
490 | ||
491 | #if defined(CONFIG_NAND) | |
492 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT | |
493 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR | |
494 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
495 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
496 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
497 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
498 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
499 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
500 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
501 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR | |
502 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK | |
503 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR | |
504 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
505 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
506 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
507 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
508 | #else | |
509 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
510 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR | |
511 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
512 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
513 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
514 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
515 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
516 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
517 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT | |
518 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR | |
519 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK | |
520 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR | |
521 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
522 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
523 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
524 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
525 | #endif | |
526 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT | |
527 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR | |
528 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK | |
529 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR | |
530 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
531 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
532 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
533 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
534 | ||
ab06b236 CL |
535 | /* CPLD on IFC */ |
536 | #define CONFIG_SYS_CPLD_BASE 0xffdf0000 | |
537 | #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) | |
538 | #define CONFIG_SYS_CSPR3_EXT (0xf) | |
539 | #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ | |
540 | | CSPR_PORT_SIZE_8 \ | |
541 | | CSPR_MSEL_GPCM \ | |
542 | | CSPR_V) | |
543 | ||
544 | #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) | |
545 | #define CONFIG_SYS_CSOR3 0x0 | |
546 | ||
547 | /* CPLD Timing parameters for IFC CS3 */ | |
548 | #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ | |
549 | FTIM0_GPCM_TEADC(0x0e) | \ | |
550 | FTIM0_GPCM_TEAHC(0x0e)) | |
551 | #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ | |
552 | FTIM1_GPCM_TRAD(0x1f)) | |
553 | #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ | |
1b5c2b51 | 554 | FTIM2_GPCM_TCH(0x8) | \ |
ab06b236 CL |
555 | FTIM2_GPCM_TWP(0x1f)) |
556 | #define CONFIG_SYS_CS3_FTIM3 0x0 | |
557 | ||
0b2e13d9 CL |
558 | #if defined(CONFIG_RAMBOOT_PBL) |
559 | #define CONFIG_SYS_RAMBOOT | |
560 | #endif | |
561 | ||
0b2e13d9 CL |
562 | /* I2C */ |
563 | #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ | |
564 | #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ | |
565 | #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ | |
566 | #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ | |
567 | ||
568 | #define I2C_MUX_CH_DEFAULT 0x8 | |
569 | #define I2C_MUX_CH_VOL_MONITOR 0xa | |
570 | #define I2C_MUX_CH_VSC3316_FS 0xc | |
571 | #define I2C_MUX_CH_VSC3316_BS 0xd | |
572 | ||
573 | /* Voltage monitor on channel 2*/ | |
574 | #define I2C_VOL_MONITOR_ADDR 0x40 | |
575 | #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 | |
576 | #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 | |
577 | #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 | |
578 | ||
2f66a828 YZ |
579 | #define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv" |
580 | #ifndef CONFIG_SPL_BUILD | |
581 | #define CONFIG_VID | |
582 | #endif | |
583 | #define CONFIG_VOL_MONITOR_IR36021_SET | |
584 | #define CONFIG_VOL_MONITOR_IR36021_READ | |
585 | /* The lowest and highest voltage allowed for T4240RDB */ | |
586 | #define VDD_MV_MIN 819 | |
587 | #define VDD_MV_MAX 1212 | |
588 | ||
0b2e13d9 CL |
589 | /* |
590 | * eSPI - Enhanced SPI | |
591 | */ | |
0b2e13d9 CL |
592 | #define CONFIG_SF_DEFAULT_SPEED 10000000 |
593 | #define CONFIG_SF_DEFAULT_MODE 0 | |
594 | ||
0b2e13d9 CL |
595 | /* Qman/Bman */ |
596 | #ifndef CONFIG_NOBQFMAN | |
597 | #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ | |
598 | #define CONFIG_SYS_BMAN_NUM_PORTALS 50 | |
599 | #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 | |
600 | #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull | |
601 | #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 | |
3fa66db4 JL |
602 | #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 |
603 | #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 | |
604 | #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE | |
605 | #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
606 | #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ | |
607 | CONFIG_SYS_BMAN_CENA_SIZE) | |
608 | #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
609 | #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 | |
0b2e13d9 CL |
610 | #define CONFIG_SYS_QMAN_NUM_PORTALS 50 |
611 | #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 | |
612 | #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull | |
613 | #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 | |
3fa66db4 JL |
614 | #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 |
615 | #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 | |
616 | #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE | |
617 | #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
618 | #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ | |
619 | CONFIG_SYS_QMAN_CENA_SIZE) | |
620 | #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
621 | #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 | |
0b2e13d9 CL |
622 | |
623 | #define CONFIG_SYS_DPAA_FMAN | |
624 | #define CONFIG_SYS_DPAA_PME | |
625 | #define CONFIG_SYS_PMAN | |
626 | #define CONFIG_SYS_DPAA_DCE | |
627 | #define CONFIG_SYS_DPAA_RMAN | |
628 | #define CONFIG_SYS_INTERLAKEN | |
629 | ||
630 | /* Default address of microcode for the Linux Fman driver */ | |
631 | #if defined(CONFIG_SPIFLASH) | |
632 | /* | |
633 | * env is stored at 0x100000, sector size is 0x10000, ucode is stored after | |
634 | * env, so we got 0x110000. | |
635 | */ | |
636 | #define CONFIG_SYS_QE_FW_IN_SPIFLASH | |
637 | #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 | |
638 | #elif defined(CONFIG_SDCARD) | |
639 | /* | |
640 | * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is | |
373762c3 CL |
641 | * about 1MB (2048 blocks), Env is stored after the image, and the env size is |
642 | * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. | |
0b2e13d9 CL |
643 | */ |
644 | #define CONFIG_SYS_QE_FMAN_FW_IN_MMC | |
373762c3 | 645 | #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) |
0b2e13d9 CL |
646 | #elif defined(CONFIG_NAND) |
647 | #define CONFIG_SYS_QE_FMAN_FW_IN_NAND | |
648 | #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) | |
649 | #else | |
650 | #define CONFIG_SYS_QE_FMAN_FW_IN_NOR | |
651 | #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 | |
652 | #endif | |
653 | #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 | |
654 | #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) | |
655 | #endif /* CONFIG_NOBQFMAN */ | |
656 | ||
657 | #ifdef CONFIG_SYS_DPAA_FMAN | |
658 | #define CONFIG_FMAN_ENET | |
659 | #define CONFIG_PHYLIB_10G | |
660 | #define CONFIG_PHY_VITESSE | |
661 | #define CONFIG_PHY_CORTINA | |
a8efe79c | 662 | #define CONFIG_SYS_CORTINA_FW_IN_NOR |
0b2e13d9 CL |
663 | #define CONFIG_CORTINA_FW_ADDR 0xefe00000 |
664 | #define CONFIG_CORTINA_FW_LENGTH 0x40000 | |
665 | #define CONFIG_PHY_TERANETICS | |
666 | #define SGMII_PHY_ADDR1 0x0 | |
667 | #define SGMII_PHY_ADDR2 0x1 | |
668 | #define SGMII_PHY_ADDR3 0x2 | |
669 | #define SGMII_PHY_ADDR4 0x3 | |
670 | #define SGMII_PHY_ADDR5 0x4 | |
671 | #define SGMII_PHY_ADDR6 0x5 | |
672 | #define SGMII_PHY_ADDR7 0x6 | |
673 | #define SGMII_PHY_ADDR8 0x7 | |
674 | #define FM1_10GEC1_PHY_ADDR 0x10 | |
675 | #define FM1_10GEC2_PHY_ADDR 0x11 | |
676 | #define FM2_10GEC1_PHY_ADDR 0x12 | |
677 | #define FM2_10GEC2_PHY_ADDR 0x13 | |
678 | #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR | |
679 | #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR | |
680 | #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR | |
681 | #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR | |
682 | #endif | |
683 | ||
0b2e13d9 CL |
684 | /* SATA */ |
685 | #ifdef CONFIG_FSL_SATA_V2 | |
686 | #define CONFIG_LIBATA | |
687 | #define CONFIG_FSL_SATA | |
688 | ||
689 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 | |
690 | #define CONFIG_SATA1 | |
691 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR | |
692 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
693 | #define CONFIG_SATA2 | |
694 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR | |
695 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
696 | ||
697 | #define CONFIG_LBA48 | |
698 | #define CONFIG_CMD_SATA | |
699 | #define CONFIG_DOS_PARTITION | |
0b2e13d9 CL |
700 | #endif |
701 | ||
702 | #ifdef CONFIG_FMAN_ENET | |
703 | #define CONFIG_MII /* MII PHY management */ | |
704 | #define CONFIG_ETHPRIME "FM1@DTSEC1" | |
705 | #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ | |
706 | #endif | |
707 | ||
708 | /* | |
709 | * USB | |
710 | */ | |
0b2e13d9 CL |
711 | #define CONFIG_USB_EHCI |
712 | #define CONFIG_USB_EHCI_FSL | |
713 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
0b2e13d9 CL |
714 | #define CONFIG_HAS_FSL_DR_USB |
715 | ||
716 | #define CONFIG_MMC | |
717 | ||
718 | #ifdef CONFIG_MMC | |
719 | #define CONFIG_FSL_ESDHC | |
720 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
721 | #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT | |
0b2e13d9 | 722 | #define CONFIG_GENERIC_MMC |
0b2e13d9 | 723 | #define CONFIG_DOS_PARTITION |
929dfdc2 | 724 | #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 |
0b2e13d9 CL |
725 | #endif |
726 | ||
737537ef RG |
727 | /* Hash command with SHA acceleration supported in hardware */ |
728 | #ifdef CONFIG_FSL_CAAM | |
729 | #define CONFIG_CMD_HASH | |
730 | #define CONFIG_SHA_HW_ACCEL | |
731 | #endif | |
732 | ||
0b2e13d9 CL |
733 | |
734 | #define __USB_PHY_TYPE utmi | |
735 | ||
736 | /* | |
737 | * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be | |
738 | * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way | |
739 | * interleaving. It can be cacheline, page, bank, superbank. | |
740 | * See doc/README.fsl-ddr for details. | |
741 | */ | |
1a344456 | 742 | #ifdef CONFIG_PPC_T4240 |
0b2e13d9 | 743 | #define CTRL_INTLV_PREFERED 3way_4KB |
1a344456 CL |
744 | #else |
745 | #define CTRL_INTLV_PREFERED cacheline | |
746 | #endif | |
0b2e13d9 CL |
747 | |
748 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
749 | "hwconfig=fsl_ddr:" \ | |
750 | "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ | |
751 | "bank_intlv=auto;" \ | |
752 | "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ | |
753 | "netdev=eth0\0" \ | |
754 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ | |
755 | "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ | |
756 | "tftpflash=tftpboot $loadaddr $uboot && " \ | |
757 | "protect off $ubootaddr +$filesize && " \ | |
758 | "erase $ubootaddr +$filesize && " \ | |
759 | "cp.b $loadaddr $ubootaddr $filesize && " \ | |
760 | "protect on $ubootaddr +$filesize && " \ | |
761 | "cmp.b $loadaddr $ubootaddr $filesize\0" \ | |
762 | "consoledev=ttyS0\0" \ | |
763 | "ramdiskaddr=2000000\0" \ | |
764 | "ramdiskfile=t4240rdb/ramdisk.uboot\0" \ | |
b24a4f62 | 765 | "fdtaddr=1e00000\0" \ |
0b2e13d9 CL |
766 | "fdtfile=t4240rdb/t4240rdb.dtb\0" \ |
767 | "bdev=sda3\0" | |
768 | ||
769 | #define CONFIG_HVBOOT \ | |
770 | "setenv bootargs config-addr=0x60000000; " \ | |
771 | "bootm 0x01000000 - 0x00f00000" | |
772 | ||
773 | #define CONFIG_LINUX \ | |
774 | "setenv bootargs root=/dev/ram rw " \ | |
775 | "console=$consoledev,$baudrate $othbootargs;" \ | |
776 | "setenv ramdiskaddr 0x02000000;" \ | |
777 | "setenv fdtaddr 0x00c00000;" \ | |
778 | "setenv loadaddr 0x1000000;" \ | |
779 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
780 | ||
781 | #define CONFIG_HDBOOT \ | |
782 | "setenv bootargs root=/dev/$bdev rw " \ | |
783 | "console=$consoledev,$baudrate $othbootargs;" \ | |
784 | "tftp $loadaddr $bootfile;" \ | |
785 | "tftp $fdtaddr $fdtfile;" \ | |
786 | "bootm $loadaddr - $fdtaddr" | |
787 | ||
788 | #define CONFIG_NFSBOOTCOMMAND \ | |
789 | "setenv bootargs root=/dev/nfs rw " \ | |
790 | "nfsroot=$serverip:$rootpath " \ | |
791 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
792 | "console=$consoledev,$baudrate $othbootargs;" \ | |
793 | "tftp $loadaddr $bootfile;" \ | |
794 | "tftp $fdtaddr $fdtfile;" \ | |
795 | "bootm $loadaddr - $fdtaddr" | |
796 | ||
797 | #define CONFIG_RAMBOOTCOMMAND \ | |
798 | "setenv bootargs root=/dev/ram rw " \ | |
799 | "console=$consoledev,$baudrate $othbootargs;" \ | |
800 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
801 | "tftp $loadaddr $bootfile;" \ | |
802 | "tftp $fdtaddr $fdtfile;" \ | |
803 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
804 | ||
805 | #define CONFIG_BOOTCOMMAND CONFIG_LINUX | |
806 | ||
807 | #include <asm/fsl_secure_boot.h> | |
808 | ||
0b2e13d9 | 809 | #endif /* __CONFIG_H */ |