[people/ms/u-boot.git] / include / configs / TB5200.h

/*
 * (C) Copyright 2003-2006
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2004-2006
 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
#define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU) */
#define CONFIG_TQM5200		1	/* ... on TQM5200 module */
#define CONFIG_TB5200		1	/* ... on a TB5200 base board */

/*
 * Valid values for CONFIG_SYS_TEXT_BASE are:
 * 0xFC000000	boot low (standard configuration with room for
 *		max 64 MByte Flash ROM)
 * 0xFFF00000	boot high (for a backup copy of U-Boot)
 * 0x00100000	boot from RAM (for testing only)
 */
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE	0xFC000000
#endif

#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */

#define CONFIG_HIGH_BATS	1	/* High BATs supported */

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* default console is on PSC1 */
#define CONFIG_SERIAL_MULTI	1	/* support multiple consoles */
#define CONFIG_PSC_CONSOLE2	6	/* second console is on PSC6 */
#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

/*
 * Video console
 */
#if 1
#define CONFIG_VIDEO
#define CONFIG_VIDEO_SM501
#define CONFIG_VIDEO_SM501_32BPP
#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_LOGO
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_CONSOLE_EXTRA_INFO
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#endif

/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION

/* USB */
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE

/* POST support */
#define CONFIG_POST		(CONFIG_SYS_POST_MEMORY   | \
				 CONFIG_SYS_POST_CPU	   | \
				 CONFIG_SYS_POST_I2C)

#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
#endif


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_BSP
#define CONFIG_CMD_USB

#ifdef CONFIG_VIDEO
#define CONFIG_CMD_BMP
#endif

#ifdef CONFIG_POST
#define CONFIG_CMD_DIAG
#endif


#define	CONFIG_TIMESTAMP		/* display image timestamps */

#if (CONFIG_SYS_TEXT_BASE == 0xFC000000)		/* Boot low */
#   define CONFIG_SYS_LOWBOOT		1
#endif

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */

#define CONFIG_PREBOOT	"echo;" \
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#if defined(CONFIG_TQM5200_B)
#define CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"rootpath=/opt/eldk/ppc_6xx\0"					\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"flash_self=run ramargs addip;"					\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"flash_nfs=run nfsargs addip;"					\
		"bootm ${kernel_addr}\0"				\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
	"bootfile=/tftpboot/tqm5200/uImage\0"				\
	"load=tftp 200000 ${u-boot}\0"					\
	"u-boot=/tftpboot/tqm5200/u-boot.bin\0"				\
	"update=protect off FC000000 FC07FFFF;"				\
		"erase FC000000 FC07FFFF;"				\
		"cp.b 200000 FC000000 ${filesize};"			\
		"protect on FC000000 FC07FFFF\0"			\
	""
#else
#define CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"rootpath=/opt/eldk/ppc_6xx\0"					\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"flash_self=run ramargs addip;"					\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"flash_nfs=run nfsargs addip;"					\
		"bootm ${kernel_addr}\0"				\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
	"bootfile=/tftpboot/tqm5200/uImage\0"				\
	"load=tftp 200000 $(u-boot)\0"					\
	"u-boot=/tftpboot/tqm5200/u-boot.bin\0"				\
	"update=protect off FC000000 FC05FFFF;"				\
		"erase FC000000 FC05FFFF;"				\
		"cp.b 200000 FC000000 ${filesize};"			\
		"protect on FC000000 FC05FFFF\0"			\
	""
#endif /* CONFIG_TQM5200_B */

#define CONFIG_BOOTCOMMAND	"run net_nfs"

/*
 * IPB Bus clocking configuration.
 */
#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */

#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
/*
 * PCI Bus clocking configuration
 *
 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
 * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
 * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
 */
#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2		/* define for 66MHz speed */
#endif

/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #2 */

/*
 * I2C clock frequency
 *
 * Please notice, that the resulting clock frequency could differ from the
 * configured value. This is because the I2C clock is derived from system
 * clock over a frequency divider with only a few divider values. U-boot
 * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
 * approximation allways lies below the configured value, never above.
 */
#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE		0x7F

/*
 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
 * also). For other EEPROMs configuration should be verified. On Mini-FAP the
 * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
 * same configuration could be used.
 */
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20

/* List of I2C addresses to be verified by POST */
#undef CONFIG_SYS_POST_I2C_ADDRS
#define CONFIG_SYS_POST_I2C_ADDRS	{CONFIG_SYS_I2C_EEPROM_ADDR,	\
					 CONFIG_SYS_I2C_RTC_ADDR,	\
					 CONFIG_SYS_I2C_SLAVE}

/*
 * Flash configuration
 */
#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_TEXT_BASE /* 0xFC000000 */

/* use CFI flash driver */
#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_BOOTCS_START }
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_SIZE		0x04000000 /* 64 MByte */
#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sects on one chip */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1

#if !defined(CONFIG_SYS_LOWBOOT)
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
#else	/* CONFIG_SYS_LOWBOOT */
#if defined(CONFIG_TQM5200_B)
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00080000)
#else
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00060000)
#endif /* CONFIG_TQM5200_B */
#endif	/* CONFIG_SYS_LOWBOOT */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks
					   (= chip selects) */

/* Dynamic MTD partition support */
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT		"nor0=TQM5200-0"
#if defined(CONFIG_TQM5200_B)
#define MTDPARTS_DEFAULT	"mtdparts=TQM5200-0:768k(firmware),"	\
						"1280k(kernel),"	\
						"2m(initrd),"		\
						"4m(small-fs),"		\
						"16m(big-fs),"		\
						"8m(misc)"
#else
#define MTDPARTS_DEFAULT	"mtdparts=TQM5200-0:640k(firmware),"	\
						"1408k(kernel),"	\
						"2m(initrd),"		\
						"4m(small-fs),"		\
						"16m(big-fs),"		\
						"8m(misc)"
#endif /* CONFIG_TQM5200_B */

/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_SIZE		0x10000
#if defined(CONFIG_TQM5200_B)
#define CONFIG_ENV_SECT_SIZE	0x40000
#else
#define CONFIG_ENV_SECT_SIZE	0x20000
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
#endif /* CONFIG_TQM5200_B */

/*
 * Memory map
 */
#define CONFIG_SYS_MBAR		0xF0000000
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_DEFAULT_MBAR	0x80000000

/* Use ON-Chip SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
#else
#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE
#endif


#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#   define CONFIG_SYS_RAMBOOT		1
#endif

#if defined(CONFIG_TQM5200_B)
#define CONFIG_SYS_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor	*/
#else
#define CONFIG_SYS_MONITOR_LEN		(384 << 10)	/* Reserve 384 kB for Monitor	*/
#endif /* CONFIG_TQM5200_B */
#define CONFIG_SYS_MALLOC_LEN		(1024 << 10)	/* Reserve 1024 kB for malloc()	*/
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
#define CONFIG_MPC5xxx_FEC_MII100
/*
 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
 */
/* #define CONFIG_MPC5xxx_FEC_MII10 */
#define CONFIG_PHY_ADDR		0x00

/*
 * GPIO configuration
 *
 * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
 *	Bit 0 (mask: 0x80000000): 1
 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
 *	00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
 *	01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
 *	      Use for REV200 STK52XX boards. Do not use with REV100 modules
 *	      (because, there I2C1 is used as I2C bus)
 * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
 * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
 *	000 -> All PSC2 pins are GIOPs
 *	001 -> CAN1/2 on PSC2 pins
 *	       Use for REV100 STK52xx boards
 * use PSC3: Bits 20:23 (mask: 0x00000300):
 *      0001 -> USB2
 *      0000 -> GPIO
 * use PSC6:
 *   on STK52xx:
 *	use as UART. Pins PSC6_0 to PSC6_3 are used.
 *	Bits 9:11 (mask: 0x00700000):
 *	   101 -> PSC6 : Extended POST test is not available
 *   on MINI-FAP and TQM5200_IB:
 *	use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
 *	   000 -> PSC6 could not be used as UART, CODEC or IrDA
 *   GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
 *   tests.
 */
#define CONFIG_SYS_GPS_PORT_CONFIG	0x81500114

/*
 * RTC configuration
 */
#define CONFIG_RTC_M41T11	1
#define CONFIG_SYS_I2C_RTC_ADDR	0x68
#define CONFIG_SYS_M41T11_BASE_YEAR	1900    /* because Linux uses the same base
					   year */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
#define CONFIG_CMDLINE_EDITING	1	/* add command line history */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/* Enable an alternate, more extensive memory test */
#define CONFIG_SYS_ALT_MEMTEST

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */

#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */

/*
 * Enable loopw command.
 */
#define CONFIG_LOOPW

/*
 * Various low-level settings
 */
#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL		HID0_ICE

#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
#define CONFIG_SYS_BOOTCS_CFG		0x0008DF30 /* for pci_clk  = 66 MHz */
#else
#define CONFIG_SYS_BOOTCS_CFG		0x0004DF30 /* for pci_clk = 33 MHz */
#endif
#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE

#define CONFIG_LAST_STAGE_INIT

/*
 * SRAM - Do not map below 2 GB in address space, because this area is used
 * for SDRAM autosizing.
 */
#define CONFIG_SYS_CS2_START		0xE5000000
#define CONFIG_SYS_CS2_SIZE		0x100000	/* 1 MByte */
#define CONFIG_SYS_CS2_CFG		0x0004D930

/*
 * Grafic controller - Do not map below 2 GB in address space, because this
 * area is used for SDRAM autosizing.
 */
#define SM501_FB_BASE		0xE0000000
#define CONFIG_SYS_CS1_START		(SM501_FB_BASE)
#define CONFIG_SYS_CS1_SIZE		0x4000000	/* 64 MByte */
#define CONFIG_SYS_CS1_CFG		0x8F48FF70
#define SM501_MMIO_BASE		CONFIG_SYS_CS1_START + 0x03E00000

#define CONFIG_SYS_CS_BURST		0x00000000
#define CONFIG_SYS_CS_DEADCYCLE	0x33333311	/* 1 dead cycle for flash and SM501 */

#define CONFIG_SYS_RESET_ADDRESS	0xff000000

/*-----------------------------------------------------------------------
 * USB stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_USB_CLOCK	0x0001BBBB
#define CONFIG_USB_CONFIG	0x00001000

/*-----------------------------------------------------------------------
 * IDE/ATA stuff Supports IDE harddisk
 *-----------------------------------------------------------------------
 */

#undef	CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card Adapter */

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/

#define CONFIG_IDE_RESET		/* reset for ide supported	*/
#define CONFIG_IDE_PREINIT

#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 2 drives per IDE bus	*/

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA

/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)

/* Offset for normal register accesses	*/
#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)

/* Offset for alternate registers	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)

/* Interval between registers						     */
#define CONFIG_SYS_ATA_STRIDE		4

#endif /* __CONFIG_H */
Commit	Line	Data
b87dfd28 WD	1	/*
	2	* (C) Copyright 2003-2006
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* (C) Copyright 2004-2006
	6	* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#ifndef __CONFIG_H
	28	#define __CONFIG_H
	29
	30	/*
	31	* High Level Configuration Options
	32	* (easy to change)
	33	*/
	34
	35	#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
	36	#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
	37	#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
	38	#define CONFIG_TB5200 1 /* ... on a TB5200 base board */
	39
2ae18241 WD	40	/*
	41	* Valid values for CONFIG_SYS_TEXT_BASE are:
	42	* 0xFC000000 boot low (standard configuration with room for
	43	* max 64 MByte Flash ROM)
	44	* 0xFFF00000 boot high (for a backup copy of U-Boot)
	45	* 0x00100000 boot from RAM (for testing only)
	46	*/
	47	#ifndef CONFIG_SYS_TEXT_BASE
	48	#define CONFIG_SYS_TEXT_BASE 0xFC000000
	49	#endif
	50
6d0f6bcf	51	#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
b87dfd28	52
31d82672 BB	53	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
31d82672 BB	54
b87dfd28 WD	55	/*
	56	* Serial console configuration
	57	*/
	58	#define CONFIG_PSC_CONSOLE 1 /* default console is on PSC1 */
	59	#define CONFIG_SERIAL_MULTI 1 /* support multiple consoles */
	60	#define CONFIG_PSC_CONSOLE2 6 /* second console is on PSC6 */
	61	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
6d0f6bcf	62	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
b87dfd28 WD	63
	64	/*
	65	* Video console
	66	*/
	67	#if 1
	68	#define CONFIG_VIDEO
	69	#define CONFIG_VIDEO_SM501
	70	#define CONFIG_VIDEO_SM501_32BPP
	71	#define CONFIG_CFB_CONSOLE
	72	#define CONFIG_VIDEO_LOGO
	73	#define CONFIG_VGA_AS_SINGLE_DEVICE
	74	#define CONFIG_CONSOLE_EXTRA_INFO
	75	#define CONFIG_VIDEO_SW_CURSOR
	76	#define CONFIG_SPLASH_SCREEN
6d0f6bcf	77	#define CONFIG_SYS_CONSOLE_IS_IN_ENV
b87dfd28 WD	78	#endif
b87dfd28 WD	79
b87dfd28 WD	80	/* Partitions */
	81	#define CONFIG_MAC_PARTITION
	82	#define CONFIG_DOS_PARTITION
	83	#define CONFIG_ISO_PARTITION
	84
	85	/* USB */
	86	#define CONFIG_USB_OHCI
b87dfd28 WD	87	#define CONFIG_USB_STORAGE
	88
	89	/* POST support */
6d0f6bcf JCPV	90	#define CONFIG_POST (CONFIG_SYS_POST_MEMORY \| \
	91	CONFIG_SYS_POST_CPU \| \
	92	CONFIG_SYS_POST_I2C)
b87dfd28 WD	93
b87dfd28 WD	94	#ifdef CONFIG_POST
b87dfd28 WD	95	/* preserve space for the post_word at end of on-chip SRAM */
b87dfd28 WD	96	#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
b87dfd28 WD	97	#endif
b87dfd28 WD	98
b87dfd28	99
a1aa0bb5 JL	100	/*
	101	* BOOTP options
	102	*/
	103	#define CONFIG_BOOTP_BOOTFILESIZE
	104	#define CONFIG_BOOTP_BOOTPATH
	105	#define CONFIG_BOOTP_GATEWAY
	106	#define CONFIG_BOOTP_HOSTNAME
	107
	108
b87dfd28	109	/*
d794cfef	110	* Command line configuration.
b87dfd28	111	*/
d794cfef JL	112	#include <config_cmd_default.h>
d794cfef JL	113
d794cfef JL	114	#define CONFIG_CMD_ASKENV
	115	#define CONFIG_CMD_DATE
	116	#define CONFIG_CMD_DHCP
	117	#define CONFIG_CMD_ECHO
	118	#define CONFIG_CMD_EEPROM
	119	#define CONFIG_CMD_EXT2
	120	#define CONFIG_CMD_FAT
	121	#define CONFIG_CMD_I2C
	122	#define CONFIG_CMD_IDE
	123	#define CONFIG_CMD_JFFS2
	124	#define CONFIG_CMD_MII
	125	#define CONFIG_CMD_NFS
	126	#define CONFIG_CMD_PING
d794cfef JL	127	#define CONFIG_CMD_REGINFO
	128	#define CONFIG_CMD_SNTP
	129	#define CONFIG_CMD_BSP
	130	#define CONFIG_CMD_USB
	131
af075ee9 JL	132	#ifdef CONFIG_VIDEO
	133	#define CONFIG_CMD_BMP
	134	#endif
	135
	136	#ifdef CONFIG_POST
800eb096	137	#define CONFIG_CMD_DIAG
af075ee9 JL	138	#endif
af075ee9 JL	139
b87dfd28 WD	140
	141	#define CONFIG_TIMESTAMP /* display image timestamps */
	142
14d0a02a	143	#if (CONFIG_SYS_TEXT_BASE == 0xFC000000) /* Boot low */
6d0f6bcf	144	# define CONFIG_SYS_LOWBOOT 1
b87dfd28 WD	145	#endif
	146
	147	/*
	148	* Autobooting
	149	*/
	150	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	151
	152	#define CONFIG_PREBOOT "echo;" \
32bf3d14	153	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
b87dfd28 WD	154	"echo"
	155
	156	#undef CONFIG_BOOTARGS
	157
45a212c4 WD	158	#if defined(CONFIG_TQM5200_B)
	159	#define CONFIG_EXTRA_ENV_SETTINGS \
	160	"netdev=eth0\0" \
	161	"rootpath=/opt/eldk/ppc_6xx\0" \
	162	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	163	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	164	"nfsroot=${serverip}:${rootpath}\0" \
	165	"addip=setenv bootargs ${bootargs} " \
	166	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	167	":${hostname}:${netdev}:off panic=1\0" \
	168	"flash_self=run ramargs addip;" \
	169	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
	170	"flash_nfs=run nfsargs addip;" \
	171	"bootm ${kernel_addr}\0" \
	172	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
	173	"bootfile=/tftpboot/tqm5200/uImage\0" \
	174	"load=tftp 200000 ${u-boot}\0" \
	175	"u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
	176	"update=protect off FC000000 FC07FFFF;" \
	177	"erase FC000000 FC07FFFF;" \
	178	"cp.b 200000 FC000000 ${filesize};" \
	179	"protect on FC000000 FC07FFFF\0" \
	180	""
	181	#else
b87dfd28 WD	182	#define CONFIG_EXTRA_ENV_SETTINGS \
	183	"netdev=eth0\0" \
	184	"rootpath=/opt/eldk/ppc_6xx\0" \
	185	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	186	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	187	"nfsroot=${serverip}:${rootpath}\0" \
	188	"addip=setenv bootargs ${bootargs} " \
	189	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	190	":${hostname}:${netdev}:off panic=1\0" \
	191	"flash_self=run ramargs addip;" \
	192	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
	193	"flash_nfs=run nfsargs addip;" \
	194	"bootm ${kernel_addr}\0" \
	195	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
	196	"bootfile=/tftpboot/tqm5200/uImage\0" \
	197	"load=tftp 200000 $(u-boot)\0" \
	198	"u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
	199	"update=protect off FC000000 FC05FFFF;" \
	200	"erase FC000000 FC05FFFF;" \
	201	"cp.b 200000 FC000000 ${filesize};" \
	202	"protect on FC000000 FC05FFFF\0" \
	203	""
45a212c4	204	#endif /* CONFIG_TQM5200_B */
b87dfd28 WD	205
	206	#define CONFIG_BOOTCOMMAND "run net_nfs"
	207
	208	/*
	209	* IPB Bus clocking configuration.
	210	*/
6d0f6bcf	211	#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
b87dfd28	212
6d0f6bcf	213	#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
b87dfd28 WD	214	/*
	215	* PCI Bus clocking configuration
	216	*
	217	* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
6d0f6bcf	218	* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
c99512d6	219	* of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
b87dfd28	220	*/
6d0f6bcf	221	#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
b87dfd28 WD	222	#endif
	223
	224	/*
	225	* I2C configuration
	226	*/
	227	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
6d0f6bcf	228	#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 */
b87dfd28 WD	229
	230	/*
	231	* I2C clock frequency
	232	*
	233	* Please notice, that the resulting clock frequency could differ from the
	234	* configured value. This is because the I2C clock is derived from system
	235	* clock over a frequency divider with only a few divider values. U-boot
6d0f6bcf	236	* calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
b87dfd28 WD	237	* approximation allways lies below the configured value, never above.
b87dfd28 WD	238	*/
6d0f6bcf JCPV	239	#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
6d0f6bcf JCPV	240	#define CONFIG_SYS_I2C_SLAVE 0x7F
b87dfd28 WD	241
	242	/*
	243	* EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
	244	* also). For other EEPROMs configuration should be verified. On Mini-FAP the
	245	* EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
	246	* same configuration could be used.
	247	*/
6d0f6bcf JCPV	248	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
	249	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
	250	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
	251	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
b87dfd28 WD	252
b87dfd28 WD	253	/* List of I2C addresses to be verified by POST */
60aaaa07 PT	254	#undef CONFIG_SYS_POST_I2C_ADDRS
	255	#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_EEPROM_ADDR, \
	256	CONFIG_SYS_I2C_RTC_ADDR, \
	257	CONFIG_SYS_I2C_SLAVE}
b87dfd28 WD	258
	259	/*
	260	* Flash configuration
	261	*/
14d0a02a	262	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE /* 0xFC000000 */
b87dfd28	263
45a212c4	264	/* use CFI flash driver */
6d0f6bcf	265	#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
00b1883a	266	#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
6d0f6bcf JCPV	267	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
	268	#define CONFIG_SYS_FLASH_EMPTY_INFO
	269	#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */
	270	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
	271	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
	272
	273	#if !defined(CONFIG_SYS_LOWBOOT)
	274	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
	275	#else /* CONFIG_SYS_LOWBOOT */
45a212c4	276	#if defined(CONFIG_TQM5200_B)
6d0f6bcf	277	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00080000)
45a212c4	278	#else
6d0f6bcf	279	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
45a212c4	280	#endif /* CONFIG_TQM5200_B */
6d0f6bcf JCPV	281	#endif /* CONFIG_SYS_LOWBOOT */
6d0f6bcf JCPV	282	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
b87dfd28	283	(= chip selects) */
b87dfd28 WD	284
b87dfd28 WD	285	/* Dynamic MTD partition support */
68d7d651	286	#define CONFIG_CMD_MTDPARTS
942556a9 SR	287	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
942556a9 SR	288	#define CONFIG_FLASH_CFI_MTD
b87dfd28	289	#define MTDIDS_DEFAULT "nor0=TQM5200-0"
45a212c4 WD	290	#if defined(CONFIG_TQM5200_B)
	291	#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:768k(firmware)," \
	292	"1280k(kernel)," \
	293	"2m(initrd)," \
	294	"4m(small-fs)," \
	295	"16m(big-fs)," \
	296	"8m(misc)"
	297	#else
b87dfd28 WD	298	#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
	299	"1408k(kernel)," \
	300	"2m(initrd)," \
	301	"4m(small-fs)," \
	302	"16m(big-fs)," \
	303	"8m(misc)"
45a212c4	304	#endif /* CONFIG_TQM5200_B */
b87dfd28 WD	305
	306	/*
	307	* Environment settings
	308	*/
5a1aceb0	309	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586	310	#define CONFIG_ENV_SIZE 0x10000
45a212c4	311	#if defined(CONFIG_TQM5200_B)
0e8d1586	312	#define CONFIG_ENV_SECT_SIZE 0x40000
45a212c4	313	#else
0e8d1586 JCPV	314	#define CONFIG_ENV_SECT_SIZE 0x20000
	315	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
	316	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
45a212c4	317	#endif /* CONFIG_TQM5200_B */
b87dfd28 WD	318
	319	/*
	320	* Memory map
	321	*/
6d0f6bcf JCPV	322	#define CONFIG_SYS_MBAR 0xF0000000
	323	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	324	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
b87dfd28 WD	325
b87dfd28 WD	326	/* Use ON-Chip SRAM until RAM will be available */
6d0f6bcf	327	#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
b87dfd28 WD	328	#ifdef CONFIG_POST
b87dfd28 WD	329	/* preserve space for the post_word at end of on-chip SRAM */
6d0f6bcf	330	#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
b87dfd28	331	#else
6d0f6bcf	332	#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
b87dfd28 WD	333	#endif
	334
	335
6d0f6bcf JCPV	336	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	337	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	338	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
b87dfd28	339
14d0a02a	340	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	341	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	342	# define CONFIG_SYS_RAMBOOT 1
b87dfd28 WD	343	#endif
b87dfd28 WD	344
45a212c4	345	#if defined(CONFIG_TQM5200_B)
6d0f6bcf	346	#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
45a212c4	347	#else
6d0f6bcf	348	#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
45a212c4	349	#endif /* CONFIG_TQM5200_B */
6d0f6bcf JCPV	350	#define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* Reserve 1024 kB for malloc() */
6d0f6bcf JCPV	351	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
b87dfd28 WD	352
	353	/*
	354	* Ethernet configuration
	355	*/
	356	#define CONFIG_MPC5xxx_FEC 1
86321fc1	357	#define CONFIG_MPC5xxx_FEC_MII100
b87dfd28	358	/*
86321fc1	359	* Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
b87dfd28	360	*/
86321fc1	361	/* #define CONFIG_MPC5xxx_FEC_MII10 */
b87dfd28 WD	362	#define CONFIG_PHY_ADDR 0x00
	363
	364	/*
	365	* GPIO configuration
	366	*
	367	* use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
	368	* Bit 0 (mask: 0x80000000): 1
	369	* use ALT CAN position: Bits 2-3 (mask: 0x30000000):
	370	* 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
	371	* 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
	372	* Use for REV200 STK52XX boards. Do not use with REV100 modules
	373	* (because, there I2C1 is used as I2C bus)
	374	* use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
	375	* use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
	376	* 000 -> All PSC2 pins are GIOPs
	377	* 001 -> CAN1/2 on PSC2 pins
	378	* Use for REV100 STK52xx boards
	379	* use PSC3: Bits 20:23 (mask: 0x00000300):
	380	* 0001 -> USB2
	381	* 0000 -> GPIO
	382	* use PSC6:
	383	* on STK52xx:
	384	* use as UART. Pins PSC6_0 to PSC6_3 are used.
	385	* Bits 9:11 (mask: 0x00700000):
	386	* 101 -> PSC6 : Extended POST test is not available
	387	* on MINI-FAP and TQM5200_IB:
	388	* use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
	389	* 000 -> PSC6 could not be used as UART, CODEC or IrDA
	390	* GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
	391	* tests.
	392	*/
6d0f6bcf	393	#define CONFIG_SYS_GPS_PORT_CONFIG 0x81500114
b87dfd28 WD	394
	395	/*
	396	* RTC configuration
	397	*/
	398	#define CONFIG_RTC_M41T11 1
6d0f6bcf JCPV	399	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
6d0f6bcf JCPV	400	#define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* because Linux uses the same base
b87dfd28 WD	401	year */
	402
	403	/*
	404	* Miscellaneous configurable options
	405	*/
6d0f6bcf JCPV	406	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	407	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
33ed73bc	408	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
d794cfef	409	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	410	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
b87dfd28	411	#else
6d0f6bcf	412	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
b87dfd28	413	#endif
6d0f6bcf JCPV	414	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	415	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	416	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
b87dfd28	417
6d0f6bcf	418	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
d794cfef	419	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	420	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
d794cfef JL	421	#endif
d794cfef JL	422
b87dfd28	423	/* Enable an alternate, more extensive memory test */
6d0f6bcf	424	#define CONFIG_SYS_ALT_MEMTEST
b87dfd28	425
6d0f6bcf JCPV	426	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
6d0f6bcf JCPV	427	#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
b87dfd28	428
6d0f6bcf	429	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
b87dfd28	430
6d0f6bcf	431	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
b87dfd28 WD	432
b87dfd28 WD	433	/*
a1aa0bb5	434	* Enable loopw command.
b87dfd28 WD	435	*/
	436	#define CONFIG_LOOPW
	437
	438	/*
	439	* Various low-level settings
	440	*/
6d0f6bcf JCPV	441	#define CONFIG_SYS_HID0_INIT HID0_ICE \| HID0_ICFI
6d0f6bcf JCPV	442	#define CONFIG_SYS_HID0_FINAL HID0_ICE
b87dfd28	443
6d0f6bcf JCPV	444	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
	445	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	446	#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
	447	#define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
b87dfd28	448	#else
6d0f6bcf	449	#define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
b87dfd28	450	#endif
6d0f6bcf JCPV	451	#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
6d0f6bcf JCPV	452	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
b87dfd28	453
b87dfd28	454	#define CONFIG_LAST_STAGE_INIT
b87dfd28 WD	455
	456	/*
	457	* SRAM - Do not map below 2 GB in address space, because this area is used
	458	* for SDRAM autosizing.
	459	*/
6d0f6bcf JCPV	460	#define CONFIG_SYS_CS2_START 0xE5000000
	461	#define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */
	462	#define CONFIG_SYS_CS2_CFG 0x0004D930
b87dfd28 WD	463
	464	/*
	465	* Grafic controller - Do not map below 2 GB in address space, because this
	466	* area is used for SDRAM autosizing.
	467	*/
b87dfd28	468	#define SM501_FB_BASE 0xE0000000
6d0f6bcf JCPV	469	#define CONFIG_SYS_CS1_START (SM501_FB_BASE)
	470	#define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */
	471	#define CONFIG_SYS_CS1_CFG 0x8F48FF70
	472	#define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000
b87dfd28	473
6d0f6bcf JCPV	474	#define CONFIG_SYS_CS_BURST 0x00000000
6d0f6bcf JCPV	475	#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
b87dfd28	476
6d0f6bcf	477	#define CONFIG_SYS_RESET_ADDRESS 0xff000000
b87dfd28 WD	478
	479	/*-----------------------------------------------------------------------
	480	* USB stuff
	481	*-----------------------------------------------------------------------
	482	*/
	483	#define CONFIG_USB_CLOCK 0x0001BBBB
	484	#define CONFIG_USB_CONFIG 0x00001000
	485
	486	/*-----------------------------------------------------------------------
	487	* IDE/ATA stuff Supports IDE harddisk
	488	*-----------------------------------------------------------------------
	489	*/
	490
	491	#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
	492
	493	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	494	#undef CONFIG_IDE_LED /* LED for ide not supported */
	495
	496	#define CONFIG_IDE_RESET /* reset for ide supported */
	497	#define CONFIG_IDE_PREINIT
	498
6d0f6bcf JCPV	499	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
6d0f6bcf JCPV	500	#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
b87dfd28	501
6d0f6bcf	502	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
b87dfd28	503
6d0f6bcf	504	#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
b87dfd28 WD	505
b87dfd28 WD	506	/* Offset for data I/O */
6d0f6bcf	507	#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
b87dfd28 WD	508
b87dfd28 WD	509	/* Offset for normal register accesses */
6d0f6bcf	510	#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
b87dfd28 WD	511
b87dfd28 WD	512	/* Offset for alternate registers */
6d0f6bcf	513	#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
b87dfd28 WD	514
b87dfd28 WD	515	/* Interval between registers */
6d0f6bcf	516	#define CONFIG_SYS_ATA_STRIDE 4
b87dfd28 WD	517
b87dfd28 WD	518	#endif /* __CONFIG_H */