]>
Commit | Line | Data |
---|---|---|
e6f2e902 MB |
1 | /* |
2 | * (C) Copyright 2005 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
e6f2e902 MB |
6 | */ |
7 | ||
8 | /* | |
9 | * TQM8349 board configuration file | |
10 | */ | |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
e6f2e902 MB |
15 | /* |
16 | * High Level Configuration Options | |
17 | */ | |
18 | #define CONFIG_E300 1 /* E300 Family */ | |
2c7920af | 19 | #define CONFIG_MPC834x 1 /* MPC834x specific */ |
9ca880a2 | 20 | #define CONFIG_MPC8349 1 /* MPC8349 specific */ |
e6f2e902 MB |
21 | #define CONFIG_TQM834X 1 /* TQM834X board specific */ |
22 | ||
2ae18241 WD |
23 | #define CONFIG_SYS_TEXT_BASE 0x80000000 |
24 | ||
16263087 | 25 | /* IMMR Base Address Register, use Freescale default: 0xff400000 */ |
6d0f6bcf | 26 | #define CONFIG_SYS_IMMR 0xff400000 |
e6f2e902 MB |
27 | |
28 | /* System clock. Primary input clock when in PCI host mode */ | |
29 | #define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */ | |
30 | ||
31 | /* | |
32 | * Local Bus LCRR | |
33 | * LCRR: DLL bypass, Clock divider is 8 | |
34 | * | |
35 | * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz | |
36 | * | |
37 | * External Local Bus rate is | |
38 | * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV | |
39 | */ | |
c7190f02 KP |
40 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
41 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 | |
e6f2e902 MB |
42 | |
43 | /* board pre init: do not call, nothing to do */ | |
e6f2e902 MB |
44 | |
45 | /* detect the number of flash banks */ | |
46 | #define CONFIG_BOARD_EARLY_INIT_R | |
47 | ||
48 | /* | |
49 | * DDR Setup | |
50 | */ | |
df939e16 JH |
51 | /* DDR is system memory*/ |
52 | #define CONFIG_SYS_DDR_BASE 0x00000000 | |
53 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
6d0f6bcf | 54 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE |
df939e16 JH |
55 | #define DDR_CASLAT_25 /* CASLAT set to 2.5 */ |
56 | #undef CONFIG_DDR_ECC /* only for ECC DDR module */ | |
57 | #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */ | |
e6f2e902 | 58 | |
df939e16 | 59 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
6d0f6bcf JCPV |
60 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ |
61 | #define CONFIG_SYS_MEMTEST_END 0x00100000 | |
e6f2e902 MB |
62 | |
63 | /* | |
64 | * FLASH on the Local Bus | |
65 | */ | |
df939e16 JH |
66 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
67 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ | |
6d0f6bcf JCPV |
68 | #undef CONFIG_SYS_FLASH_CHECKSUM |
69 | #define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */ | |
70 | #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */ | |
df939e16 | 71 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */ |
a3455c00 | 72 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
e6f2e902 MB |
73 | |
74 | /* | |
75 | * FLASH bank number detection | |
76 | */ | |
77 | ||
78 | /* | |
df939e16 JH |
79 | * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of |
80 | * Flash banks has to be determined at runtime and stored in a gloabl variable | |
81 | * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is | |
82 | * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array | |
83 | * flash_info, and should be made sufficiently large to accomodate the number | |
84 | * of banks that might actually be detected. Since most (all?) Flash related | |
85 | * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on | |
86 | * the board, it is defined as tqm834x_num_flash_banks. | |
e6f2e902 | 87 | */ |
6d0f6bcf | 88 | #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 |
e6f2e902 | 89 | |
df939e16 | 90 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */ |
e6f2e902 MB |
91 | |
92 | /* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */ | |
df939e16 JH |
93 | #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA) \ |
94 | | BR_MS_GPCM \ | |
95 | | BR_PS_32 \ | |
96 | | BR_V) | |
e6f2e902 MB |
97 | |
98 | /* FLASH timing (0x0000_0c54) */ | |
df939e16 JH |
99 | #define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT \ |
100 | | OR_GPCM_ACS_DIV4 \ | |
101 | | OR_GPCM_SCY_5 \ | |
102 | | OR_GPCM_TRLX) | |
e6f2e902 | 103 | |
7d6a0982 | 104 | #define CONFIG_SYS_PRELIM_OR_AM OR_AM_1GB /* OR addr mask: 1 GiB */ |
e6f2e902 | 105 | |
df939e16 JH |
106 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \ |
107 | | CONFIG_SYS_OR_TIMING_FLASH) | |
e6f2e902 | 108 | |
7d6a0982 | 109 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_1GB) |
6902df56 | 110 | |
df939e16 JH |
111 | /* Window base at flash base */ |
112 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE | |
e6f2e902 MB |
113 | |
114 | /* disable remaining mappings */ | |
6d0f6bcf JCPV |
115 | #define CONFIG_SYS_BR1_PRELIM 0x00000000 |
116 | #define CONFIG_SYS_OR1_PRELIM 0x00000000 | |
117 | #define CONFIG_SYS_LBLAWBAR1_PRELIM 0x00000000 | |
118 | #define CONFIG_SYS_LBLAWAR1_PRELIM 0x00000000 | |
119 | ||
120 | #define CONFIG_SYS_BR2_PRELIM 0x00000000 | |
121 | #define CONFIG_SYS_OR2_PRELIM 0x00000000 | |
122 | #define CONFIG_SYS_LBLAWBAR2_PRELIM 0x00000000 | |
123 | #define CONFIG_SYS_LBLAWAR2_PRELIM 0x00000000 | |
124 | ||
125 | #define CONFIG_SYS_BR3_PRELIM 0x00000000 | |
126 | #define CONFIG_SYS_OR3_PRELIM 0x00000000 | |
127 | #define CONFIG_SYS_LBLAWBAR3_PRELIM 0x00000000 | |
128 | #define CONFIG_SYS_LBLAWAR3_PRELIM 0x00000000 | |
e6f2e902 MB |
129 | |
130 | /* | |
131 | * Monitor config | |
132 | */ | |
14d0a02a | 133 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
e6f2e902 | 134 | |
6d0f6bcf | 135 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
4681e673 | 136 | # define CONFIG_SYS_RAMBOOT |
e6f2e902 | 137 | #else |
4681e673 | 138 | # undef CONFIG_SYS_RAMBOOT |
e6f2e902 MB |
139 | #endif |
140 | ||
6d0f6bcf | 141 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
df939e16 JH |
142 | #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */ |
143 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ | |
e6f2e902 | 144 | |
df939e16 JH |
145 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
146 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
6d0f6bcf | 147 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
e6f2e902 | 148 | |
df939e16 JH |
149 | /* Reserve 384 kB = 3 sect. for Mon */ |
150 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) | |
151 | /* Reserve 512 kB for malloc */ | |
152 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) | |
e6f2e902 MB |
153 | |
154 | /* | |
155 | * Serial Port | |
156 | */ | |
157 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
158 | #define CONFIG_SYS_NS16550_SERIAL |
159 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
160 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
e6f2e902 | 161 | |
6d0f6bcf | 162 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
df939e16 | 163 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
e6f2e902 | 164 | |
6d0f6bcf JCPV |
165 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) |
166 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) | |
e6f2e902 MB |
167 | |
168 | /* | |
169 | * I2C | |
170 | */ | |
00f792e0 HS |
171 | #define CONFIG_SYS_I2C |
172 | #define CONFIG_SYS_I2C_FSL | |
173 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
174 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
175 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
e6f2e902 MB |
176 | |
177 | /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */ | |
df939e16 JH |
178 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ |
179 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */ | |
180 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes/write */ | |
181 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */ | |
e6f2e902 MB |
182 | |
183 | /* I2C RTC */ | |
df939e16 JH |
184 | #define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */ |
185 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ | |
e6f2e902 | 186 | |
e6f2e902 MB |
187 | /* |
188 | * TSEC | |
189 | */ | |
53677ef1 | 190 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
e6f2e902 MB |
191 | #define CONFIG_MII |
192 | ||
6d0f6bcf | 193 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
df939e16 | 194 | #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) |
6d0f6bcf | 195 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 |
df939e16 | 196 | #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) |
e6f2e902 MB |
197 | |
198 | #if defined(CONFIG_TSEC_ENET) | |
199 | ||
255a3577 KP |
200 | #define CONFIG_TSEC1 1 |
201 | #define CONFIG_TSEC1_NAME "TSEC0" | |
202 | #define CONFIG_TSEC2 1 | |
203 | #define CONFIG_TSEC2_NAME "TSEC1" | |
df939e16 JH |
204 | #define TSEC1_PHY_ADDR 2 |
205 | #define TSEC2_PHY_ADDR 1 | |
206 | #define TSEC1_PHYIDX 0 | |
207 | #define TSEC2_PHYIDX 0 | |
3a79013e AF |
208 | #define TSEC1_FLAGS TSEC_GIGABIT |
209 | #define TSEC2_FLAGS TSEC_GIGABIT | |
e6f2e902 MB |
210 | |
211 | /* Options are: TSEC[0-1] */ | |
df939e16 | 212 | #define CONFIG_ETHPRIME "TSEC0" |
e6f2e902 MB |
213 | |
214 | #endif /* CONFIG_TSEC_ENET */ | |
215 | ||
e6f2e902 MB |
216 | #if defined(CONFIG_PCI) |
217 | ||
df939e16 | 218 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
6902df56 RJ |
219 | |
220 | /* PCI1 host bridge */ | |
df939e16 JH |
221 | #define CONFIG_SYS_PCI1_MEM_BASE 0x90000000 |
222 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
223 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
224 | #define CONFIG_SYS_PCI1_MMIO_BASE \ | |
225 | (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) | |
226 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE | |
227 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
228 | #define CONFIG_SYS_PCI1_IO_BASE 0xe2000000 | |
229 | #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE | |
230 | #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */ | |
e6f2e902 | 231 | |
e6f2e902 | 232 | #undef CONFIG_EEPRO100 |
63ff004c | 233 | #define CONFIG_EEPRO100 |
e6f2e902 MB |
234 | #undef CONFIG_TULIP |
235 | ||
236 | #if !defined(CONFIG_PCI_PNP) | |
6d0f6bcf JCPV |
237 | #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE |
238 | #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_MEM_BASE | |
6902df56 | 239 | #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */ |
e6f2e902 MB |
240 | #endif |
241 | ||
6d0f6bcf | 242 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
e6f2e902 MB |
243 | |
244 | #endif /* CONFIG_PCI */ | |
245 | ||
246 | /* | |
247 | * Environment | |
248 | */ | |
df939e16 JH |
249 | #define CONFIG_ENV_ADDR \ |
250 | (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
251 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */ | |
252 | #define CONFIG_ENV_SIZE 0x8000 /* 32K max size */ | |
929b79a0 WD |
253 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
254 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
255 | ||
df939e16 JH |
256 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
257 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
e6f2e902 | 258 | |
a1aa0bb5 JL |
259 | /* |
260 | * BOOTP options | |
261 | */ | |
262 | #define CONFIG_BOOTP_BOOTFILESIZE | |
263 | #define CONFIG_BOOTP_BOOTPATH | |
264 | #define CONFIG_BOOTP_GATEWAY | |
265 | #define CONFIG_BOOTP_HOSTNAME | |
266 | ||
e6f2e902 MB |
267 | /* |
268 | * Miscellaneous configurable options | |
269 | */ | |
df939e16 JH |
270 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
271 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
e6f2e902 | 272 | |
df939e16 JH |
273 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
274 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
a059e90e | 275 | |
df939e16 JH |
276 | /* Boot Argument Buffer Size */ |
277 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
e6f2e902 | 278 | |
df939e16 | 279 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
e6f2e902 MB |
280 | |
281 | /* | |
282 | * For booting Linux, the board info and command line data | |
9f530d59 | 283 | * have to be in the first 256 MB of memory, since this is |
e6f2e902 MB |
284 | * the maximum mapped by the Linux kernel during initialization. |
285 | */ | |
df939e16 JH |
286 | /* Initial Memory map for Linux */ |
287 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) | |
e6f2e902 | 288 | |
6d0f6bcf | 289 | #define CONFIG_SYS_HRCW_LOW (\ |
e6f2e902 MB |
290 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
291 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
292 | HRCWL_CSB_TO_CLKIN_4X1 |\ | |
293 | HRCWL_VCO_1X2 |\ | |
294 | HRCWL_CORE_TO_CSB_2X1) | |
295 | ||
296 | #if defined(PCI_64BIT) | |
6d0f6bcf | 297 | #define CONFIG_SYS_HRCW_HIGH (\ |
e6f2e902 MB |
298 | HRCWH_PCI_HOST |\ |
299 | HRCWH_64_BIT_PCI |\ | |
300 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
301 | HRCWH_PCI2_ARBITER_DISABLE |\ | |
302 | HRCWH_CORE_ENABLE |\ | |
303 | HRCWH_FROM_0X00000100 |\ | |
304 | HRCWH_BOOTSEQ_DISABLE |\ | |
305 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
306 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
307 | HRCWH_TSEC1M_IN_GMII |\ | |
df939e16 | 308 | HRCWH_TSEC2M_IN_GMII) |
e6f2e902 | 309 | #else |
6d0f6bcf | 310 | #define CONFIG_SYS_HRCW_HIGH (\ |
e6f2e902 MB |
311 | HRCWH_PCI_HOST |\ |
312 | HRCWH_32_BIT_PCI |\ | |
313 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
6902df56 | 314 | HRCWH_PCI2_ARBITER_DISABLE |\ |
e6f2e902 MB |
315 | HRCWH_CORE_ENABLE |\ |
316 | HRCWH_FROM_0X00000100 |\ | |
317 | HRCWH_BOOTSEQ_DISABLE |\ | |
318 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
319 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
320 | HRCWH_TSEC1M_IN_GMII |\ | |
df939e16 | 321 | HRCWH_TSEC2M_IN_GMII) |
e6f2e902 MB |
322 | #endif |
323 | ||
9260a561 | 324 | /* System IO Config */ |
3c9b1ee1 | 325 | #define CONFIG_SYS_SICRH 0 |
6d0f6bcf | 326 | #define CONFIG_SYS_SICRL SICRL_LDP_A |
9260a561 | 327 | |
e6f2e902 | 328 | /* i-cache and d-cache disabled */ |
6d0f6bcf | 329 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
1a2e203b KP |
330 | #define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \ |
331 | HID0_ENABLE_INSTRUCTION_CACHE) | |
6d0f6bcf | 332 | #define CONFIG_SYS_HID2 HID2_HBE |
e6f2e902 | 333 | |
31d82672 BB |
334 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
335 | ||
2688e2f9 | 336 | /* DDR 0 - 512M */ |
df939e16 | 337 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ |
72cd4087 | 338 | | BATL_PP_RW \ |
df939e16 JH |
339 | | BATL_MEMCOHERENCE) |
340 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ | |
341 | | BATU_BL_256M \ | |
342 | | BATU_VS \ | |
343 | | BATU_VP) | |
344 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 \ | |
72cd4087 | 345 | | BATL_PP_RW \ |
df939e16 JH |
346 | | BATL_MEMCOHERENCE) |
347 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 \ | |
348 | | BATU_BL_256M \ | |
349 | | BATU_VS \ | |
350 | | BATU_VP) | |
2688e2f9 KG |
351 | |
352 | /* stack in DCACHE @ 512M (no backing mem) */ | |
df939e16 | 353 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR \ |
72cd4087 | 354 | | BATL_PP_RW \ |
df939e16 JH |
355 | | BATL_MEMCOHERENCE) |
356 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR \ | |
357 | | BATU_BL_128K \ | |
358 | | BATU_VS \ | |
359 | | BATU_VP) | |
2688e2f9 KG |
360 | |
361 | /* PCI */ | |
6fe16a87 | 362 | #ifdef CONFIG_PCI |
842033e6 | 363 | #define CONFIG_PCI_INDIRECT_BRIDGE |
df939e16 | 364 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE \ |
72cd4087 | 365 | | BATL_PP_RW \ |
df939e16 JH |
366 | | BATL_MEMCOHERENCE) |
367 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE \ | |
368 | | BATU_BL_256M \ | |
369 | | BATU_VS \ | |
370 | | BATU_VP) | |
371 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE \ | |
72cd4087 | 372 | | BATL_PP_RW \ |
df939e16 JH |
373 | | BATL_MEMCOHERENCE \ |
374 | | BATL_GUARDEDSTORAGE) | |
375 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE \ | |
376 | | BATU_BL_256M \ | |
377 | | BATU_VS \ | |
378 | | BATU_VP) | |
379 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE \ | |
72cd4087 | 380 | | BATL_PP_RW \ |
df939e16 JH |
381 | | BATL_CACHEINHIBIT \ |
382 | | BATL_GUARDEDSTORAGE) | |
383 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE \ | |
384 | | BATU_BL_16M \ | |
385 | | BATU_VS \ | |
386 | | BATU_VP) | |
6fe16a87 | 387 | #else |
6d0f6bcf JCPV |
388 | #define CONFIG_SYS_IBAT3L (0) |
389 | #define CONFIG_SYS_IBAT3U (0) | |
390 | #define CONFIG_SYS_IBAT4L (0) | |
391 | #define CONFIG_SYS_IBAT4U (0) | |
392 | #define CONFIG_SYS_IBAT5L (0) | |
393 | #define CONFIG_SYS_IBAT5U (0) | |
6fe16a87 | 394 | #endif |
2688e2f9 KG |
395 | |
396 | /* IMMRBAR */ | |
df939e16 | 397 | #define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR \ |
72cd4087 | 398 | | BATL_PP_RW \ |
df939e16 JH |
399 | | BATL_CACHEINHIBIT \ |
400 | | BATL_GUARDEDSTORAGE) | |
401 | #define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR \ | |
402 | | BATU_BL_1M \ | |
403 | | BATU_VS \ | |
404 | | BATU_VP) | |
2688e2f9 KG |
405 | |
406 | /* FLASH */ | |
df939e16 | 407 | #define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE \ |
72cd4087 | 408 | | BATL_PP_RW \ |
df939e16 JH |
409 | | BATL_CACHEINHIBIT \ |
410 | | BATL_GUARDEDSTORAGE) | |
411 | #define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE \ | |
412 | | BATU_BL_256M \ | |
413 | | BATU_VS \ | |
414 | | BATU_VP) | |
6d0f6bcf JCPV |
415 | |
416 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
417 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
418 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
419 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
420 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
421 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
422 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
423 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
424 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L | |
425 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
426 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L | |
427 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
428 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
429 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
430 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
431 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
2688e2f9 | 432 | |
2694690e | 433 | #if defined(CONFIG_CMD_KGDB) |
e6f2e902 | 434 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
e6f2e902 MB |
435 | #endif |
436 | ||
437 | /* | |
438 | * Environment Configuration | |
439 | */ | |
440 | ||
df939e16 JH |
441 | /* default location for tftp and bootm */ |
442 | #define CONFIG_LOADADDR 400000 | |
e6f2e902 | 443 | |
e6f2e902 | 444 | #define CONFIG_PREBOOT "echo;" \ |
32bf3d14 | 445 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
e6f2e902 MB |
446 | "echo" |
447 | ||
e6f2e902 MB |
448 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
449 | "netdev=eth0\0" \ | |
b931b3a9 | 450 | "hostname=tqm834x\0" \ |
e6f2e902 | 451 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
fe126d8b | 452 | "nfsroot=${serverip}:${rootpath}\0" \ |
e6f2e902 | 453 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
fe126d8b WD |
454 | "addip=setenv bootargs ${bootargs} " \ |
455 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
456 | ":${hostname}:${netdev}:off panic=1\0" \ | |
df939e16 | 457 | "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ |
4681e673 | 458 | "flash_nfs_old=run nfsargs addip addcons;" \ |
fe126d8b | 459 | "bootm ${kernel_addr}\0" \ |
4681e673 WD |
460 | "flash_nfs=run nfsargs addip addcons;" \ |
461 | "bootm ${kernel_addr} - ${fdt_addr}\0" \ | |
462 | "flash_self_old=run ramargs addip addcons;" \ | |
fe126d8b | 463 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
4681e673 WD |
464 | "flash_self=run ramargs addip addcons;" \ |
465 | "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ | |
466 | "net_nfs_old=tftp 400000 ${bootfile};" \ | |
467 | "run nfsargs addip addcons;bootm\0" \ | |
468 | "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ | |
469 | "tftp ${fdt_addr_r} ${fdt_file}; " \ | |
470 | "run nfsargs addip addcons; " \ | |
471 | "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ | |
e6f2e902 | 472 | "rootpath=/opt/eldk/ppc_6xx\0" \ |
4681e673 WD |
473 | "bootfile=tqm834x/uImage\0" \ |
474 | "fdtfile=tqm834x/tqm834x.dtb\0" \ | |
475 | "kernel_addr_r=400000\0" \ | |
476 | "fdt_addr_r=600000\0" \ | |
477 | "ramdisk_addr_r=800000\0" \ | |
478 | "kernel_addr=800C0000\0" \ | |
479 | "fdt_addr=800A0000\0" \ | |
480 | "ramdisk_addr=80300000\0" \ | |
481 | "u-boot=tqm834x/u-boot.bin\0" \ | |
482 | "load=tftp 200000 ${u-boot}\0" \ | |
483 | "update=protect off 80000000 +${filesize};" \ | |
484 | "era 80000000 +${filesize};" \ | |
485 | "cp.b 200000 80000000 ${filesize}\0" \ | |
d8ab58b2 | 486 | "upd=run load update\0" \ |
e6f2e902 MB |
487 | "" |
488 | ||
489 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
490 | ||
491 | /* | |
492 | * JFFS2 partitions | |
493 | */ | |
494 | /* mtdparts command line support */ | |
942556a9 SR |
495 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
496 | #define CONFIG_FLASH_CFI_MTD | |
e6f2e902 MB |
497 | #define MTDIDS_DEFAULT "nor0=TQM834x-0" |
498 | ||
499 | /* default mtd partition table */ | |
df939e16 JH |
500 | #define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),256k(env)," \ |
501 | "1m(kernel),2m(initrd)," \ | |
502 | "-(user);" \ | |
e6f2e902 MB |
503 | |
504 | #endif /* __CONFIG_H */ |