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Commit | Line | Data |
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d4ca31c4 | 1 | /* |
23c5d253 | 2 | * (C) Copyright 2000-2014 |
d4ca31c4 WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
d4ca31c4 WD |
6 | */ |
7 | ||
8 | /* | |
9 | * board/config.h - configuration options, board specific | |
10 | */ | |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
15 | /* | |
16 | * High Level Configuration Options | |
17 | * (easy to change) | |
18 | */ | |
19 | ||
20 | #define CONFIG_MPC866 1 /* This is a MPC866 CPU */ | |
21 | #define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */ | |
23c5d253 WD |
22 | #define CONFIG_SYS_GENERIC_BOARD |
23 | #define CONFIG_DISPLAY_BOARDINFO | |
d4ca31c4 | 24 | |
2ae18241 WD |
25 | #define CONFIG_SYS_TEXT_BASE 0x40000000 |
26 | ||
66ca92a5 | 27 | #define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */ |
6d0f6bcf JCPV |
28 | #define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */ |
29 | #define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */ | |
66ca92a5 | 30 | #define CONFIG_8xx_CPUCLK_DEFAULT 50000000 /* 50 MHz - CPU default clock */ |
c178d3da WD |
31 | /* (it will be used if there is no */ |
32 | /* 'cpuclk' variable with valid value) */ | |
d4ca31c4 | 33 | |
6d0f6bcf | 34 | #undef CONFIG_SYS_MEASURE_CPUCLK /* Measure real cpu clock */ |
75d1ea7f WD |
35 | /* (function measure_gclk() */ |
36 | /* will be called) */ | |
6d0f6bcf JCPV |
37 | #ifdef CONFIG_SYS_MEASURE_CPUCLK |
38 | #define CONFIG_SYS_8XX_XIN 10000000 /* measure_gclk() needs this */ | |
75d1ea7f WD |
39 | #endif |
40 | ||
c178d3da | 41 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
3cb7a480 WD |
42 | #define CONFIG_SYS_SMC_RXBUFLEN 128 |
43 | #define CONFIG_SYS_MAXIDLE 10 | |
d4ca31c4 WD |
44 | #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ |
45 | ||
c178d3da | 46 | #define CONFIG_BOOTCOUNT_LIMIT |
d4ca31c4 WD |
47 | |
48 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
49 | ||
50 | #define CONFIG_BOARD_TYPES 1 /* support board types */ | |
51 | ||
c178d3da | 52 | #define CONFIG_PREBOOT "echo;" \ |
32bf3d14 | 53 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
d4ca31c4 WD |
54 | "echo" |
55 | ||
56 | #undef CONFIG_BOOTARGS | |
57 | ||
c178d3da | 58 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
d4ca31c4 WD |
59 | "netdev=eth0\0" \ |
60 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
fe126d8b | 61 | "nfsroot=${serverip}:${rootpath}\0" \ |
d4ca31c4 | 62 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
fe126d8b WD |
63 | "addip=setenv bootargs ${bootargs} " \ |
64 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
65 | ":${hostname}:${netdev}:off panic=1\0" \ | |
d4ca31c4 | 66 | "flash_nfs=run nfsargs addip;" \ |
fe126d8b | 67 | "bootm ${kernel_addr}\0" \ |
d4ca31c4 | 68 | "flash_self=run ramargs addip;" \ |
fe126d8b WD |
69 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
70 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
d4ca31c4 | 71 | "rootpath=/opt/eldk/ppc_8xx\0" \ |
29f8f58f WD |
72 | "hostname=TQM866M\0" \ |
73 | "bootfile=TQM866M/uImage\0" \ | |
9ef57bbe MK |
74 | "fdt_addr=400C0000\0" \ |
75 | "kernel_addr=40100000\0" \ | |
eb6da805 | 76 | "ramdisk_addr=40280000\0" \ |
29f8f58f | 77 | "u-boot=TQM866M/u-image.bin\0" \ |
9ef57bbe | 78 | "load=tftp 200000 ${u-boot}\0" \ |
29f8f58f WD |
79 | "update=prot off 40000000 +${filesize};" \ |
80 | "era 40000000 +${filesize};" \ | |
9ef57bbe | 81 | "cp.b 200000 40000000 ${filesize};" \ |
29f8f58f | 82 | "sete filesize;save\0" \ |
d4ca31c4 WD |
83 | "" |
84 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
85 | ||
86 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 87 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
d4ca31c4 WD |
88 | |
89 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
90 | ||
c178d3da | 91 | #define CONFIG_STATUS_LED 1 /* Status LED enabled */ |
d4ca31c4 WD |
92 | |
93 | #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ | |
94 | ||
95 | /* enable I2C and select the hardware/software driver */ | |
ea818dbb HS |
96 | #define CONFIG_SYS_I2C |
97 | #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ | |
98 | #define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */ | |
99 | #define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE | |
d4ca31c4 | 100 | |
d4ca31c4 WD |
101 | /* |
102 | * Software (bit-bang) I2C driver configuration | |
103 | */ | |
104 | #define PB_SCL 0x00000020 /* PB 26 */ | |
105 | #define PB_SDA 0x00000010 /* PB 27 */ | |
106 | ||
107 | #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) | |
108 | #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) | |
109 | #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) | |
110 | #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) | |
111 | #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ | |
c178d3da | 112 | else immr->im_cpm.cp_pbdat &= ~PB_SDA |
d4ca31c4 | 113 | #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ |
c178d3da | 114 | else immr->im_cpm.cp_pbdat &= ~PB_SCL |
d4ca31c4 | 115 | #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ |
d4ca31c4 | 116 | |
6d0f6bcf JCPV |
117 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C256 */ |
118 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ | |
119 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 | |
120 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ | |
d4ca31c4 | 121 | |
37d4bb70 JL |
122 | /* |
123 | * BOOTP options | |
124 | */ | |
125 | #define CONFIG_BOOTP_SUBNETMASK | |
126 | #define CONFIG_BOOTP_GATEWAY | |
127 | #define CONFIG_BOOTP_HOSTNAME | |
128 | #define CONFIG_BOOTP_BOOTPATH | |
129 | #define CONFIG_BOOTP_BOOTFILESIZE | |
130 | ||
d4ca31c4 WD |
131 | |
132 | #define CONFIG_MAC_PARTITION | |
133 | #define CONFIG_DOS_PARTITION | |
134 | ||
a6cccaea WD |
135 | #undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */ |
136 | ||
137 | #define CONFIG_TIMESTAMP /* but print image timestmps */ | |
d4ca31c4 | 138 | |
d4ca31c4 | 139 | |
2694690e JL |
140 | /* |
141 | * Command line configuration. | |
142 | */ | |
2694690e JL |
143 | #define CONFIG_CMD_ASKENV |
144 | #define CONFIG_CMD_DHCP | |
145 | #define CONFIG_CMD_EEPROM | |
9a63b7f4 | 146 | #define CONFIG_CMD_EXT2 |
2694690e | 147 | #define CONFIG_CMD_IDE |
29f8f58f | 148 | #define CONFIG_CMD_JFFS2 |
29f8f58f WD |
149 | #define CONFIG_CMD_SNTP |
150 | ||
151 | ||
152 | #define CONFIG_NETCONSOLE | |
2694690e | 153 | |
d4ca31c4 WD |
154 | |
155 | /* | |
156 | * Miscellaneous configurable options | |
157 | */ | |
6d0f6bcf | 158 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
d4ca31c4 | 159 | |
2751a95a | 160 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
6d0f6bcf | 161 | #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ |
d4ca31c4 | 162 | |
2694690e | 163 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 164 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
d4ca31c4 | 165 | #else |
6d0f6bcf | 166 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
d4ca31c4 | 167 | #endif |
6d0f6bcf JCPV |
168 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
169 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
170 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
d4ca31c4 | 171 | |
6d0f6bcf JCPV |
172 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
173 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
d4ca31c4 | 174 | |
6d0f6bcf | 175 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
d4ca31c4 | 176 | |
d4ca31c4 WD |
177 | /* |
178 | * Low Level Configuration Settings | |
179 | * (address mappings, register initial values, etc.) | |
180 | * You should know what you are doing if you make changes here. | |
181 | */ | |
182 | /*----------------------------------------------------------------------- | |
183 | * Internal Memory Mapped Register | |
184 | */ | |
6d0f6bcf | 185 | #define CONFIG_SYS_IMMR 0xFFF00000 |
d4ca31c4 WD |
186 | |
187 | /*----------------------------------------------------------------------- | |
188 | * Definitions for initial stack pointer and data area (in DPRAM) | |
189 | */ | |
6d0f6bcf | 190 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
553f0982 | 191 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
25ddd1fb | 192 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 193 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
d4ca31c4 WD |
194 | |
195 | /*----------------------------------------------------------------------- | |
196 | * Start addresses for the final memory configuration | |
197 | * (Set up by the startup code) | |
6d0f6bcf | 198 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
d4ca31c4 | 199 | */ |
6d0f6bcf JCPV |
200 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
201 | #define CONFIG_SYS_FLASH_BASE 0x40000000 | |
202 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
203 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
204 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ | |
d4ca31c4 WD |
205 | |
206 | /* | |
207 | * For booting Linux, the board info and command line data | |
208 | * have to be in the first 8 MB of memory, since this is | |
209 | * the maximum mapped by the Linux kernel during initialization. | |
210 | */ | |
6d0f6bcf | 211 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
d4ca31c4 WD |
212 | |
213 | /*----------------------------------------------------------------------- | |
214 | * FLASH organization | |
215 | */ | |
e318d9e9 | 216 | /* use CFI flash driver */ |
6d0f6bcf | 217 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
00b1883a | 218 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
6d0f6bcf JCPV |
219 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
220 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
221 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 | |
222 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
223 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
d4ca31c4 | 224 | |
5a1aceb0 | 225 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
226 | #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ |
227 | #define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ | |
228 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ | |
d4ca31c4 WD |
229 | |
230 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
231 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) |
232 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
d4ca31c4 | 233 | |
6d0f6bcf | 234 | #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ |
67c31036 | 235 | |
7c803be2 WD |
236 | #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ |
237 | ||
29f8f58f WD |
238 | /*----------------------------------------------------------------------- |
239 | * Dynamic MTD partition support | |
240 | */ | |
68d7d651 | 241 | #define CONFIG_CMD_MTDPARTS |
942556a9 SR |
242 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
243 | #define CONFIG_FLASH_CFI_MTD | |
29f8f58f WD |
244 | #define MTDIDS_DEFAULT "nor0=TQM8xxM-0" |
245 | ||
246 | #define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ | |
247 | "128k(dtb)," \ | |
248 | "1920k(kernel)," \ | |
249 | "5632(rootfs)," \ | |
cd82919e | 250 | "4m(data)" |
29f8f58f | 251 | |
d4ca31c4 WD |
252 | /*----------------------------------------------------------------------- |
253 | * Hardware Information Block | |
254 | */ | |
6d0f6bcf JCPV |
255 | #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ |
256 | #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ | |
257 | #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ | |
d4ca31c4 WD |
258 | |
259 | /*----------------------------------------------------------------------- | |
260 | * Cache Configuration | |
261 | */ | |
6d0f6bcf | 262 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
2694690e | 263 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 264 | #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
d4ca31c4 WD |
265 | #endif |
266 | ||
267 | /*----------------------------------------------------------------------- | |
268 | * SYPCR - System Protection Control 11-9 | |
269 | * SYPCR can only be written once after reset! | |
270 | *----------------------------------------------------------------------- | |
271 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
272 | */ | |
273 | #if defined(CONFIG_WATCHDOG) | |
6d0f6bcf | 274 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
d4ca31c4 WD |
275 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
276 | #else | |
6d0f6bcf | 277 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
d4ca31c4 WD |
278 | #endif |
279 | ||
280 | /*----------------------------------------------------------------------- | |
281 | * SIUMCR - SIU Module Configuration 11-6 | |
282 | *----------------------------------------------------------------------- | |
283 | * PCMCIA config., multi-function pin tri-state | |
284 | */ | |
c178d3da | 285 | #ifndef CONFIG_CAN_DRIVER |
6d0f6bcf | 286 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
d4ca31c4 | 287 | #else /* we must activate GPL5 in the SIUMCR for CAN */ |
6d0f6bcf | 288 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
d4ca31c4 WD |
289 | #endif /* CONFIG_CAN_DRIVER */ |
290 | ||
291 | /*----------------------------------------------------------------------- | |
292 | * TBSCR - Time Base Status and Control 11-26 | |
293 | *----------------------------------------------------------------------- | |
294 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
295 | */ | |
6d0f6bcf | 296 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
d4ca31c4 | 297 | |
d4ca31c4 WD |
298 | /*----------------------------------------------------------------------- |
299 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
300 | *----------------------------------------------------------------------- | |
301 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
302 | */ | |
6d0f6bcf | 303 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
d4ca31c4 | 304 | |
d4ca31c4 WD |
305 | /*----------------------------------------------------------------------- |
306 | * SCCR - System Clock and reset Control Register 15-27 | |
307 | *----------------------------------------------------------------------- | |
308 | * Set clock output, timebase and RTC source and divider, | |
309 | * power management and some other internal clocks | |
310 | */ | |
311 | #define SCCR_MASK SCCR_EBDF11 | |
6d0f6bcf | 312 | #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
d4ca31c4 WD |
313 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ |
314 | SCCR_DFALCD00) | |
d4ca31c4 WD |
315 | |
316 | /*----------------------------------------------------------------------- | |
317 | * PCMCIA stuff | |
318 | *----------------------------------------------------------------------- | |
319 | * | |
320 | */ | |
6d0f6bcf JCPV |
321 | #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
322 | #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) | |
323 | #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) | |
324 | #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) | |
325 | #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) | |
326 | #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) | |
327 | #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) | |
328 | #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) | |
d4ca31c4 WD |
329 | |
330 | /*----------------------------------------------------------------------- | |
331 | * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) | |
332 | *----------------------------------------------------------------------- | |
333 | */ | |
334 | ||
8d1165e1 | 335 | #define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ |
c178d3da | 336 | #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ |
d4ca31c4 | 337 | |
c178d3da WD |
338 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
339 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
d4ca31c4 WD |
340 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ |
341 | ||
6d0f6bcf JCPV |
342 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
343 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
d4ca31c4 | 344 | |
6d0f6bcf | 345 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
d4ca31c4 | 346 | |
6d0f6bcf | 347 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR |
d4ca31c4 WD |
348 | |
349 | /* Offset for data I/O */ | |
6d0f6bcf | 350 | #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
d4ca31c4 WD |
351 | |
352 | /* Offset for normal register accesses */ | |
6d0f6bcf | 353 | #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
d4ca31c4 WD |
354 | |
355 | /* Offset for alternate registers */ | |
6d0f6bcf | 356 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 |
d4ca31c4 WD |
357 | |
358 | /*----------------------------------------------------------------------- | |
359 | * | |
360 | *----------------------------------------------------------------------- | |
361 | * | |
362 | */ | |
6d0f6bcf | 363 | #define CONFIG_SYS_DER 0 |
d4ca31c4 WD |
364 | |
365 | /* | |
366 | * Init Memory Controller: | |
367 | * | |
368 | * BR0/1 and OR0/1 (FLASH) | |
369 | */ | |
370 | ||
371 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ | |
372 | #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ | |
373 | ||
374 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
375 | * restrict access enough to keep SRAM working (if any) | |
376 | * but not too much to meddle with FLASH accesses | |
377 | */ | |
6d0f6bcf JCPV |
378 | #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
379 | #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ | |
d4ca31c4 WD |
380 | |
381 | /* | |
c178d3da | 382 | * FLASH timing: Default value of OR0 after reset |
d4ca31c4 | 383 | */ |
6d0f6bcf | 384 | #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \ |
c178d3da | 385 | OR_SCY_15_CLK | OR_TRLX) |
d4ca31c4 | 386 | |
6d0f6bcf JCPV |
387 | #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
388 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) | |
389 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) | |
d4ca31c4 | 390 | |
6d0f6bcf JCPV |
391 | #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP |
392 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM | |
393 | #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) | |
d4ca31c4 WD |
394 | |
395 | /* | |
396 | * BR2/3 and OR2/3 (SDRAM) | |
397 | * | |
398 | */ | |
399 | #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ | |
400 | #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ | |
c178d3da | 401 | #define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */ |
d4ca31c4 WD |
402 | |
403 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ | |
6d0f6bcf | 404 | #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 |
d4ca31c4 | 405 | |
6d0f6bcf JCPV |
406 | #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) |
407 | #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
d4ca31c4 | 408 | |
c178d3da | 409 | #ifndef CONFIG_CAN_DRIVER |
6d0f6bcf JCPV |
410 | #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM |
411 | #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
d4ca31c4 | 412 | #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ |
6d0f6bcf JCPV |
413 | #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ |
414 | #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ | |
415 | #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) | |
416 | #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ | |
d4ca31c4 WD |
417 | BR_PS_8 | BR_MS_UPMB | BR_V ) |
418 | #endif /* CONFIG_CAN_DRIVER */ | |
419 | ||
c178d3da | 420 | /* |
c178d3da WD |
421 | * 4096 Rows from SDRAM example configuration |
422 | * 1000 factor s -> ms | |
423 | * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration | |
424 | * 4 Number of refresh cycles per period | |
425 | * 64 Refresh cycle in ms per number of rows | |
426 | */ | |
6d0f6bcf | 427 | #define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) |
c178d3da | 428 | |
d4ca31c4 | 429 | /* |
d43e489b MK |
430 | * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad) |
431 | * | |
432 | * CPUclock(MHz) * 31.2 | |
6d0f6bcf | 433 | * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0 |
d43e489b MK |
434 | * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16 |
435 | * | |
6d0f6bcf JCPV |
436 | * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us |
437 | * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us | |
438 | * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us | |
439 | * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us | |
d43e489b MK |
440 | * |
441 | * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will | |
442 | * be met also in the default configuration, i.e. if environment variable | |
443 | * 'cpuclk' is not set. | |
d4ca31c4 | 444 | */ |
6d0f6bcf | 445 | #define CONFIG_SYS_MAMR_PTA 97 |
d4ca31c4 WD |
446 | |
447 | /* | |
d43e489b | 448 | * Memory Periodic Timer Prescaler Register (MPTPR) values. |
d4ca31c4 | 449 | */ |
d43e489b | 450 | /* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */ |
6d0f6bcf | 451 | #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 |
d43e489b | 452 | /* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */ |
6d0f6bcf | 453 | #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 |
d4ca31c4 WD |
454 | |
455 | /* | |
456 | * MAMR settings for SDRAM | |
457 | */ | |
458 | ||
459 | /* 8 column SDRAM */ | |
6d0f6bcf | 460 | #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
d4ca31c4 WD |
461 | MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ |
462 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
463 | /* 9 column SDRAM */ | |
6d0f6bcf | 464 | #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
d4ca31c4 WD |
465 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ |
466 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
c178d3da | 467 | /* 10 column SDRAM */ |
6d0f6bcf | 468 | #define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
c178d3da WD |
469 | MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ |
470 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
d4ca31c4 | 471 | |
d4ca31c4 WD |
472 | #define CONFIG_SCC1_ENET |
473 | #define CONFIG_FEC_ENET | |
48690d80 | 474 | #define CONFIG_ETHPRIME "SCC" |
d4ca31c4 | 475 | |
7026ead0 HS |
476 | /* pass open firmware flat tree */ |
477 | #define CONFIG_OF_LIBFDT 1 | |
478 | #define CONFIG_OF_BOARD_SETUP 1 | |
479 | #define CONFIG_HWCONFIG 1 | |
480 | ||
d4ca31c4 | 481 | #endif /* __CONFIG_H */ |