]>
Commit | Line | Data |
---|---|---|
1cb8e980 | 1 | /* |
531716e1 | 2 | * (C) Copyright 2002, 2003 |
1cb8e980 WD |
3 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
4 | * Marius Groeger <mgroeger@sysgo.de> | |
792a09eb | 5 | * Gary Jennejohn <garyj@denx.de> |
1cb8e980 WD |
6 | * David Mueller <d.mueller@elsoft.ch> |
7 | * | |
8 | * Configuation settings for the MPL VCMA9 board. | |
9 | * | |
1a459660 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
1cb8e980 WD |
11 | */ |
12 | ||
13 | #ifndef __CONFIG_H | |
14 | #define __CONFIG_H | |
15 | ||
c686537f DMEA |
16 | |
17 | #define MACH_TYPE_MPL_VCMA9 227 | |
18 | ||
1cb8e980 WD |
19 | /* |
20 | * High Level Configuration Options | |
21 | * (easy to change) | |
22 | */ | |
f2168440 | 23 | #define CONFIG_S3C24X0 /* This is a SAMSUNG S3C24x0-type SoC */ |
f3108304 DMEA |
24 | #define CONFIG_S3C2410 /* specifically a SAMSUNG S3C2410 SoC */ |
25 | #define CONFIG_VCMA9 /* on a MPL VCMA9 Board */ | |
c686537f | 26 | #define CONFIG_MACH_TYPE MACH_TYPE_MPL_VCMA9 /* Machine type */ |
1cb8e980 | 27 | |
0bf42fec DMEA |
28 | #define CONFIG_SYS_TEXT_BASE 0x0 |
29 | ||
13bd4d87 DMEA |
30 | #define CONFIG_SYS_GENERIC_BOARD |
31 | ||
f3108304 | 32 | #define CONFIG_SYS_ARM_CACHE_WRITETHROUGH |
1cb8e980 | 33 | |
f3108304 DMEA |
34 | /* input clock of PLL (VCMA9 has 12MHz input clock) */ |
35 | #define CONFIG_SYS_CLK_FREQ 12000000 | |
1cb8e980 | 36 | |
f3108304 DMEA |
37 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
38 | #define CONFIG_SETUP_MEMORY_TAGS | |
39 | #define CONFIG_INITRD_TAG | |
a5562901 | 40 | |
a1aa0bb5 JL |
41 | /* |
42 | * BOOTP options | |
43 | */ | |
44 | #define CONFIG_BOOTP_BOOTFILESIZE | |
45 | #define CONFIG_BOOTP_BOOTPATH | |
46 | #define CONFIG_BOOTP_GATEWAY | |
47 | #define CONFIG_BOOTP_HOSTNAME | |
48 | ||
a5562901 JL |
49 | /* |
50 | * Command line configuration. | |
51 | */ | |
a5562901 JL |
52 | #define CONFIG_CMD_CACHE |
53 | #define CONFIG_CMD_EEPROM | |
54 | #define CONFIG_CMD_I2C | |
55 | #define CONFIG_CMD_USB | |
56 | #define CONFIG_CMD_REGINFO | |
a5562901 JL |
57 | #define CONFIG_CMD_DATE |
58 | #define CONFIG_CMD_ELF | |
59 | #define CONFIG_CMD_DHCP | |
60 | #define CONFIG_CMD_PING | |
61 | #define CONFIG_CMD_BSP | |
f3108304 | 62 | #define CONFIG_CMD_NAND |
a5562901 | 63 | |
9660e442 | 64 | #define CONFIG_BOARD_LATE_INIT |
1cb8e980 | 65 | |
6d0f6bcf | 66 | #define CONFIG_SYS_HUSH_PARSER |
f3108304 DMEA |
67 | #define CONFIG_CMDLINE_EDITING |
68 | ||
69 | /* | |
1cb8e980 WD |
70 | * I2C stuff: |
71 | * the MPL VCMA9 is equipped with an ATMEL 24C256 EEPROM at | |
72 | * address 0x50 with 16bit addressing | |
f3108304 | 73 | */ |
2d8f1e27 | 74 | #define CONFIG_SYS_I2C |
1cb8e980 | 75 | |
f3108304 | 76 | /* we use the built-in I2C controller */ |
2d8f1e27 PW |
77 | #define CONFIG_SYS_I2C_S3C24X0 |
78 | #define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* I2C speed */ | |
79 | #define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x7F /* I2C slave addr */ | |
f3108304 | 80 | |
6d0f6bcf JCPV |
81 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
82 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
f3108304 DMEA |
83 | /* use EEPROM for environment vars */ |
84 | #define CONFIG_ENV_IS_IN_EEPROM 1 | |
85 | /* environment starts at offset 0 */ | |
86 | #define CONFIG_ENV_OFFSET 0x000 | |
87 | /* 2KB should be more than enough */ | |
88 | #define CONFIG_ENV_SIZE 0x800 | |
1cb8e980 | 89 | |
6d0f6bcf | 90 | #undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW |
f3108304 DMEA |
91 | /* 64 bytes page write mode on 24C256 */ |
92 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 | |
6d0f6bcf | 93 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 |
1cb8e980 | 94 | |
1cb8e980 WD |
95 | /* |
96 | * Hardware drivers | |
97 | */ | |
f3108304 DMEA |
98 | #define CONFIG_CS8900 /* we have a CS8900 on-board */ |
99 | #define CONFIG_CS8900_BASE 0x20000300 | |
100 | #define CONFIG_CS8900_BUS16 | |
1cb8e980 WD |
101 | |
102 | /* | |
103 | * select serial console configuration | |
104 | */ | |
300f99f4 | 105 | #define CONFIG_S3C24X0_SERIAL |
f3108304 | 106 | #define CONFIG_SERIAL1 1 /* we use SERIAL 1 on VCMA9 */ |
1cb8e980 | 107 | |
f3108304 DMEA |
108 | /* USB support (currently only works with D-cache off) */ |
109 | #define CONFIG_USB_OHCI | |
fb24ffc0 | 110 | #define CONFIG_USB_OHCI_S3C24XX |
f3108304 DMEA |
111 | #define CONFIG_USB_KEYBOARD |
112 | #define CONFIG_USB_STORAGE | |
113 | #define CONFIG_DOS_PARTITION | |
48b42616 WD |
114 | |
115 | /* Enable needed helper functions */ | |
f3108304 | 116 | #define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */ |
48b42616 | 117 | |
f3108304 DMEA |
118 | /* RTC */ |
119 | #define CONFIG_RTC_S3C24X0 | |
48b42616 WD |
120 | |
121 | ||
1cb8e980 WD |
122 | /* allow to overwrite serial and ethaddr */ |
123 | #define CONFIG_ENV_OVERWRITE | |
124 | ||
f3108304 | 125 | #define CONFIG_BAUDRATE 9600 |
1cb8e980 | 126 | |
f3108304 DMEA |
127 | #define CONFIG_BOOTDELAY 5 |
128 | #define CONFIG_BOOT_RETRY_TIME -1 | |
129 | #define CONFIG_RESET_TO_RETRY | |
130 | #define CONFIG_ZERO_BOOTDELAY_CHECK | |
a2663ea4 | 131 | |
f3108304 DMEA |
132 | #define CONFIG_NETMASK 255.255.255.0 |
133 | #define CONFIG_IPADDR 10.0.0.110 | |
134 | #define CONFIG_SERVERIP 10.0.0.1 | |
1cb8e980 | 135 | |
a5562901 | 136 | #if defined(CONFIG_CMD_KGDB) |
f3108304 DMEA |
137 | /* speed to run kgdb serial port */ |
138 | #define CONFIG_KGDB_BAUDRATE 115200 | |
1cb8e980 WD |
139 | #endif |
140 | ||
f3108304 DMEA |
141 | /* Miscellaneous configurable options */ |
142 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
143 | #define CONFIG_SYS_PROMPT "VCMA9 # " | |
144 | #define CONFIG_SYS_CBSIZE 256 | |
145 | /* Print Buffer Size */ | |
146 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
147 | #define CONFIG_SYS_MAXARGS 16 | |
148 | /* Boot Argument Buffer Size */ | |
149 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
150 | ||
3d3206f1 | 151 | #define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ |
f3108304 | 152 | #define CONFIG_DISPLAY_BOARDINFO /* Display board info */ |
1cb8e980 | 153 | |
f3108304 DMEA |
154 | #define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */ |
155 | #define CONFIG_SYS_MEMTEST_END 0x31FFFFFF /* 32 MB in DRAM */ | |
531716e1 | 156 | |
6d0f6bcf | 157 | #define CONFIG_SYS_ALT_MEMTEST |
f3108304 | 158 | #define CONFIG_SYS_LOAD_ADDR 0x30800000 |
1cb8e980 | 159 | |
f3108304 | 160 | /* we configure PWM Timer 4 to 1ms 1000Hz */ |
1cb8e980 | 161 | |
f3108304 DMEA |
162 | /* support additional compression methods */ |
163 | #define CONFIG_BZIP2 | |
164 | #define CONFIG_LZO | |
165 | #define CONFIG_LZMA | |
a2663ea4 | 166 | |
f3108304 | 167 | /* Ident */ |
48b42616 WD |
168 | /*#define VERSION_TAG "released"*/ |
169 | #define VERSION_TAG "unstable" | |
f3108304 DMEA |
170 | #define CONFIG_IDENT_STRING "\n(c) 2003 - 2011 by MPL AG Switzerland, " \ |
171 | "MEV-10080-001 " VERSION_TAG | |
48b42616 | 172 | |
f3108304 DMEA |
173 | /* Physical Memory Map */ |
174 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ | |
175 | #define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ | |
176 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ | |
1cb8e980 | 177 | |
6d754843 | 178 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
1cb8e980 | 179 | |
f3108304 | 180 | /* FLASH and environment organization */ |
1cb8e980 | 181 | |
6d754843 DMEA |
182 | #define CONFIG_SYS_FLASH_CFI |
183 | #define CONFIG_FLASH_CFI_DRIVER | |
184 | #define CONFIG_FLASH_CFI_LEGACY | |
185 | #define CONFIG_SYS_FLASH_LEGACY_512Kx16 | |
186 | #define CONFIG_FLASH_SHOW_PROGRESS 45 | |
6d0f6bcf | 187 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
f3108304 | 188 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
6d754843 | 189 | #define CONFIG_SYS_MAX_FLASH_SECT (19) |
1cb8e980 | 190 | |
f3108304 DMEA |
191 | /* |
192 | * Size of malloc() pool | |
193 | * BZIP2 / LZO / LZMA need a lot of RAM | |
194 | */ | |
195 | #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) | |
196 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) | |
197 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
1cb8e980 | 198 | |
f3108304 DMEA |
199 | /* NAND configuration */ |
200 | #ifdef CONFIG_CMD_NAND | |
201 | #define CONFIG_NAND_S3C2410 | |
202 | #define CONFIG_SYS_S3C2410_NAND_HWECC | |
203 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
f3108304 DMEA |
204 | #define CONFIG_SYS_NAND_BASE 0x4E000000 |
205 | #define CONFIG_S3C24XX_CUSTOM_NAND_TIMING | |
206 | #define CONFIG_S3C24XX_TACLS 1 | |
207 | #define CONFIG_S3C24XX_TWRPH0 5 | |
208 | #define CONFIG_S3C24XX_TWRPH1 3 | |
209 | #endif | |
48b42616 | 210 | |
f3108304 | 211 | #define MULTI_PURPOSE_SOCKET_ADDR 0x08000000 |
48b42616 | 212 | |
f3108304 DMEA |
213 | /* File system */ |
214 | #define CONFIG_CMD_FAT | |
f3108304 DMEA |
215 | #define CONFIG_CMD_UBI |
216 | #define CONFIG_CMD_UBIFS | |
217 | #define CONFIG_CMD_JFFS2 | |
218 | #define CONFIG_YAFFS2 | |
219 | #define CONFIG_RBTREE | |
220 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ | |
221 | #define CONFIG_MTD_PARTITIONS | |
222 | #define CONFIG_CMD_MTDPARTS | |
223 | #define CONFIG_LZO | |
48b42616 | 224 | |
d2d94571 DMEA |
225 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
226 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ | |
227 | GENERATED_GBL_DATA_SIZE) | |
228 | ||
f3108304 | 229 | #define CONFIG_BOARD_EARLY_INIT_F |
d2d94571 | 230 | |
f3108304 | 231 | #endif /* __CONFIG_H */ |