[people/ms/u-boot.git] / include / configs / adp-ae3xx.h

/*
 * Copyright (C) 2011 Andes Technology Corporation
 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <asm/arch-ae3xx/ae3xx.h>

/*
 * CPU and Board Configuration Options
 */
#define CONFIG_USE_INTERRUPT

#define CONFIG_SKIP_LOWLEVEL_INIT

#define CONFIG_SKIP_TRUNOFF_WATCHDOG

#define CONFIG_CMDLINE_EDITING
#define CONFIG_PANIC_HANG

#define CONFIG_SYS_ICACHE_OFF
#define CONFIG_SYS_DCACHE_OFF

#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_BOOTP_SERVERIP

#ifdef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_TEXT_BASE	0x00500000
#ifdef CONFIG_OF_CONTROL
#undef CONFIG_OF_SEPARATE
#define CONFIG_OF_EMBED
#endif
#else

#define CONFIG_SYS_TEXT_BASE	0x80000000
#endif

/*
 * Timer
 */
#define CONFIG_SYS_CLK_FREQ	39062500
#define VERSION_CLOCK		CONFIG_SYS_CLK_FREQ

/*
 * Use Externel CLOCK or PCLK
 */
#undef CONFIG_FTRTC010_EXTCLK

#ifndef CONFIG_FTRTC010_EXTCLK
#define CONFIG_FTRTC010_PCLK
#endif

#ifdef CONFIG_FTRTC010_EXTCLK
#define TIMER_CLOCK	32768			/* CONFIG_FTRTC010_EXTCLK */
#else
#define TIMER_CLOCK	CONFIG_SYS_HZ		/* CONFIG_FTRTC010_PCLK */
#endif

#define TIMER_LOAD_VAL	0xffffffff

/*
 * Real Time Clock
 */
#define CONFIG_RTC_FTRTC010

/*
 * Real Time Clock Divider
 * RTC_DIV_COUNT			(OSC_CLK/OSC_5MHZ)
 */
#define OSC_5MHZ			(5*1000000)
#define OSC_CLK				(4*OSC_5MHZ)
#define RTC_DIV_COUNT			(0.5)	/* Why?? */

/*
 * Serial console configuration
 */

/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
#define CONFIG_CONS_INDEX		1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_COM1		CONFIG_FTUART010_02_BASE
#ifndef CONFIG_DM_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	-4
#endif
#define CONFIG_SYS_NS16550_CLK		((18432000 * 20) / 25)	/* AG101P */

/*
 * SD (MMC) controller
 */
#define CONFIG_FTSDC010
#define CONFIG_FTSDC010_NUMBER		1
#define CONFIG_FTSDC010_SDIO

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory */

/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE

/*
 * Size of malloc() pool
 */
/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
#define CONFIG_SYS_MALLOC_LEN		(512 << 10)

/*
 * Physical Memory Map
 */
#define PHYS_SDRAM_0	0x00000000  /* SDRAM Bank #1 */

#define PHYS_SDRAM_1 \
	(PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)	/* SDRAM Bank #2 */

#define CONFIG_NR_DRAM_BANKS	2		/* we have 2 bank of DRAM */

#define PHYS_SDRAM_0_SIZE	0x20000000	/* 512 MB */
#define PHYS_SDRAM_1_SIZE	0x20000000	/* 512 MB */

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_0

#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
					GENERATED_GBL_DATA_SIZE)

/*
 * Load address and memory test area should agree with
 * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
 */
#define CONFIG_SYS_LOAD_ADDR		0x300000

/* memtest works on 63 MB in DRAM */
#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_0
#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_0 + 0x03F00000)

/*
 * Static memory controller configuration
 */
#define CONFIG_FTSMC020

#ifdef CONFIG_FTSMC020
#include <faraday/ftsmc020.h>

#define CONFIG_SYS_FTSMC020_CONFIGS	{			\
	{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },	\
	{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },	\
}

#ifndef CONFIG_SKIP_LOWLEVEL_INIT	/* FLASH is on BANK 0 */
#define FTSMC020_BANK0_LOWLV_CONFIG	(FTSMC020_BANK_ENABLE	|	\
					 FTSMC020_BANK_SIZE_32M	|	\
					 FTSMC020_BANK_MBW_32)

#define FTSMC020_BANK0_LOWLV_TIMING	(FTSMC020_TPR_RBE	|	\
					 FTSMC020_TPR_AST(1)	|	\
					 FTSMC020_TPR_CTW(1)	|	\
					 FTSMC020_TPR_ATI(1)	|	\
					 FTSMC020_TPR_AT2(1)	|	\
					 FTSMC020_TPR_WTC(1)	|	\
					 FTSMC020_TPR_AHT(1)	|	\
					 FTSMC020_TPR_TRNA(1))
#endif

/*
 * FLASH on ADP_AG101P is connected to BANK0
 * Just disalbe the other BANK to avoid detection error.
 */
#define FTSMC020_BANK0_CONFIG	(FTSMC020_BANK_ENABLE             |	\
				 FTSMC020_BANK_BASE(PHYS_FLASH_1) |	\
				 FTSMC020_BANK_SIZE_32M           |	\
				 FTSMC020_BANK_MBW_32)

#define FTSMC020_BANK0_TIMING	(FTSMC020_TPR_AST(3)   |	\
				 FTSMC020_TPR_CTW(3)   |	\
				 FTSMC020_TPR_ATI(0xf) |	\
				 FTSMC020_TPR_AT2(3)   |	\
				 FTSMC020_TPR_WTC(3)   |	\
				 FTSMC020_TPR_AHT(3)   |	\
				 FTSMC020_TPR_TRNA(0xf))

#define FTSMC020_BANK1_CONFIG	(0x00)
#define FTSMC020_BANK1_TIMING	(0x00)
#endif /* CONFIG_FTSMC020 */

/*
 * FLASH and environment organization
 */
/* use CFI framework */
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER

#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_CFI_FLASH_STATUS_POLL

/* support JEDEC */
#ifdef CONFIG_CFI_FLASH
#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT	1
#endif

/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
#define PHYS_FLASH_1			0x88000000	/* BANK 0 */
#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
#define CONFIG_SYS_FLASH_BANKS_LIST	{ PHYS_FLASH_1, }
#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* TO for Flash Erase (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* TO for Flash Write (ms) */

/* max number of memory banks */
/*
 * There are 4 banks supported for this Controller,
 * but we have only 1 bank connected to flash on board
 */
#ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#endif
#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}

/* max number of sectors on one chip */
#define CONFIG_FLASH_SECTOR_SIZE	(0x10000*2)
#define CONFIG_ENV_SECT_SIZE		CONFIG_FLASH_SECTOR_SIZE
#define CONFIG_SYS_MAX_FLASH_SECT	512

/* environments */
#define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE + 0x140000)
#define CONFIG_ENV_SIZE			8192
#define CONFIG_ENV_OVERWRITE

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 16 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */

/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)
/* Increase max gunzip size */
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)

#endif	/* __CONFIG_H */
Commit	Line	Data
b841b6e9	1	/*
	2	* Copyright (C) 2011 Andes Technology Corporation
	3	* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
	4	* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
	5	*
	6	* SPDX-License-Identifier: GPL-2.0+
	7	*/
	8
	9	#ifndef __CONFIG_H
	10	#define __CONFIG_H
	11
	12	#include <asm/arch-ae3xx/ae3xx.h>
	13
	14	/*
	15	* CPU and Board Configuration Options
	16	*/
	17	#define CONFIG_USE_INTERRUPT
	18
	19	#define CONFIG_SKIP_LOWLEVEL_INIT
	20
	21	#define CONFIG_SKIP_TRUNOFF_WATCHDOG
	22
	23	#define CONFIG_CMDLINE_EDITING
	24	#define CONFIG_PANIC_HANG
	25
	26	#define CONFIG_SYS_ICACHE_OFF
	27	#define CONFIG_SYS_DCACHE_OFF
	28
	29	#define CONFIG_BOOTP_SEND_HOSTNAME
	30	#define CONFIG_BOOTP_SERVERIP
	31
	32	#ifdef CONFIG_SKIP_LOWLEVEL_INIT
	33	#define CONFIG_SYS_TEXT_BASE 0x00500000
	34	#ifdef CONFIG_OF_CONTROL
	35	#undef CONFIG_OF_SEPARATE
	36	#define CONFIG_OF_EMBED
	37	#endif
	38	#else
	39
	40	#define CONFIG_SYS_TEXT_BASE 0x80000000
	41	#endif
	42
	43	/*
	44	* Timer
	45	*/
	46	#define CONFIG_SYS_CLK_FREQ 39062500
	47	#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
	48
	49	/*
	50	* Use Externel CLOCK or PCLK
	51	*/
	52	#undef CONFIG_FTRTC010_EXTCLK
	53
	54	#ifndef CONFIG_FTRTC010_EXTCLK
	55	#define CONFIG_FTRTC010_PCLK
	56	#endif
	57
	58	#ifdef CONFIG_FTRTC010_EXTCLK
	59	#define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
	60	#else
	61	#define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
	62	#endif
	63
	64	#define TIMER_LOAD_VAL 0xffffffff
65
66	/*
67	* Real Time Clock
68	*/
69	#define CONFIG_RTC_FTRTC010
70
71	/*
72	* Real Time Clock Divider
73	* RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
74	*/
75	#define OSC_5MHZ (5*1000000)
76	#define OSC_CLK (4*OSC_5MHZ)
77	#define RTC_DIV_COUNT (0.5) /* Why?? */
78
79	/*
80	* Serial console configuration
81	*/
82
83	/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
84	#define CONFIG_CONS_INDEX 1
85	#define CONFIG_SYS_NS16550_SERIAL
86	#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
87	#ifndef CONFIG_DM_SERIAL
88	#define CONFIG_SYS_NS16550_REG_SIZE -4
89	#endif
90	#define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */
91
b841b6e9	92	/*
	93	* SD (MMC) controller
	94	*/
	95	#define CONFIG_FTSDC010
	96	#define CONFIG_FTSDC010_NUMBER 1
	97	#define CONFIG_FTSDC010_SDIO
	98
	99	/*
	100	* Miscellaneous configurable options
	101	*/
	102	#define CONFIG_SYS_LONGHELP /* undef to save memory */
b841b6e9	103
b841b6e9	104	/* Boot Argument Buffer Size */
	105	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	106
	107	/*
	108	* Size of malloc() pool
	109	*/
	110	/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
	111	#define CONFIG_SYS_MALLOC_LEN (512 << 10)
	112
	113	/*
	114	* Physical Memory Map
	115	*/
	116	#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
	117
	118	#define PHYS_SDRAM_1 \
	119	(PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
	120
	121	#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */
	122
	123	#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
	124	#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
	125
	126	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
	127
	128	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
	129	GENERATED_GBL_DATA_SIZE)
	130
	131	/*
	132	* Load address and memory test area should agree with
	133	* arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
	134	*/
	135	#define CONFIG_SYS_LOAD_ADDR 0x300000
	136
	137	/* memtest works on 63 MB in DRAM */
	138	#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
	139	#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000)
	140
	141	/*
	142	* Static memory controller configuration
	143	*/
	144	#define CONFIG_FTSMC020
	145
	146	#ifdef CONFIG_FTSMC020
	147	#include <faraday/ftsmc020.h>
	148
	149	#define CONFIG_SYS_FTSMC020_CONFIGS { \
	150	{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
	151	{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
	152	}
	153
	154	#ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */
	155	#define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE \| \
	156	FTSMC020_BANK_SIZE_32M \| \
	157	FTSMC020_BANK_MBW_32)
	158
	159	#define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE \| \
	160	FTSMC020_TPR_AST(1) \| \
	161	FTSMC020_TPR_CTW(1) \| \
	162	FTSMC020_TPR_ATI(1) \| \
	163	FTSMC020_TPR_AT2(1) \| \
	164	FTSMC020_TPR_WTC(1) \| \
	165	FTSMC020_TPR_AHT(1) \| \
	166	FTSMC020_TPR_TRNA(1))
	167	#endif
168
169	/*
170	* FLASH on ADP_AG101P is connected to BANK0
171	* Just disalbe the other BANK to avoid detection error.
172	*/
173	#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE \| \
174	FTSMC020_BANK_BASE(PHYS_FLASH_1) \| \
175	FTSMC020_BANK_SIZE_32M \| \
176	FTSMC020_BANK_MBW_32)
177
178	#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) \| \
179	FTSMC020_TPR_CTW(3) \| \
180	FTSMC020_TPR_ATI(0xf) \| \
181	FTSMC020_TPR_AT2(3) \| \
182	FTSMC020_TPR_WTC(3) \| \
183	FTSMC020_TPR_AHT(3) \| \
184	FTSMC020_TPR_TRNA(0xf))
185
186	#define FTSMC020_BANK1_CONFIG (0x00)
187	#define FTSMC020_BANK1_TIMING (0x00)
188	#endif /* CONFIG_FTSMC020 */
189
190	/*
191	* FLASH and environment organization
192	*/
193	/* use CFI framework */
194	#define CONFIG_SYS_FLASH_CFI
195	#define CONFIG_FLASH_CFI_DRIVER
196
197	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
198	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
199	#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
200
201	/* support JEDEC */
202	#ifdef CONFIG_CFI_FLASH
203	#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
204	#endif
205
206	/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
207	#define PHYS_FLASH_1 0x88000000 /* BANK 0 */
208	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
209	#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
210	#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
211
212	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
213	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
214
215	/* max number of memory banks */
216	/*
217	* There are 4 banks supported for this Controller,
218	* but we have only 1 bank connected to flash on board
219	*/
220	#ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
221	#define CONFIG_SYS_MAX_FLASH_BANKS 1
222	#endif
223	#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
224
225	/* max number of sectors on one chip */
226	#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
227	#define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE
228	#define CONFIG_SYS_MAX_FLASH_SECT 512
229
230	/* environments */
b841b6e9	231	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000)
	232	#define CONFIG_ENV_SIZE 8192
	233	#define CONFIG_ENV_OVERWRITE
	234
	235	/*
	236	* For booting Linux, the board info and command line data
	237	* have to be in the first 16 MB of memory, since this is
	238	* the maximum mapped by the Linux kernel during initialization.
	239	*/
	240
	241	/* Initial Memory map for Linux*/
	242	#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
	243	/* Increase max gunzip size */
	244	#define CONFIG_SYS_BOOTM_LEN (64 << 20)
	245
	246	#endif /* __CONFIG_H */