[people/ms/u-boot.git] / include / configs / apf27.h

/*
 *
 * Configuration settings for the Armadeus Project motherboard APF27
 *
 * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
 *
 * SPDX-License-Identifier:    GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_ENV_VERSION	10
#define CONFIG_BOARD_NAME apf27

/*
 * SoC configurations
 */
#define CONFIG_MX27			/* This is a Freescale i.MX27 Chip */
#define CONFIG_MACH_TYPE	1698	/* APF27 */

/*
 * Enable the call to miscellaneous platform dependent initialization.
 */

/*
 * SPL
 */
#define CONFIG_SPL_TARGET	"u-boot-with-spl.bin"
#define CONFIG_SPL_MAX_SIZE	2048
#define CONFIG_SPL_TEXT_BASE    0xA0000000

/* NAND boot config */
#define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x800
#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_SIZE	CONFIG_SYS_MONITOR_LEN - 0x800

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2

#define CONFIG_HOSTNAME	CONFIG_BOARD_NAME
#define CONFIG_ROOTPATH	"/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root"

/*
 * Memory configurations
 */
#define CONFIG_NR_DRAM_POPULATED 1
#define CONFIG_NR_DRAM_BANKS	2

#define ACFG_SDRAM_MBYTE_SYZE 64

#define PHYS_SDRAM_1			0xA0000000
#define PHYS_SDRAM_2			0xB0000000
#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (512<<10))
#define CONFIG_SYS_MEMTEST_START	0xA0000000	/* memtest test area  */
#define CONFIG_SYS_MEMTEST_END		0xA0300000	/* 3 MiB RAM test */

#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE	\
		+ PHYS_SDRAM_1_SIZE - 0x0100000)

#define CONFIG_SYS_TEXT_BASE		0xA0000800

/*
 * FLASH organization
 */
#define	ACFG_MONITOR_OFFSET		0x00000000
#define	CONFIG_SYS_MONITOR_LEN		0x00100000	/* 1MiB */
#define	CONFIG_ENV_OVERWRITE
#define	CONFIG_ENV_OFFSET		0x00100000	/* NAND offset */
#define	CONFIG_ENV_SIZE			0x00020000	/* 128kB  */
#define CONFIG_ENV_RANGE		0X00080000	/* 512kB */
#define	CONFIG_ENV_OFFSET_REDUND	\
		(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)	/* +512kB */
#define	CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE	/* 512kB */
#define	CONFIG_FIRMWARE_OFFSET		0x00200000
#define	CONFIG_FIRMWARE_SIZE		0x00080000	/* 512kB  */
#define	CONFIG_KERNEL_OFFSET		0x00300000
#define	CONFIG_ROOTFS_OFFSET		0x00800000

#define CONFIG_MTDMAP			"mxc_nand.0"
#define MTDIDS_DEFAULT			"nand0=" CONFIG_MTDMAP
#define MTDPARTS_DEFAULT	"mtdparts=" CONFIG_MTDMAP \
				":1M(u-boot)ro," \
				"512K(env)," \
				"512K(env2)," \
				"512K(firmware)," \
				"512K(dtb)," \
				"5M(kernel)," \
				"-(rootfs)"

/*
 * U-Boot general configurations
 */
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_CBSIZE		2048		/* console I/O buffer */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
						/* Boot argument buffer size */
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
#define CONFIG_ENV_VARS_UBOOT_CONFIG
#define CONFIG_PREBOOT			"run check_flash check_env;"

/*
 * Boot Linux
 */
#define CONFIG_CMDLINE_TAG		/* send commandline to Kernel	*/
#define CONFIG_SETUP_MEMORY_TAGS	/* send memory definition to kernel */
#define CONFIG_INITRD_TAG		/* send initrd params	*/

#define	CONFIG_BOOTFILE		__stringify(CONFIG_BOARD_NAME) "-linux.bin"

#define ACFG_CONSOLE_DEV	ttySMX0
#define CONFIG_BOOTCOMMAND	"run ubifsboot"
#define CONFIG_SYS_AUTOLOAD	"no"
/*
 * Default load address for user programs and kernel
 */
#define CONFIG_LOADADDR			0xA0000000
#define	CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR

/*
 * Extra Environments
 */
#define CONFIG_EXTRA_ENV_SETTINGS \
	"env_version="		__stringify(CONFIG_ENV_VERSION)		"\0" \
	"consoledev="		__stringify(ACFG_CONSOLE_DEV)		"\0" \
	"mtdparts="		MTDPARTS_DEFAULT			"\0" \
	"partition=nand0,6\0"						\
	"u-boot_addr="		__stringify(ACFG_MONITOR_OFFSET)	"\0" \
	"env_addr="		__stringify(CONFIG_ENV_OFFSET)		"\0" \
	"firmware_addr="	__stringify(CONFIG_FIRMWARE_OFFSET)	"\0" \
	"firmware_size="	__stringify(CONFIG_FIRMWARE_SIZE)	"\0" \
	"kernel_addr="		__stringify(CONFIG_KERNEL_OFFSET)	"\0" \
	"rootfs_addr="		__stringify(CONFIG_ROOTFS_OFFSET)	"\0" \
	"board_name="		__stringify(CONFIG_BOARD_NAME)		"\0" \
	"kernel_addr_r=A0000000\0" \
	"check_env=if test -n ${flash_env_version}; "			\
		"then env default env_version; "			\
		"else env set flash_env_version ${env_version}; env save; "\
		"fi; "							\
		"if itest ${flash_env_version} < ${env_version}; then " \
			"echo \"*** Warning - Environment version"	\
			" change suggests: run flash_reset_env; reset\"; "\
			"env default flash_reset_env; "\
		"fi; \0"						\
	"check_flash=nand lock; nand unlock ${env_addr}; \0"	\
	"flash_reset_env=env default -f -a; saveenv; run update_env;"	\
		"echo Flash environment variables erased!\0"		\
	"download_uboot=tftpboot ${loadaddr} ${board_name}"		\
		"-u-boot-with-spl.bin\0"				\
	"flash_uboot=nand unlock ${u-boot_addr} ;"			\
		"nand erase.part u-boot;"		\
		"if nand write.trimffs ${fileaddr} ${u-boot_addr} ${filesize};"\
			"then nand lock; nand unlock ${env_addr};"	\
				"echo Flashing of uboot succeed;"	\
			"else echo Flashing of uboot failed;"		\
		"fi; \0"						\
	"update_uboot=run download_uboot flash_uboot\0"			\
	"download_env=tftpboot ${loadaddr} ${board_name}"		\
		"-u-boot-env.txt\0"				\
	"flash_env=env import -t ${loadaddr}; env save; \0"		\
	"update_env=run download_env flash_env\0"			\
	"update_all=run update_env update_uboot\0"			\
	"unlock_regs=mw 10000008 0; mw 10020008 0\0"			\

/*
 * Serial Driver
 */
#define CONFIG_MXC_UART
#define CONFIG_CONS_INDEX		1
#define CONFIG_MXC_UART_BASE		UART1_BASE

/*
 * GPIO
 */
#define CONFIG_MXC_GPIO

/*
 * NOR
 */

/*
 * NAND
 */
#define CONFIG_NAND_MXC

#define CONFIG_MXC_NAND_REGS_BASE	0xD8000000
#define CONFIG_SYS_NAND_BASE		CONFIG_MXC_NAND_REGS_BASE
#define CONFIG_SYS_MAX_NAND_DEVICE	1

#define CONFIG_MXC_NAND_HWECC
#define CONFIG_SYS_NAND_LARGEPAGE
#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
#define CONFIG_SYS_NAND_PAGE_SIZE	2048
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
#define CONFIG_SYS_NAND_PAGE_COUNT	CONFIG_SYS_NAND_BLOCK_SIZE / \
						CONFIG_SYS_NAND_PAGE_SIZE
#define CONFIG_SYS_NAND_SIZE		(256 * 1024 * 1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	11
#define NAND_MAX_CHIPS			1

#define CONFIG_FLASH_SHOW_PROGRESS	45
#define CONFIG_SYS_NAND_QUIET		1

/*
 * Partitions & Filsystems
 */
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_SUPPORT_VFAT

/*
 * Ethernet (on SOC imx FEC)
 */
#define CONFIG_FEC_MXC
#define CONFIG_FEC_MXC_PHYADDR		0x1f
#define CONFIG_MII				/* MII PHY management	*/

/*
 * FPGA
 */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_FPGA
#endif
#define CONFIG_FPGA_COUNT		1
#define CONFIG_FPGA_XILINX
#define CONFIG_FPGA_SPARTAN3
#define CONFIG_SYS_FPGA_WAIT		250 /* 250 ms */
#define CONFIG_SYS_FPGA_PROG_FEEDBACK
#define CONFIG_SYS_FPGA_CHECK_CTRLC
#define CONFIG_SYS_FPGA_CHECK_ERROR

/*
 * Fuses - IIM
 */
#ifdef CONFIG_CMD_IMX_FUSE
#define IIM_MAC_BANK		0
#define IIM_MAC_ROW		5
#define IIM0_SCC_KEY		11
#define IIM1_SUID		1
#endif

/*
 * I2C
 */

#ifdef CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
#define CONFIG_SYS_MXC_I2C1_SPEED	100000	/* 100 kHz */
#define CONFIG_SYS_MXC_I2C1_SLAVE	0x7F
#define CONFIG_SYS_MXC_I2C2_SPEED	100000	/* 100 kHz */
#define CONFIG_SYS_MXC_I2C2_SLAVE	0x7F
#define CONFIG_SYS_I2C_NOPROBES		{ }

#ifdef CONFIG_CMD_EEPROM
# define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM 24LC02 */
# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* bytes of address */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* msec */
#endif /* CONFIG_CMD_EEPROM */
#endif /* CONFIG_CMD_I2C */

/*
 * SD/MMC
 */
#ifdef CONFIG_CMD_MMC
#define CONFIG_MXC_MCI_REGS_BASE	0x10014000
#endif

/*
 * RTC
 */
#ifdef CONFIG_CMD_DATE
#define CONFIG_RTC_DS1374
#define CONFIG_SYS_RTC_BUS_NUM		0
#endif /* CONFIG_CMD_DATE */

/*
 * PLL
 *
 *  31 | x  |x| x x x x |x x x x x x x x x x |x x|x x x x|x x x x x x x x x x| 0
 *     |CPLM|X|----PD---|--------MFD---------|XXX|--MFI--|-----MFN-----------|
 */
#define CONFIG_MX27_CLK32		32768	/* 32768 or 32000 Hz crystal */

#if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
/* micron 64MB */
#define PHYS_SDRAM_1_SIZE			0x04000000 /* 64 MB */
#define PHYS_SDRAM_2_SIZE			0x04000000 /* 64 MB */
#endif

#if (ACFG_SDRAM_MBYTE_SYZE == 128)
/* micron 128MB */
#define PHYS_SDRAM_1_SIZE			0x08000000 /* 128 MB */
#define PHYS_SDRAM_2_SIZE			0x08000000 /* 128 MB */
#endif

#if (ACFG_SDRAM_MBYTE_SYZE == 256)
/* micron 256MB */
#define PHYS_SDRAM_1_SIZE			0x10000000 /* 256 MB */
#define PHYS_SDRAM_2_SIZE			0x10000000 /* 256 MB */
#endif

#endif /* __CONFIG_H */
Commit	Line	Data
bcc05c7a	1	/*
	2	*
	3	* Configuration settings for the Armadeus Project motherboard APF27
	4	*
	5	* Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
	6	*
	7	* SPDX-License-Identifier: GPL-2.0+
	8	*/
	9
	10	#ifndef __CONFIG_H
	11	#define __CONFIG_H
	12
bcc05c7a	13	#define CONFIG_ENV_VERSION 10
bcc05c7a	14	#define CONFIG_BOARD_NAME apf27
	15
	16	/*
	17	* SoC configurations
	18	*/
5d7b131d	19	#define CONFIG_MX27 /* This is a Freescale i.MX27 Chip */
bcc05c7a	20	#define CONFIG_MACH_TYPE 1698 /* APF27 */
bcc05c7a	21
	22	/*
	23	* Enable the call to miscellaneous platform dependent initialization.
	24	*/
bcc05c7a	25
bcc05c7a	26	/*
	27	* SPL
	28	*/
bcc05c7a	29	#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
bcc05c7a	30	#define CONFIG_SPL_MAX_SIZE 2048
	31	#define CONFIG_SPL_TEXT_BASE 0xA0000000
	32
	33	/* NAND boot config */
bcc05c7a	34	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	35	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800
	36	#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
	37	#define CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_MONITOR_LEN - 0x800
	38
	39	/*
	40	* BOOTP options
	41	*/
	42	#define CONFIG_BOOTP_SUBNETMASK
	43	#define CONFIG_BOOTP_GATEWAY
	44	#define CONFIG_BOOTP_HOSTNAME
	45	#define CONFIG_BOOTP_BOOTPATH
	46	#define CONFIG_BOOTP_BOOTFILESIZE
	47	#define CONFIG_BOOTP_DNS
	48	#define CONFIG_BOOTP_DNS2
	49
	50	#define CONFIG_HOSTNAME CONFIG_BOARD_NAME
	51	#define CONFIG_ROOTPATH "/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root"
	52
bcc05c7a	53	/*
	54	* Memory configurations
	55	*/
	56	#define CONFIG_NR_DRAM_POPULATED 1
	57	#define CONFIG_NR_DRAM_BANKS 2
	58
	59	#define ACFG_SDRAM_MBYTE_SYZE 64
	60
	61	#define PHYS_SDRAM_1 0xA0000000
	62	#define PHYS_SDRAM_2 0xB0000000
	63	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	64	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (512<<10))
	65	#define CONFIG_SYS_MEMTEST_START 0xA0000000 /* memtest test area */
	66	#define CONFIG_SYS_MEMTEST_END 0xA0300000 /* 3 MiB RAM test */
	67
	68	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE \
	69	+ PHYS_SDRAM_1_SIZE - 0x0100000)
	70
	71	#define CONFIG_SYS_TEXT_BASE 0xA0000800
	72
	73	/*
	74	* FLASH organization
	75	*/
	76	#define ACFG_MONITOR_OFFSET 0x00000000
	77	#define CONFIG_SYS_MONITOR_LEN 0x00100000 /* 1MiB */
bcc05c7a	78	#define CONFIG_ENV_OVERWRITE
	79	#define CONFIG_ENV_OFFSET 0x00100000 /* NAND offset */
	80	#define CONFIG_ENV_SIZE 0x00020000 /* 128kB */
	81	#define CONFIG_ENV_RANGE 0X00080000 /* 512kB */
	82	#define CONFIG_ENV_OFFSET_REDUND \
	83	(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) /* +512kB */
	84	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE /* 512kB */
	85	#define CONFIG_FIRMWARE_OFFSET 0x00200000
	86	#define CONFIG_FIRMWARE_SIZE 0x00080000 /* 512kB */
	87	#define CONFIG_KERNEL_OFFSET 0x00300000
	88	#define CONFIG_ROOTFS_OFFSET 0x00800000
	89
	90	#define CONFIG_MTDMAP "mxc_nand.0"
	91	#define MTDIDS_DEFAULT "nand0=" CONFIG_MTDMAP
	92	#define MTDPARTS_DEFAULT "mtdparts=" CONFIG_MTDMAP \
	93	":1M(u-boot)ro," \
	94	"512K(env)," \
	95	"512K(env2)," \
	96	"512K(firmware)," \
	97	"512K(dtb)," \
	98	"5M(kernel)," \
	99	"-(rootfs)"
	100
	101	/*
	102	* U-Boot general configurations
	103	*/
	104	#define CONFIG_SYS_LONGHELP
bcc05c7a	105	#define CONFIG_SYS_CBSIZE 2048 /* console I/O buffer */
bcc05c7a	106	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	107	/* Boot argument buffer size */
	108	#define CONFIG_AUTO_COMPLETE
	109	#define CONFIG_CMDLINE_EDITING
bcc05c7a	110	#define CONFIG_ENV_VARS_UBOOT_CONFIG
	111	#define CONFIG_PREBOOT "run check_flash check_env;"
	112
bcc05c7a	113	/*
	114	* Boot Linux
	115	*/
	116	#define CONFIG_CMDLINE_TAG /* send commandline to Kernel */
	117	#define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */
	118	#define CONFIG_INITRD_TAG /* send initrd params */
	119
bcc05c7a	120	#define CONFIG_BOOTFILE __stringify(CONFIG_BOARD_NAME) "-linux.bin"
bcc05c7a	121
	122	#define ACFG_CONSOLE_DEV ttySMX0
	123	#define CONFIG_BOOTCOMMAND "run ubifsboot"
	124	#define CONFIG_SYS_AUTOLOAD "no"
	125	/*
	126	* Default load address for user programs and kernel
	127	*/
	128	#define CONFIG_LOADADDR 0xA0000000
	129	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
	130
	131	/*
	132	* Extra Environments
	133	*/
	134	#define CONFIG_EXTRA_ENV_SETTINGS \
	135	"env_version=" __stringify(CONFIG_ENV_VERSION) "\0" \
	136	"consoledev=" __stringify(ACFG_CONSOLE_DEV) "\0" \
	137	"mtdparts=" MTDPARTS_DEFAULT "\0" \
	138	"partition=nand0,6\0" \
	139	"u-boot_addr=" __stringify(ACFG_MONITOR_OFFSET) "\0" \
	140	"env_addr=" __stringify(CONFIG_ENV_OFFSET) "\0" \
	141	"firmware_addr=" __stringify(CONFIG_FIRMWARE_OFFSET) "\0" \
	142	"firmware_size=" __stringify(CONFIG_FIRMWARE_SIZE) "\0" \
	143	"kernel_addr=" __stringify(CONFIG_KERNEL_OFFSET) "\0" \
	144	"rootfs_addr=" __stringify(CONFIG_ROOTFS_OFFSET) "\0" \
	145	"board_name=" __stringify(CONFIG_BOARD_NAME) "\0" \
	146	"kernel_addr_r=A0000000\0" \
	147	"check_env=if test -n ${flash_env_version}; " \
	148	"then env default env_version; " \
	149	"else env set flash_env_version ${env_version}; env save; "\
	150	"fi; " \
	151	"if itest ${flash_env_version} < ${env_version}; then " \
	152	"echo \"*** Warning - Environment version" \
	153	" change suggests: run flash_reset_env; reset\"; "\
	154	"env default flash_reset_env; "\
	155	"fi; \0" \
	156	"check_flash=nand lock; nand unlock ${env_addr}; \0" \
	157	"flash_reset_env=env default -f -a; saveenv; run update_env;" \
	158	"echo Flash environment variables erased!\0" \
	159	"download_uboot=tftpboot ${loadaddr} ${board_name}" \
	160	"-u-boot-with-spl.bin\0" \
	161	"flash_uboot=nand unlock ${u-boot_addr} ;" \
	162	"nand erase.part u-boot;" \
	163	"if nand write.trimffs ${fileaddr} ${u-boot_addr} ${filesize};"\
	164	"then nand lock; nand unlock ${env_addr};" \
	165	"echo Flashing of uboot succeed;" \
	166	"else echo Flashing of uboot failed;" \
	167	"fi; \0" \
	168	"update_uboot=run download_uboot flash_uboot\0" \
	169	"download_env=tftpboot ${loadaddr} ${board_name}" \
	170	"-u-boot-env.txt\0" \
	171	"flash_env=env import -t ${loadaddr}; env save; \0" \
	172	"update_env=run download_env flash_env\0" \
	173	"update_all=run update_env update_uboot\0" \
	174	"unlock_regs=mw 10000008 0; mw 10020008 0\0" \
	175
	176	/*
	177	* Serial Driver
	178	*/
	179	#define CONFIG_MXC_UART
	180	#define CONFIG_CONS_INDEX 1
bcc05c7a	181	#define CONFIG_MXC_UART_BASE UART1_BASE
	182
	183	/*
	184	* GPIO
	185	*/
	186	#define CONFIG_MXC_GPIO
	187
	188	/*
	189	* NOR
	190	*/
	191
	192	/*
	193	* NAND
	194	*/
	195	#define CONFIG_NAND_MXC
	196
	197	#define CONFIG_MXC_NAND_REGS_BASE 0xD8000000
	198	#define CONFIG_SYS_NAND_BASE CONFIG_MXC_NAND_REGS_BASE
	199	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	200
	201	#define CONFIG_MXC_NAND_HWECC
	202	#define CONFIG_SYS_NAND_LARGEPAGE
	203	#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
	204	#define CONFIG_SYS_NAND_PAGE_SIZE 2048
	205	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
	206	#define CONFIG_SYS_NAND_PAGE_COUNT CONFIG_SYS_NAND_BLOCK_SIZE / \
	207	CONFIG_SYS_NAND_PAGE_SIZE
	208	#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
	209	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 11
	210	#define NAND_MAX_CHIPS 1
	211
	212	#define CONFIG_FLASH_SHOW_PROGRESS 45
	213	#define CONFIG_SYS_NAND_QUIET 1
	214
	215	/*
	216	* Partitions & Filsystems
	217	*/
	218	#define CONFIG_MTD_DEVICE
	219	#define CONFIG_MTD_PARTITIONS
bcc05c7a	220	#define CONFIG_SUPPORT_VFAT
bcc05c7a	221
bcc05c7a	222	/*
	223	* Ethernet (on SOC imx FEC)
	224	*/
	225	#define CONFIG_FEC_MXC
	226	#define CONFIG_FEC_MXC_PHYADDR 0x1f
	227	#define CONFIG_MII /* MII PHY management */
	228
b5e7f1bc	229	/*
	230	* FPGA
	231	*/
	232	#ifndef CONFIG_SPL_BUILD
	233	#define CONFIG_FPGA
	234	#endif
	235	#define CONFIG_FPGA_COUNT 1
	236	#define CONFIG_FPGA_XILINX
	237	#define CONFIG_FPGA_SPARTAN3
	238	#define CONFIG_SYS_FPGA_WAIT 250 /* 250 ms */
	239	#define CONFIG_SYS_FPGA_PROG_FEEDBACK
	240	#define CONFIG_SYS_FPGA_CHECK_CTRLC
	241	#define CONFIG_SYS_FPGA_CHECK_ERROR
	242
bcc05c7a	243	/*
	244	* Fuses - IIM
	245	*/
	246	#ifdef CONFIG_CMD_IMX_FUSE
	247	#define IIM_MAC_BANK 0
	248	#define IIM_MAC_ROW 5
	249	#define IIM0_SCC_KEY 11
	250	#define IIM1_SUID 1
	251	#endif
	252
	253	/*
	254	* I2C
	255	*/
	256
	257	#ifdef CONFIG_CMD_I2C
b089d039	258	#define CONFIG_SYS_I2C
b089d039	259	#define CONFIG_SYS_I2C_MXC
03544c66 AA	260	#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
03544c66 AA	261	#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
b089d039	262	#define CONFIG_SYS_MXC_I2C1_SPEED 100000 /* 100 kHz */
	263	#define CONFIG_SYS_MXC_I2C1_SLAVE 0x7F
	264	#define CONFIG_SYS_MXC_I2C2_SPEED 100000 /* 100 kHz */
	265	#define CONFIG_SYS_MXC_I2C2_SLAVE 0x7F
bcc05c7a	266	#define CONFIG_SYS_I2C_NOPROBES { }
	267
	268	#ifdef CONFIG_CMD_EEPROM
	269	# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24LC02 */
	270	# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
	271	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	272	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* msec */
	273	#endif /* CONFIG_CMD_EEPROM */
	274	#endif /* CONFIG_CMD_I2C */
	275
	276	/*
	277	* SD/MMC
	278	*/
	279	#ifdef CONFIG_CMD_MMC
bcc05c7a	280	#define CONFIG_MXC_MCI_REGS_BASE 0x10014000
	281	#endif
	282
	283	/*
	284	* RTC
	285	*/
	286	#ifdef CONFIG_CMD_DATE
	287	#define CONFIG_RTC_DS1374
	288	#define CONFIG_SYS_RTC_BUS_NUM 0
	289	#endif /* CONFIG_CMD_DATE */
	290
bcc05c7a	291	/*
	292	* PLL
	293	*
	294	* 31 \| x \|x\| x x x x \|x x x x x x x x x x \|x x\|x x x x\|x x x x x x x x x x\| 0
	295	* \|CPLM\|X\|----PD---\|--------MFD---------\|XXX\|--MFI--\|-----MFN-----------\|
	296	*/
	297	#define CONFIG_MX27_CLK32 32768 /* 32768 or 32000 Hz crystal */
	298
	299	#if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
	300	/* micron 64MB */
	301	#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
	302	#define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */
	303	#endif
	304
	305	#if (ACFG_SDRAM_MBYTE_SYZE == 128)
	306	/* micron 128MB */
	307	#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
	308	#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */
	309	#endif
	310
	311	#if (ACFG_SDRAM_MBYTE_SYZE == 256)
	312	/* micron 256MB */
	313	#define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */
	314	#define PHYS_SDRAM_2_SIZE 0x10000000 /* 256 MB */
	315	#endif
	316
	317	#endif /* __CONFIG_H */