[people/ms/u-boot.git] / include / configs / at91sam9x5ek.h

/*
 * Copyright (C) 2012 Atmel Corporation
 *
 * Configuation settings for the AT91SAM9X5EK board.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H__
#define __CONFIG_H__

#include <asm/hardware.h>

#define CONFIG_SYS_TEXT_BASE		0x26f00000

/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK	32768
#define CONFIG_SYS_AT91_MAIN_CLOCK	12000000	/* 12 MHz crystal */

#define CONFIG_AT91SAM9X5EK

#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_SKIP_LOWLEVEL_INIT

/* general purpose I/O */
#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */

/* LCD */
#define LCD_BPP			LCD_COLOR16
#define LCD_OUTPUT_BPP		24
#define CONFIG_LCD_LOGO
#define CONFIG_LCD_INFO
#define CONFIG_LCD_INFO_BELOW_LOGO
#define CONFIG_ATMEL_HLCD
#define CONFIG_ATMEL_LCD_RGB565


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * define CONFIG_USB_EHCI_HCD to enable USB Hi-Speed (aka 2.0)
 * NB: in this case, USB 1.1 devices won't be recognized.
 */

/* SDRAM */
#define CONFIG_NR_DRAM_BANKS		1
#define CONFIG_SYS_SDRAM_BASE		0x20000000
#define CONFIG_SYS_SDRAM_SIZE		0x08000000	/* 128 megs */

#define CONFIG_SYS_INIT_SP_ADDR \
	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)

/* DataFlash */
#ifdef CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED		30000000
#endif

/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BASE		0x40000000
#define CONFIG_SYS_NAND_DBW_8		1
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PD4
#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PD5

#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#endif

/* PMECC & PMERRLOC */
#define CONFIG_ATMEL_NAND_HWECC		1
#define CONFIG_ATMEL_NAND_HW_PMECC	1
#define CONFIG_PMECC_CAP		2
#define CONFIG_PMECC_SECTOR_SIZE	512

/* USB */
#ifdef CONFIG_CMD_USB
#ifndef CONFIG_USB_EHCI_HCD
#define CONFIG_USB_ATMEL
#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_REGS_BASE		ATMEL_BASE_OHCI
#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9x5"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	3
#endif
#endif

#define CONFIG_SYS_LOAD_ADDR		0x22000000	/* load address */

#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END		0x26e00000

#ifdef CONFIG_SYS_USE_NANDFLASH
/* bootstrap + u-boot + env + linux in nandflash */
#define CONFIG_ENV_OFFSET		0x120000
#define CONFIG_ENV_OFFSET_REDUND	0x100000
#define CONFIG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
#define CONFIG_BOOTCOMMAND	"nand read " \
				"0x22000000 0x200000 0x300000; " \
				"bootm 0x22000000"
#elif defined(CONFIG_SYS_USE_SPIFLASH)
/* bootstrap + u-boot + env + linux in spi flash */
#define CONFIG_ENV_OFFSET	0x5000
#define CONFIG_ENV_SIZE		0x3000
#define CONFIG_ENV_SECT_SIZE	0x1000
#define CONFIG_ENV_SPI_MAX_HZ	30000000
#define CONFIG_BOOTCOMMAND	"sf probe 0; " \
				"sf read 0x22000000 0x100000 0x300000; " \
				"bootm 0x22000000"
#elif defined(CONFIG_SYS_USE_DATAFLASH)
/* bootstrap + u-boot + env + linux in data flash */
#define CONFIG_ENV_OFFSET	0x4200
#define CONFIG_ENV_SIZE		0x4200
#define CONFIG_ENV_SECT_SIZE	0x210
#define CONFIG_ENV_SPI_MAX_HZ	30000000
#define CONFIG_BOOTCOMMAND	"sf probe 0; " \
				"sf read 0x22000000 0x84000 0x294000; " \
				"bootm 0x22000000"
#else /* CONFIG_SYS_USE_MMC */
/* bootstrap + u-boot + env + linux in mmc */
#define CONFIG_ENV_SIZE		0x4000
#endif

#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(512 * 1024 + 0x1000)

/* SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE		0x300000
#define CONFIG_SPL_MAX_SIZE		0x6000
#define CONFIG_SPL_STACK		0x308000

#define CONFIG_SPL_BSS_START_ADDR	0x20000000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
#define CONFIG_SYS_SPL_MALLOC_START	0x20080000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000

#define CONFIG_SYS_MONITOR_LEN		(512 << 10)

#define CONFIG_SYS_MASTER_CLOCK		132096000
#define CONFIG_SYS_AT91_PLLA		0x20c73f03
#define CONFIG_SYS_MCKR			0x1301
#define CONFIG_SYS_MCKR_CSS		0x1302

#ifdef CONFIG_SYS_USE_MMC
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"

#elif CONFIG_SYS_USE_NANDFLASH
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE	0x800
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_BLOCK_SIZE	0x20000
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0x0
#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER

#elif CONFIG_SYS_USE_SPIFLASH
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x8400

#endif

#endif
Commit	Line	Data
f7fa2f37 BS	1	/*
	2	* Copyright (C) 2012 Atmel Corporation
	3	*
	4	* Configuation settings for the AT91SAM9X5EK board.
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
f7fa2f37 BS	7	*/
	8
	9	#ifndef __CONFIG_H__
	10	#define __CONFIG_H__
	11
	12	#include <asm/hardware.h>
	13
77461a65 BS	14	#define CONFIG_SYS_TEXT_BASE 0x26f00000
77461a65 BS	15
f7fa2f37 BS	16	/* ARM asynchronous clock */
	17	#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
	18	#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
f7fa2f37 BS	19
f7fa2f37 BS	20	#define CONFIG_AT91SAM9X5EK
f7fa2f37	21
f7fa2f37 BS	22	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	23	#define CONFIG_SETUP_MEMORY_TAGS
	24	#define CONFIG_INITRD_TAG
	25	#define CONFIG_SKIP_LOWLEVEL_INIT
f7fa2f37 BS	26
	27	/* general purpose I/O */
	28	#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
f7fa2f37 BS	29
f7fa2f37 BS	30	/* LCD */
f7fa2f37 BS	31	#define LCD_BPP LCD_COLOR16
	32	#define LCD_OUTPUT_BPP 24
	33	#define CONFIG_LCD_LOGO
f7fa2f37 BS	34	#define CONFIG_LCD_INFO
f7fa2f37 BS	35	#define CONFIG_LCD_INFO_BELOW_LOGO
f7fa2f37 BS	36	#define CONFIG_ATMEL_HLCD
f7fa2f37 BS	37	#define CONFIG_ATMEL_LCD_RGB565
f7fa2f37	38
f7fa2f37 BS	39
	40	/*
	41	* BOOTP options
	42	*/
	43	#define CONFIG_BOOTP_BOOTFILESIZE
	44	#define CONFIG_BOOTP_BOOTPATH
	45	#define CONFIG_BOOTP_GATEWAY
	46	#define CONFIG_BOOTP_HOSTNAME
	47
b030e731	48	/*
8850c5d5	49	* define CONFIG_USB_EHCI_HCD to enable USB Hi-Speed (aka 2.0)
b030e731 RG	50	* NB: in this case, USB 1.1 devices won't be recognized.
	51	*/
	52
f7fa2f37 BS	53	/* SDRAM */
	54	#define CONFIG_NR_DRAM_BANKS 1
	55	#define CONFIG_SYS_SDRAM_BASE 0x20000000
	56	#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */
	57
	58	#define CONFIG_SYS_INIT_SP_ADDR \
74631b69	59	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
f7fa2f37 BS	60
f7fa2f37 BS	61	/* DataFlash */
1d7442e6	62	#ifdef CONFIG_CMD_SF
1d7442e6	63	#define CONFIG_SF_DEFAULT_SPEED 30000000
f7fa2f37 BS	64	#endif
f7fa2f37 BS	65
f7fa2f37 BS	66	/* NAND flash */
	67	#ifdef CONFIG_CMD_NAND
	68	#define CONFIG_NAND_ATMEL
	69	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	70	#define CONFIG_SYS_NAND_BASE 0x40000000
	71	#define CONFIG_SYS_NAND_DBW_8 1
	72	/* our ALE is AD21 */
	73	#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
	74	/* our CLE is AD22 */
	75	#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
	76	#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
	77	#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
	78
8f1a80e9 TR	79	#define CONFIG_MTD_DEVICE
	80	#define CONFIG_MTD_PARTITIONS
	81	#endif
	82
df95321c WJ	83	/* PMECC & PMERRLOC */
	84	#define CONFIG_ATMEL_NAND_HWECC 1
	85	#define CONFIG_ATMEL_NAND_HW_PMECC 1
	86	#define CONFIG_PMECC_CAP 2
	87	#define CONFIG_PMECC_SECTOR_SIZE 512
df95321c	88
b030e731 RG	89	/* USB */
b030e731 RG	90	#ifdef CONFIG_CMD_USB
8850c5d5	91	#ifndef CONFIG_USB_EHCI_HCD
dcd2f1a0 BS	92	#define CONFIG_USB_ATMEL
dcd2f1a0 BS	93	#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
b030e731 RG	94	#define CONFIG_USB_OHCI_NEW
	95	#define CONFIG_SYS_USB_OHCI_CPU_INIT
	96	#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI
	97	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9x5"
	98	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
	99	#endif
b030e731 RG	100	#endif
b030e731 RG	101
f7fa2f37 BS	102	#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
	103
	104	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
	105	#define CONFIG_SYS_MEMTEST_END 0x26e00000
	106
	107	#ifdef CONFIG_SYS_USE_NANDFLASH
	108	/* bootstrap + u-boot + env + linux in nandflash */
74631b69	109	#define CONFIG_ENV_OFFSET 0x120000
f7fa2f37 BS	110	#define CONFIG_ENV_OFFSET_REDUND 0x100000
	111	#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
	112	#define CONFIG_BOOTCOMMAND "nand read " \
	113	"0x22000000 0x200000 0x300000; " \
	114	"bootm 0x22000000"
b7e3129e	115	#elif defined(CONFIG_SYS_USE_SPIFLASH)
1d7442e6	116	/* bootstrap + u-boot + env + linux in spi flash */
1d7442e6 BS	117	#define CONFIG_ENV_OFFSET 0x5000
	118	#define CONFIG_ENV_SIZE 0x3000
	119	#define CONFIG_ENV_SECT_SIZE 0x1000
	120	#define CONFIG_ENV_SPI_MAX_HZ 30000000
	121	#define CONFIG_BOOTCOMMAND "sf probe 0; " \
	122	"sf read 0x22000000 0x100000 0x300000; " \
	123	"bootm 0x22000000"
961ffc77 BS	124	#elif defined(CONFIG_SYS_USE_DATAFLASH)
961ffc77 BS	125	/* bootstrap + u-boot + env + linux in data flash */
961ffc77 BS	126	#define CONFIG_ENV_OFFSET 0x4200
	127	#define CONFIG_ENV_SIZE 0x4200
	128	#define CONFIG_ENV_SECT_SIZE 0x210
	129	#define CONFIG_ENV_SPI_MAX_HZ 30000000
	130	#define CONFIG_BOOTCOMMAND "sf probe 0; " \
	131	"sf read 0x22000000 0x84000 0x294000; " \
	132	"bootm 0x22000000"
b7e3129e WJ	133	#else /* CONFIG_SYS_USE_MMC */
b7e3129e WJ	134	/* bootstrap + u-boot + env + linux in mmc */
26961772	135	#define CONFIG_ENV_SIZE 0x4000
f7fa2f37 BS	136	#endif
f7fa2f37 BS	137
f7fa2f37 BS	138	#define CONFIG_SYS_LONGHELP
	139	#define CONFIG_CMDLINE_EDITING
	140	#define CONFIG_AUTO_COMPLETE
f7fa2f37 BS	141
	142	/*
	143	* Size of malloc() pool
	144	*/
	145	#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000)
	146
d85e8914 BS	147	/* SPL */
	148	#define CONFIG_SPL_FRAMEWORK
	149	#define CONFIG_SPL_TEXT_BASE 0x300000
	150	#define CONFIG_SPL_MAX_SIZE 0x6000
	151	#define CONFIG_SPL_STACK 0x308000
	152
	153	#define CONFIG_SPL_BSS_START_ADDR 0x20000000
	154	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
	155	#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
	156	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
	157
d85e8914 BS	158	#define CONFIG_SYS_MONITOR_LEN (512 << 10)
	159
	160	#define CONFIG_SYS_MASTER_CLOCK 132096000
	161	#define CONFIG_SYS_AT91_PLLA 0x20c73f03
	162	#define CONFIG_SYS_MCKR 0x1301
	163	#define CONFIG_SYS_MCKR_CSS 0x1302
	164
d85e8914	165	#ifdef CONFIG_SYS_USE_MMC
d85e8914 BS	166	#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
d85e8914 BS	167	#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
d85e8914 BS	168
d85e8914 BS	169	#elif CONFIG_SYS_USE_NANDFLASH
d85e8914 BS	170	#define CONFIG_SPL_NAND_DRIVERS
	171	#define CONFIG_SPL_NAND_BASE
	172	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
	173	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	174	#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
	175	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	176	#define CONFIG_SYS_NAND_OOBSIZE 64
	177	#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
	178	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
	179	#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
	180
	181	#elif CONFIG_SYS_USE_SPIFLASH
d85e8914 BS	182	#define CONFIG_SPL_SPI_LOAD
	183	#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400
	184
	185	#endif
	186
f7fa2f37	187	#endif