]> git.ipfire.org Git - people/ms/u-boot.git/blame - include/configs/atngw100.h
Move default y configs out of arch/board Kconfig
[people/ms/u-boot.git] / include / configs / atngw100.h
CommitLineData
6b443944
HS
1/*
2 * Copyright (C) 2006 Atmel Corporation
3 *
4 * Configuration settings for the AVR32 Network Gateway
5 *
1a459660 6 * SPDX-License-Identifier: GPL-2.0+
6b443944
HS
7 */
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
5d73bc7a 11#include <asm/arch/hardware.h>
a23e277c 12
b78431a4
AB
13#define CONFIG_AT32AP
14#define CONFIG_AT32AP7000
15#define CONFIG_ATNGW100
6b443944 16
fb1e3eb9
AB
17#define CONFIG_BOARD_EARLY_INIT_F
18#define CONFIG_BOARD_EARLY_INIT_R
19
6b443944
HS
20/*
21 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
22 * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
23 * and the PBA bus to run at 1/4 the PLL frequency.
24 */
b78431a4
AB
25#define CONFIG_PLL
26#define CONFIG_SYS_POWER_MANAGER
6d0f6bcf
JCPV
27#define CONFIG_SYS_OSC0_HZ 20000000
28#define CONFIG_SYS_PLL0_DIV 1
29#define CONFIG_SYS_PLL0_MUL 7
30#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
31#define CONFIG_SYS_CLKDIV_CPU 0
32#define CONFIG_SYS_CLKDIV_HSB 1
33#define CONFIG_SYS_CLKDIV_PBA 2
34#define CONFIG_SYS_CLKDIV_PBB 1
6b443944 35
1f36f73f
HS
36/* Reserve VM regions for SDRAM and NOR flash */
37#define CONFIG_SYS_NR_VM_REGIONS 2
38
6b443944
HS
39/*
40 * The PLLOPT register controls the PLL like this:
41 * icp = PLLOPT<2>
42 * ivco = PLLOPT<1:0>
43 *
44 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
45 */
6d0f6bcf 46#define CONFIG_SYS_PLL0_OPT 0x04
6b443944 47
f4278b71
AB
48#define CONFIG_USART_BASE ATMEL_BASE_USART1
49#define CONFIG_USART_ID 1
6b443944 50/* User serviceable stuff */
b78431a4 51#define CONFIG_DOS_PARTITION
6b443944 52
b78431a4
AB
53#define CONFIG_CMDLINE_TAG
54#define CONFIG_SETUP_MEMORY_TAGS
55#define CONFIG_INITRD_TAG
6b443944
HS
56
57#define CONFIG_STACKSIZE (2048)
58
59#define CONFIG_BAUDRATE 115200
60#define CONFIG_BOOTARGS \
61 "console=ttyS0 root=/dev/mtdblock1 rootfstype=jffs2"
62#define CONFIG_BOOTCOMMAND \
63 "fsload; bootm"
64
6b443944 65#define CONFIG_BOOTDELAY 1
6b443944
HS
66
67/*
68 * After booting the board for the first time, new ethernet addresses
69 * should be generated and assigned to the environment variables
70 * "ethaddr" and "eth1addr". This is normally done during production.
71 */
b78431a4 72#define CONFIG_OVERWRITE_ETHADDR_ONCE
6b443944
HS
73
74/*
75 * BOOTP/DHCP options
76 */
77#define CONFIG_BOOTP_SUBNETMASK
78#define CONFIG_BOOTP_GATEWAY
79
6b443944
HS
80/*
81 * Command line configuration.
82 */
83#include <config_cmd_default.h>
84
85#define CONFIG_CMD_ASKENV
86#define CONFIG_CMD_DHCP
87#define CONFIG_CMD_EXT2
88#define CONFIG_CMD_FAT
89#define CONFIG_CMD_JFFS2
90#define CONFIG_CMD_MMC
5f723a3b
HS
91#define CONFIG_CMD_SF
92#define CONFIG_CMD_SPI
55ac7a74 93
6b443944
HS
94#undef CONFIG_CMD_FPGA
95#undef CONFIG_CMD_SETGETDCR
74de7aef 96#undef CONFIG_CMD_SOURCE
55ac7a74 97#undef CONFIG_CMD_XIMG
6b443944 98
b78431a4
AB
99#define CONFIG_ATMEL_USART
100#define CONFIG_MACB
101#define CONFIG_PORTMUX_PIO
6d0f6bcf 102#define CONFIG_SYS_NR_PIOS 5
b78431a4
AB
103#define CONFIG_SYS_HSDRAMC
104#define CONFIG_MMC
72fa4679
SS
105#define CONFIG_GENERIC_ATMEL_MCI
106#define CONFIG_GENERIC_MMC
b78431a4 107#define CONFIG_ATMEL_SPI
5f723a3b 108
b78431a4 109#define CONFIG_SPI_FLASH_ATMEL
6b443944 110
6d0f6bcf
JCPV
111#define CONFIG_SYS_DCACHE_LINESZ 32
112#define CONFIG_SYS_ICACHE_LINESZ 32
6b443944
HS
113
114#define CONFIG_NR_DRAM_BANKS 1
115
b78431a4
AB
116#define CONFIG_SYS_FLASH_CFI
117#define CONFIG_FLASH_CFI_DRIVER
6b443944 118
6d0f6bcf
JCPV
119#define CONFIG_SYS_FLASH_BASE 0x00000000
120#define CONFIG_SYS_FLASH_SIZE 0x800000
121#define CONFIG_SYS_MAX_FLASH_BANKS 1
122#define CONFIG_SYS_MAX_FLASH_SECT 135
6b443944 123
6d0f6bcf 124#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
da484372 125#define CONFIG_SYS_TEXT_BASE 0x00000000
6b443944 126
6d0f6bcf
JCPV
127#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
128#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
129#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
6b443944 130
b78431a4 131#define CONFIG_ENV_IS_IN_FLASH
0e8d1586 132#define CONFIG_ENV_SIZE 65536
6d0f6bcf 133#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
6b443944 134
6d0f6bcf 135#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
6b443944 136
6d0f6bcf 137#define CONFIG_SYS_MALLOC_LEN (256*1024)
6b443944
HS
138
139/* Allow 4MB for the kernel run-time image */
6d0f6bcf
JCPV
140#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
141#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
6b443944
HS
142
143/* Other configuration settings that shouldn't have to change all that often */
6d0f6bcf
JCPV
144#define CONFIG_SYS_PROMPT "U-Boot> "
145#define CONFIG_SYS_CBSIZE 256
146#define CONFIG_SYS_MAXARGS 16
147#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
b78431a4 148#define CONFIG_SYS_LONGHELP
6b443944 149
6d0f6bcf
JCPV
150#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE
151#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000)
2bcacc2d 152
6d0f6bcf 153#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
6b443944
HS
154
155#endif /* __CONFIG_H */