[people/ms/u-boot.git] / include / configs / atstk1006.h

/*
 * Copyright (C) 2005-2006 Atmel Corporation
 *
 * Configuration settings for the ATSTK1002 CPU daughterboard
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
#ifndef __CONFIG_H
#define __CONFIG_H

#include <asm/arch/memory-map.h>

#define CONFIG_AVR32			1
#define CONFIG_AT32AP			1
#define CONFIG_AT32AP7000		1
#define CONFIG_ATSTK1006		1
#define CONFIG_ATSTK1000		1

#define CONFIG_ATSTK1000_EXT_FLASH	1

/*
 * Timer clock frequency. We're using the CPU-internal COUNT register
 * for this, so this is equivalent to the CPU core clock frequency
 */
#define CONFIG_SYS_HZ				1000

/*
 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
 * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
 * PLL frequency.
 * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
 */
#define CONFIG_PLL			1
#define CONFIG_SYS_POWER_MANAGER		1
#define CONFIG_SYS_OSC0_HZ			20000000
#define CONFIG_SYS_PLL0_DIV			1
#define CONFIG_SYS_PLL0_MUL			7
#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES	16
/*
 * Set the CPU running at:
 * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
 */
#define CONFIG_SYS_CLKDIV_CPU			0
/*
 * Set the HSB running at:
 * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
 */
#define CONFIG_SYS_CLKDIV_HSB			1
/*
 * Set the PBA running at:
 * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
 */
#define CONFIG_SYS_CLKDIV_PBA			2
/*
 * Set the PBB running at:
 * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
 */
#define CONFIG_SYS_CLKDIV_PBB			1

/*
 * The PLLOPT register controls the PLL like this:
 *   icp = PLLOPT<2>
 *   ivco = PLLOPT<1:0>
 *
 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
 */
#define CONFIG_SYS_PLL0_OPT			0x04

#undef CONFIG_USART0
#define CONFIG_USART1			1
#undef CONFIG_USART2
#undef CONFIG_USART3

/* User serviceable stuff */
#define CONFIG_DOS_PARTITION		1

#define CONFIG_CMDLINE_TAG		1
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_INITRD_TAG		1

#define CONFIG_STACKSIZE		(2048)

#define CONFIG_BAUDRATE			115200
#define CONFIG_BOOTARGS							\
	"console=ttyS0 root=mtd3 fbmem=2400k"

#define CONFIG_BOOTCOMMAND						\
	"fsload; bootm $(fileaddr)"

/*
 * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
 * data on the serial line may interrupt the boot sequence.
 */
#define CONFIG_BOOTDELAY		1
#define CONFIG_AUTOBOOT			1
#define CONFIG_AUTOBOOT_KEYED		1
#define CONFIG_AUTOBOOT_PROMPT		\
	"Press SPACE to abort autoboot in %d seconds\n", bootdelay
#define CONFIG_AUTOBOOT_DELAY_STR	"d"
#define CONFIG_AUTOBOOT_STOP_STR	" "

/*
 * After booting the board for the first time, new ethernet addresses
 * should be generated and assigned to the environment variables
 * "ethaddr" and "eth1addr". This is normally done during production.
 */
#define CONFIG_OVERWRITE_ETHADDR_ONCE	1
#define CONFIG_NET_MULTI		1

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MMC

#undef CONFIG_CMD_AUTOSCRIPT
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_SETGETDCR
#undef CONFIG_CMD_XIMG

#define CONFIG_ATMEL_USART		1
#define CONFIG_MACB			1
#define CONFIG_PIO2			1
#define CONFIG_SYS_NR_PIOS			5
#define CONFIG_SYS_HSDRAMC			1
#define CONFIG_MMC			1
#define CONFIG_ATMEL_MCI		1

#define CONFIG_SYS_DCACHE_LINESZ		32
#define CONFIG_SYS_ICACHE_LINESZ		32

#define CONFIG_NR_DRAM_BANKS		1

/* External flash on STK1000 */
#if 0
#define CONFIG_SYS_FLASH_CFI			1
#define CONFIG_FLASH_CFI_DRIVER		1
#endif

#define CONFIG_SYS_FLASH_BASE			0x00000000
#define CONFIG_SYS_FLASH_SIZE			0x800000
#define CONFIG_SYS_MAX_FLASH_BANKS		1
#define CONFIG_SYS_MAX_FLASH_SECT		135

#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE

#define CONFIG_SYS_INTRAM_BASE			INTERNAL_SRAM_BASE
#define CONFIG_SYS_INTRAM_SIZE			INTERNAL_SRAM_SIZE
#define CONFIG_SYS_SDRAM_BASE			EBI_SDRAM_BASE

#define CONFIG_ENV_IS_IN_FLASH		1
#define CONFIG_ENV_SIZE			65536
#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)

#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)

#define CONFIG_SYS_MALLOC_LEN			(256*1024)
#define CONFIG_SYS_DMA_ALLOC_LEN		(16384)

/* Allow 4MB for the kernel run-time image */
#define CONFIG_SYS_LOAD_ADDR			(EBI_SDRAM_BASE + 0x00400000)
#define CONFIG_SYS_BOOTPARAMS_LEN		(16 * 1024)

/* Other configuration settings that shouldn't have to change all that often */
#define CONFIG_SYS_PROMPT			"U-Boot> "
#define CONFIG_SYS_CBSIZE			256
#define CONFIG_SYS_MAXARGS			16
#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_LONGHELP			1

#define CONFIG_SYS_MEMTEST_START		EBI_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END			(CONFIG_SYS_MEMTEST_START + 0x3f00000)
#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }

#endif /* __CONFIG_H */
Commit	Line	Data
0a2e4879 HS	1	/*
	2	* Copyright (C) 2005-2006 Atmel Corporation
	3	*
	4	* Configuration settings for the ATSTK1002 CPU daughterboard
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24	#ifndef __CONFIG_H
	25	#define __CONFIG_H
	26
a23e277c HS	27	#include <asm/arch/memory-map.h>
a23e277c HS	28
0a2e4879 HS	29	#define CONFIG_AVR32 1
	30	#define CONFIG_AT32AP 1
	31	#define CONFIG_AT32AP7000 1
	32	#define CONFIG_ATSTK1006 1
	33	#define CONFIG_ATSTK1000 1
	34
	35	#define CONFIG_ATSTK1000_EXT_FLASH 1
	36
	37	/*
	38	* Timer clock frequency. We're using the CPU-internal COUNT register
	39	* for this, so this is equivalent to the CPU core clock frequency
	40	*/
6d0f6bcf	41	#define CONFIG_SYS_HZ 1000
0a2e4879 HS	42
	43	/*
	44	* Set up the PLL to run at 140 MHz, the CPU to run at the PLL
	45	* frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
	46	* PLL frequency.
6d0f6bcf	47	* (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
0a2e4879 HS	48	*/
0a2e4879 HS	49	#define CONFIG_PLL 1
6d0f6bcf JCPV	50	#define CONFIG_SYS_POWER_MANAGER 1
	51	#define CONFIG_SYS_OSC0_HZ 20000000
	52	#define CONFIG_SYS_PLL0_DIV 1
	53	#define CONFIG_SYS_PLL0_MUL 7
	54	#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
0a2e4879 HS	55	/*
0a2e4879 HS	56	* Set the CPU running at:
6d0f6bcf	57	* PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
0a2e4879	58	*/
6d0f6bcf	59	#define CONFIG_SYS_CLKDIV_CPU 0
0a2e4879 HS	60	/*
0a2e4879 HS	61	* Set the HSB running at:
6d0f6bcf	62	* PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
0a2e4879	63	*/
6d0f6bcf	64	#define CONFIG_SYS_CLKDIV_HSB 1
0a2e4879 HS	65	/*
0a2e4879 HS	66	* Set the PBA running at:
6d0f6bcf	67	* PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
0a2e4879	68	*/
6d0f6bcf	69	#define CONFIG_SYS_CLKDIV_PBA 2
0a2e4879 HS	70	/*
0a2e4879 HS	71	* Set the PBB running at:
6d0f6bcf	72	* PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
0a2e4879	73	*/
6d0f6bcf	74	#define CONFIG_SYS_CLKDIV_PBB 1
0a2e4879 HS	75
	76	/*
	77	* The PLLOPT register controls the PLL like this:
	78	* icp = PLLOPT<2>
	79	* ivco = PLLOPT<1:0>
	80	*
	81	* We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
	82	*/
6d0f6bcf	83	#define CONFIG_SYS_PLL0_OPT 0x04
0a2e4879 HS	84
	85	#undef CONFIG_USART0
	86	#define CONFIG_USART1 1
	87	#undef CONFIG_USART2
	88	#undef CONFIG_USART3
	89
	90	/* User serviceable stuff */
	91	#define CONFIG_DOS_PARTITION 1
	92
	93	#define CONFIG_CMDLINE_TAG 1
	94	#define CONFIG_SETUP_MEMORY_TAGS 1
	95	#define CONFIG_INITRD_TAG 1
	96
	97	#define CONFIG_STACKSIZE (2048)
	98
	99	#define CONFIG_BAUDRATE 115200
	100	#define CONFIG_BOOTARGS \
	101	"console=ttyS0 root=mtd3 fbmem=2400k"
	102
	103	#define CONFIG_BOOTCOMMAND \
	104	"fsload; bootm $(fileaddr)"
	105
	106	/*
	107	* Only interrupt autoboot if <space> is pressed. Otherwise, garbage
	108	* data on the serial line may interrupt the boot sequence.
	109	*/
	110	#define CONFIG_BOOTDELAY 1
	111	#define CONFIG_AUTOBOOT 1
	112	#define CONFIG_AUTOBOOT_KEYED 1
c37207d7 WD	113	#define CONFIG_AUTOBOOT_PROMPT \
c37207d7 WD	114	"Press SPACE to abort autoboot in %d seconds\n", bootdelay
0a2e4879 HS	115	#define CONFIG_AUTOBOOT_DELAY_STR "d"
	116	#define CONFIG_AUTOBOOT_STOP_STR " "
	117
	118	/*
	119	* After booting the board for the first time, new ethernet addresses
	120	* should be generated and assigned to the environment variables
	121	* "ethaddr" and "eth1addr". This is normally done during production.
	122	*/
	123	#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
	124	#define CONFIG_NET_MULTI 1
	125
	126	/*
	127	* BOOTP options
	128	*/
	129	#define CONFIG_BOOTP_SUBNETMASK
	130	#define CONFIG_BOOTP_GATEWAY
	131
	132
	133	/*
	134	* Command line configuration.
	135	*/
	136	#include <config_cmd_default.h>
	137
	138	#define CONFIG_CMD_ASKENV
	139	#define CONFIG_CMD_DHCP
	140	#define CONFIG_CMD_EXT2
	141	#define CONFIG_CMD_FAT
	142	#define CONFIG_CMD_JFFS2
	143	#define CONFIG_CMD_MMC
	144
	145	#undef CONFIG_CMD_AUTOSCRIPT
	146	#undef CONFIG_CMD_FPGA
	147	#undef CONFIG_CMD_SETGETDCR
	148	#undef CONFIG_CMD_XIMG
	149
	150	#define CONFIG_ATMEL_USART 1
	151	#define CONFIG_MACB 1
	152	#define CONFIG_PIO2 1
6d0f6bcf JCPV	153	#define CONFIG_SYS_NR_PIOS 5
6d0f6bcf JCPV	154	#define CONFIG_SYS_HSDRAMC 1
0a2e4879	155	#define CONFIG_MMC 1
d2d54ea4	156	#define CONFIG_ATMEL_MCI 1
0a2e4879	157
6d0f6bcf JCPV	158	#define CONFIG_SYS_DCACHE_LINESZ 32
6d0f6bcf JCPV	159	#define CONFIG_SYS_ICACHE_LINESZ 32
0a2e4879 HS	160
	161	#define CONFIG_NR_DRAM_BANKS 1
	162
	163	/* External flash on STK1000 */
	164	#if 0
6d0f6bcf	165	#define CONFIG_SYS_FLASH_CFI 1
00b1883a	166	#define CONFIG_FLASH_CFI_DRIVER 1
0a2e4879 HS	167	#endif
0a2e4879 HS	168
6d0f6bcf JCPV	169	#define CONFIG_SYS_FLASH_BASE 0x00000000
	170	#define CONFIG_SYS_FLASH_SIZE 0x800000
	171	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	172	#define CONFIG_SYS_MAX_FLASH_SECT 135
0a2e4879	173
6d0f6bcf	174	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
0a2e4879	175
6d0f6bcf JCPV	176	#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
	177	#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
	178	#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
0a2e4879	179
5a1aceb0	180	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586	181	#define CONFIG_ENV_SIZE 65536
6d0f6bcf	182	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
0a2e4879	183
6d0f6bcf	184	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
0a2e4879	185
6d0f6bcf JCPV	186	#define CONFIG_SYS_MALLOC_LEN (256*1024)
6d0f6bcf JCPV	187	#define CONFIG_SYS_DMA_ALLOC_LEN (16384)
0a2e4879 HS	188
0a2e4879 HS	189	/* Allow 4MB for the kernel run-time image */
6d0f6bcf JCPV	190	#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
6d0f6bcf JCPV	191	#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
0a2e4879 HS	192
0a2e4879 HS	193	/* Other configuration settings that shouldn't have to change all that often */
6d0f6bcf JCPV	194	#define CONFIG_SYS_PROMPT "U-Boot> "
	195	#define CONFIG_SYS_CBSIZE 256
	196	#define CONFIG_SYS_MAXARGS 16
	197	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	198	#define CONFIG_SYS_LONGHELP 1
	199
	200	#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE
	201	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x3f00000)
	202	#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
0a2e4879 HS	203
0a2e4879 HS	204	#endif /* __CONFIG_H */