[people/ms/u-boot.git] / include / configs / cm_t43.h

/*
 * cm_t43.h
 *
 * Copyright (C) 2015 Compulab, Ltd.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_CM_T43_H
#define __CONFIG_CM_T43_H

#define CONFIG_CM_T43
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_MAX_RAM_BANK_SIZE	(2048 << 20)	/* 2GB */
#define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */

#include <asm/arch/omap.h>

/* Serial support */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_CLK		48000000
#define CONFIG_SYS_NS16550_COM1		0x44e09000
#if !defined(CONFIG_SPL_DM) || !defined(CONFIG_DM_SERIAL)
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#endif

/* NAND support */
#define CONFIG_NAND_OMAP_ELM
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE	2048
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCSIZE		512
#define CONFIG_SYS_NAND_ECCBYTES	14
#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW
#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
					 CONFIG_SYS_NAND_PAGE_SIZE)
#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
					 10, 11, 12, 13, 14, 15, 16, 17, \
					 18, 19, 20, 21, 22, 23, 24, 25, \
					 26, 27, 28, 29, 30, 31, 32, 33, \
					 34, 35, 36, 37, 38, 39, 40, 41, \
					 42, 43, 44, 45, 46, 47, 48, 49, \
					 50, 51, 52, 53, 54, 55, 56, 57, }

/* CPSW Ethernet support */
#define CONFIG_DRIVER_TI_CPSW
#define CONFIG_MII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_NET_MULTI
#define CONFIG_PHY_ATHEROS
#define CONFIG_SYS_RX_ETH_BUFFER	64

/* USB support */
#define CONFIG_USB_XHCI_OMAP
#define CONFIG_OMAP_USB_PHY
#define CONFIG_AM437X_USB2PHY2_HOST

/* SPI Flash support */
#define CONFIG_TI_SPI_MMAP
#define CONFIG_SF_DEFAULT_SPEED		48000000
#define CONFIG_DEFAULT_SPI_MODE		SPI_MODE_3

/* Power */
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_TPS65218

/* Enabling L2 Cache */
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE		0x48242000

/*
 * Since SPL did pll and ddr initialization for us,
 * we don't need to do it twice.
 */
#if !defined(CONFIG_SPL_BUILD)
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif

#define CONFIG_HSMMC2_8BIT

#include <configs/ti_armv7_omap.h>
#undef CONFIG_SYS_MONITOR_LEN

#define CONFIG_ENV_SIZE			(16 * 1024)
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG

#define V_OSCK				24000000  /* Clock output from T2 */
#define V_SCLK				(V_OSCK)

#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
#define CONFIG_ENV_OFFSET		(768 * 1024)
#define CONFIG_ENV_SPI_MAX_HZ           48000000

#define CONFIG_EXTRA_ENV_SETTINGS \
	"loadaddr=0x80200000\0" \
	"fdtaddr=0x81200000\0" \
	"bootm_size=0x8000000\0" \
	"autoload=no\0" \
	"console=ttyO0,115200n8\0" \
	"fdtfile=am437x-sb-som-t43.dtb\0" \
	"kernel=zImage-cm-t43\0" \
	"bootscr=bootscr.img\0" \
	"emmcroot=/dev/mmcblk0p2 rw\0" \
	"emmcrootfstype=ext4 rootwait\0" \
	"emmcargs=setenv bootargs console=${console} " \
		"root=${emmcroot} " \
		"rootfstype=${emmcrootfstype}\0" \
	"loadbootscript=load mmc 0 ${loadaddr} ${bootscr}\0" \
	"bootscript=echo Running bootscript from mmc ...; " \
		"source ${loadaddr}\0" \
	"emmcboot=echo Booting from emmc ... && " \
		"run emmcargs && " \
		"load mmc 1 ${loadaddr} ${kernel} && " \
		"load mmc 1 ${fdtaddr} ${fdtfile} && " \
		"bootz ${loadaddr} - ${fdtaddr}\0"

#define CONFIG_BOOTCOMMAND \
	"mmc dev 0; " \
	"if mmc rescan; then " \
		"if run loadbootscript; then " \
			"run bootscript; " \
		"fi; " \
	"fi; " \
	"mmc dev 1; " \
	"if mmc rescan; then " \
		"run emmcboot; " \
	"fi;"

#define CONFIG_CONS_INDEX		1

/* SPL defines. */
#define CONFIG_SPL_TEXT_BASE		0x40300350
#define CONFIG_SYS_SPL_ARGS_ADDR	(CONFIG_SYS_SDRAM_BASE + (128 << 20))
#define CONFIG_SYS_SPI_U_BOOT_OFFS	(256 * 1024)
#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
#define CONFIG_SPL_SPI_LOAD

/* EEPROM */
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
#define CONFIG_SYS_EEPROM_SIZE			256

#endif	/* __CONFIG_CM_T43_H */
Commit	Line	Data
8883ddaf NK	1	/*
	2	* cm_t43.h
	3	*
	4	* Copyright (C) 2015 Compulab, Ltd.
	5	*
	6	* SPDX-License-Identifier: GPL-2.0+
	7	*/
	8
	9	#ifndef __CONFIG_CM_T43_H
	10	#define __CONFIG_CM_T43_H
	11
8883ddaf NK	12	#define CONFIG_CM_T43
	13	#define CONFIG_ARCH_CPU_INIT
	14	#define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2GB */
	15	#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
	16
	17	#include <asm/arch/omap.h>
	18
	19	/* Serial support */
8883ddaf NK	20	#define CONFIG_SYS_NS16550_SERIAL
	21	#define CONFIG_SYS_NS16550_CLK 48000000
	22	#define CONFIG_SYS_NS16550_COM1 0x44e09000
f2d78c1c	23	#if !defined(CONFIG_SPL_DM) \|\| !defined(CONFIG_DM_SERIAL)
7ef77c02 NK	24	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
7ef77c02 NK	25	#endif
8883ddaf NK	26
8883ddaf NK	27	/* NAND support */
8883ddaf NK	28	#define CONFIG_NAND_OMAP_ELM
	29	#define CONFIG_SYS_NAND_ONFI_DETECTION
	30	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	31	#define CONFIG_SYS_NAND_PAGE_SIZE 2048
	32	#define CONFIG_SYS_NAND_OOBSIZE 64
	33	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
	34	#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
	35	#define CONFIG_SYS_NAND_ECCSIZE 512
	36	#define CONFIG_SYS_NAND_ECCBYTES 14
	37	#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
	38	#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
	39	CONFIG_SYS_NAND_PAGE_SIZE)
	40	#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
	41	10, 11, 12, 13, 14, 15, 16, 17, \
	42	18, 19, 20, 21, 22, 23, 24, 25, \
	43	26, 27, 28, 29, 30, 31, 32, 33, \
	44	34, 35, 36, 37, 38, 39, 40, 41, \
	45	42, 43, 44, 45, 46, 47, 48, 49, \
	46	50, 51, 52, 53, 54, 55, 56, 57, }
	47
	48	/* CPSW Ethernet support */
	49	#define CONFIG_DRIVER_TI_CPSW
	50	#define CONFIG_MII
	51	#define CONFIG_BOOTP_DEFAULT
	52	#define CONFIG_BOOTP_SEND_HOSTNAME
	53	#define CONFIG_BOOTP_GATEWAY
	54	#define CONFIG_NET_MULTI
8883ddaf	55	#define CONFIG_PHY_ATHEROS
8883ddaf NK	56	#define CONFIG_SYS_RX_ETH_BUFFER 64
	57
	58	/* USB support */
8883ddaf	59	#define CONFIG_USB_XHCI_OMAP
8883ddaf NK	60	#define CONFIG_OMAP_USB_PHY
	61	#define CONFIG_AM437X_USB2PHY2_HOST
	62
	63	/* SPI Flash support */
8883ddaf	64	#define CONFIG_TI_SPI_MMAP
8883ddaf NK	65	#define CONFIG_SF_DEFAULT_SPEED 48000000
	66	#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3
	67
	68	/* Power */
	69	#define CONFIG_POWER
	70	#define CONFIG_POWER_I2C
	71	#define CONFIG_POWER_TPS65218
	72
	73	/* Enabling L2 Cache */
	74	#define CONFIG_SYS_L2_PL310
	75	#define CONFIG_SYS_PL310_BASE 0x48242000
8883ddaf NK	76
	77	/*
	78	* Since SPL did pll and ddr initialization for us,
	79	* we don't need to do it twice.
	80	*/
	81	#if !defined(CONFIG_SPL_BUILD)
	82	#define CONFIG_SKIP_LOWLEVEL_INIT
	83	#endif
	84
	85	#define CONFIG_HSMMC2_8BIT
	86
	87	#include <configs/ti_armv7_omap.h>
7d751d66	88	#undef CONFIG_SYS_MONITOR_LEN
8883ddaf NK	89
	90	#define CONFIG_ENV_SIZE (16 * 1024)
	91	#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	92
	93	#define V_OSCK 24000000 /* Clock output from T2 */
	94	#define V_SCLK (V_OSCK)
	95
8883ddaf NK	96	#define CONFIG_ENV_SECT_SIZE (64 * 1024)
	97	#define CONFIG_ENV_OFFSET (768 * 1024)
	98	#define CONFIG_ENV_SPI_MAX_HZ 48000000
	99
8883ddaf NK	100	#define CONFIG_EXTRA_ENV_SETTINGS \
	101	"loadaddr=0x80200000\0" \
	102	"fdtaddr=0x81200000\0" \
	103	"bootm_size=0x8000000\0" \
	104	"autoload=no\0" \
	105	"console=ttyO0,115200n8\0" \
	106	"fdtfile=am437x-sb-som-t43.dtb\0" \
	107	"kernel=zImage-cm-t43\0" \
	108	"bootscr=bootscr.img\0" \
	109	"emmcroot=/dev/mmcblk0p2 rw\0" \
	110	"emmcrootfstype=ext4 rootwait\0" \
	111	"emmcargs=setenv bootargs console=${console} " \
	112	"root=${emmcroot} " \
	113	"rootfstype=${emmcrootfstype}\0" \
	114	"loadbootscript=load mmc 0 ${loadaddr} ${bootscr}\0" \
	115	"bootscript=echo Running bootscript from mmc ...; " \
	116	"source ${loadaddr}\0" \
	117	"emmcboot=echo Booting from emmc ... && " \
	118	"run emmcargs && " \
	119	"load mmc 1 ${loadaddr} ${kernel} && " \
	120	"load mmc 1 ${fdtaddr} ${fdtfile} && " \
	121	"bootz ${loadaddr} - ${fdtaddr}\0"
	122
	123	#define CONFIG_BOOTCOMMAND \
	124	"mmc dev 0; " \
	125	"if mmc rescan; then " \
	126	"if run loadbootscript; then " \
	127	"run bootscript; " \
	128	"fi; " \
	129	"fi; " \
	130	"mmc dev 1; " \
	131	"if mmc rescan; then " \
	132	"run emmcboot; " \
	133	"fi;"
	134
8883ddaf NK	135	#define CONFIG_CONS_INDEX 1
	136
	137	/* SPL defines. */
	138	#define CONFIG_SPL_TEXT_BASE 0x40300350
8883ddaf	139	#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + (128 << 20))
8883ddaf	140	#define CONFIG_SYS_SPI_U_BOOT_OFFS (256 * 1024)
7d751d66	141	#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
8883ddaf NK	142	#define CONFIG_SPL_SPI_LOAD
8883ddaf NK	143
2d9a76b6	144	/* EEPROM */
2d9a76b6 NK	145	#define CONFIG_ENV_EEPROM_IS_ON_I2C
	146	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	147	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
	148	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
	149	#define CONFIG_SYS_EEPROM_SIZE 256
	150
8883ddaf	151	#endif /* __CONFIG_CM_T43_H */