[people/ms/u-boot.git] / include / configs / cogent_mpc8xx.h

/*
 * (C) Copyright 2000
 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * Config header file for Cogent platform using an MPC8xx CPU module
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC860		1	/* This is an MPC860 CPU	*/
#define CONFIG_COGENT		1	/* using Cogent Modular Architecture */

#define	CONFIG_MISC_INIT_F	1	/* Use misc_init_f()		*/

/* Cogent Modular Architecture options */
#define CONFIG_CMA286_60_OLD	1	/* ...on an old CMA286-60 CPU module */
#define CONFIG_CMA102		1	/* ...on a CMA102 motherboard	*/
#define CONFIG_CMA302		1	/* ...with a CMA302 flash I/O module */

/* serial console configuration */
#undef	CONFIG_8xx_CONS_SMC1
#undef	CONFIG_8xx_CONS_SMC2
#define CONFIG_8xx_CONS_NONE	/* not on 8xx serial ports (eg on cogent m/b) */

#if defined(CONFIG_CMA286_60_OLD)
#define CONFIG_8xx_GCLK_FREQ	33333000 /* define if cant use get_gclk_freq */
#endif

#define CONFIG_BAUDRATE		230400

#define CONFIG_HARD_I2C		/* I2C with hardware support */
#define CONFIG_SYS_I2C_SPEED		400000  /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE		0x7F


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_KGDB
#define CONFIG_CMD_I2C

#undef CONFIG_CMD_NET


#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif
#define CONFIG_BOOTCOMMAND	"bootm 04080000 04200000" /* autoboot command*/

#define CONFIG_BOOTARGS		"root=/dev/ram rw"

#if defined(CONFIG_CMD_KGDB)
#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
#undef	CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
#define	CONFIG_KGDB_NONE		/* define if kgdb on something else */
#define CONFIG_KGDB_INDEX	2	/* which SMC/SCC channel for kgdb */
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#endif

#define CONFIG_WATCHDOG			/* turn on platform specific watchdog */

/*
 * Miscellaneous configurable options
 */
#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x00400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x01c00000	/* 4 ... 28 MB in DRAM	*/

#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/

#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/

#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

#define CONFIG_SYS_ALLOC_DPRAM

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

/*-----------------------------------------------------------------------
 * Low Level Cogent settings
 * if CONFIG_SYS_CMA_CONS_SERIAL is defined, make sure the 8xx CPM serial is not.
 * also, make sure CONFIG_CONS_INDEX is still defined - the index will be
 * 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B
 * (second 2 for CMA120 only)
 */
#define CONFIG_SYS_CMA_MB_BASE		0x00000000	/* base of m/b address space */

#include <configs/cogent_common.h>

#define CONFIG_SYS_CMA_CONS_SERIAL	/* use Cogent motherboard serial for console */
#define CONFIG_CONS_INDEX	1
#define CONFIG_SYS_CMA_LCD_HEARTBEAT	/* define for sec rotator in lcd corner */
#define CONFIG_SHOW_ACTIVITY
#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
/*
 * flash exists on the motherboard
 * set these four according to TOP dipsw:
 * TOP on  => ..._FLLOW_...	(boot EPROM space is high so FLASH is low )
 * TOP off => ..._FLHIGH_...	(boot EPROM space is low  so FLASH is high)
 */
#define CMA_MB_FLASH_EXEC_BASE	CMA_MB_FLLOW_EXEC_BASE
#define CMA_MB_FLASH_EXEC_SIZE	CMA_MB_FLLOW_EXEC_SIZE
#define CMA_MB_FLASH_RDWR_BASE	CMA_MB_FLLOW_RDWR_BASE
#define CMA_MB_FLASH_RDWR_SIZE	CMA_MB_FLLOW_RDWR_SIZE
#endif
#define CMA_MB_FLASH_BASE	CMA_MB_FLASH_EXEC_BASE
#define CMA_MB_FLASH_SIZE	CMA_MB_FLASH_EXEC_SIZE

/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xFF000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define	CONFIG_SYS_SDRAM_BASE		CMA_MB_RAM_BASE
#ifdef CONFIG_CMA302
#define CONFIG_SYS_FLASH_BASE		CMA_MB_SLOT2_BASE	/* cma302 in slot 2 */
#else
#define CONFIG_SYS_FLASH_BASE		CMA_MB_FLASH_BASE	/* flash on m/b */
#endif
#define	CONFIG_SYS_MONITOR_BASE	TEXT_BASE
#define	CONFIG_SYS_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define	CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		CONFIG_SYS_FLASH_BASE /* Addr of Environment Sector */
#ifdef CONFIG_CMA302
#define	CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/
#define CONFIG_ENV_SECT_SIZE	(512*1024) /* see README - env sect real size */
#else
#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
#endif
/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif


/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif	/* CONFIG_WATCHDOG */

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit - leave PLL multiplication factor unchanged !
 */
#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
#define CONFIG_SYS_SCCR	(SCCR_TBS     | SCCR_RTDIV    | SCCR_RTSEL    | \
			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
			 SCCR_DFALCD00)

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
/*#define	CONFIG_SYS_DER	0x2002000F*/
#define CONFIG_SYS_DER	0

#if defined(CONFIG_CMA286_60_OLD)

/*
 * Init Memory Controller:
 *
 * NOTE: although the names (CONFIG_SYS_xRn_PRELIM) suggest preliminary settings,
 * they are actually the final settings for this cpu/board, because the
 * flash and RAM are on the motherboard, accessed via the CMAbus, and the
 * mappings are pretty much fixed.
 *
 * (the *_SIZE vars must be a power of 2)
 */

#define CONFIG_SYS_CMA_CS0_BASE	TEXT_BASE		/* EPROM */
#define CONFIG_SYS_CMA_CS0_SIZE	(1 << 20)
#define CONFIG_SYS_CMA_CS1_BASE	CMA_MB_RAM_BASE		/* RAM + I/O SLOT 1 */
#define CONFIG_SYS_CMA_CS1_SIZE	(64 << 20)
#define CONFIG_SYS_CMA_CS2_BASE	CMA_MB_SLOT2_BASE	/* I/O SLOTS 2 + 3 */
#define CONFIG_SYS_CMA_CS2_SIZE	(64 << 20)
#define CONFIG_SYS_CMA_CS3_BASE	CMA_MB_ROMLOW_BASE	/* M/B I/O */
#define CONFIG_SYS_CMA_CS3_SIZE	(32 << 20)

/*
 * CS0 maps the EPROM on the cpu module
 * Set it for 4 wait states, address CONFIG_SYS_MONITOR_BASE and size 1M
 *
 * Note: We must have already transferred control to the final location
 * of the EPROM before these are used, because when BR0/OR0 are set, the
 * mirror of the eprom at any other addresses will disappear.
 */

/* base address = CONFIG_SYS_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm */
#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_CMA_CS0_BASE&BR_BA_MSK)|BR_PS_16|BR_WP|BR_V)
/* mask size CONFIG_SYS_CMA_CS0_SIZE, CS time normal, burst inhibit, 4-wait states */
#define CONFIG_SYS_OR0_PRELIM	((~(CONFIG_SYS_CMA_CS0_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SCY_4_CLK)

/*
 * CS1 maps motherboard DRAM and motherboard I/O slot 1
 * (each 32Mbyte in size)
 */

/* base address = CONFIG_SYS_CMA_CS1_BASE, 32-bit, no parity, r/w, gpcm */
#define CONFIG_SYS_BR1_PRELIM	((CONFIG_SYS_CMA_CS1_BASE&BR_BA_MSK)|BR_V)
/* mask size CONFIG_SYS_CMA_CS1_SIZE, CS time normal, burst ok, ext xfer ack */
#define CONFIG_SYS_OR1_PRELIM	((~(CONFIG_SYS_CMA_CS1_SIZE-1)&OR_AM_MSK)|OR_SETA)

/*
 * CS2 maps motherboard I/O slots 2 and 3
 * (each 32Mbyte in size)
 */

/* base address = CONFIG_SYS_CMA_CS2_BASE, 32-bit, no parity, r/w, gpcm */
#define CONFIG_SYS_BR2_PRELIM	((CONFIG_SYS_CMA_CS2_BASE&BR_BA_MSK)|BR_V)
/* mask size CONFIG_SYS_CMA_CS2_SIZE, CS time normal, burst ok, ext xfer ack */
#define CONFIG_SYS_OR2_PRELIM	((~(CONFIG_SYS_CMA_CS2_SIZE-1)&OR_AM_MSK)|OR_SETA)

/*
 * CS3 maps motherboard I/O
 * (32Mbyte in size)
 */

/* base address = CONFIG_SYS_CMA_CS3_BASE, 32-bit, no parity, r/w, gpcm */
#define CONFIG_SYS_BR3_PRELIM	((CONFIG_SYS_CMA_CS3_BASE&BR_BA_MSK)|BR_V)
/* mask size CONFIG_SYS_CMA_CS3_SIZE, CS time normal, burst inhibit, ext xfer ack */
#define CONFIG_SYS_OR3_PRELIM	((~(CONFIG_SYS_CMA_CS3_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SETA)

#endif

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#endif	/* __CONFIG_H */
Commit	Line	Data
0f8c9768 WD	1	/*
	2	* (C) Copyright 2000
	3	* Murray Jensen <Murray.Jensen@cmst.csiro.au>
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* Config header file for Cogent platform using an MPC8xx CPU module
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
	36	#define CONFIG_MPC860 1 /* This is an MPC860 CPU */
	37	#define CONFIG_COGENT 1 /* using Cogent Modular Architecture */
	38
c837dcb1 WD	39	#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
c837dcb1 WD	40
0f8c9768 WD	41	/* Cogent Modular Architecture options */
	42	#define CONFIG_CMA286_60_OLD 1 /* ...on an old CMA286-60 CPU module */
	43	#define CONFIG_CMA102 1 /* ...on a CMA102 motherboard */
	44	#define CONFIG_CMA302 1 /* ...with a CMA302 flash I/O module */
	45
	46	/* serial console configuration */
	47	#undef CONFIG_8xx_CONS_SMC1
	48	#undef CONFIG_8xx_CONS_SMC2
	49	#define CONFIG_8xx_CONS_NONE /* not on 8xx serial ports (eg on cogent m/b) */
	50
	51	#if defined(CONFIG_CMA286_60_OLD)
	52	#define CONFIG_8xx_GCLK_FREQ 33333000 /* define if cant use get_gclk_freq */
	53	#endif
	54
	55	#define CONFIG_BAUDRATE 230400
	56
	57	#define CONFIG_HARD_I2C /* I2C with hardware support */
6d0f6bcf JCPV	58	#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
6d0f6bcf JCPV	59	#define CONFIG_SYS_I2C_SLAVE 0x7F
0f8c9768 WD	60
0f8c9768 WD	61
80ff4f99 JL	62	/*
	63	* BOOTP options
	64	*/
	65	#define CONFIG_BOOTP_BOOTFILESIZE
	66	#define CONFIG_BOOTP_BOOTPATH
	67	#define CONFIG_BOOTP_GATEWAY
	68	#define CONFIG_BOOTP_HOSTNAME
	69
	70
37e4f24b JL	71	/*
	72	* Command line configuration.
	73	*/
	74	#include <config_cmd_default.h>
	75
	76	#define CONFIG_CMD_KGDB
	77	#define CONFIG_CMD_I2C
	78
	79	#undef CONFIG_CMD_NET
0f8c9768	80
0f8c9768 WD	81
	82	#if 0
	83	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	84	#else
	85	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	86	#endif
	87	#define CONFIG_BOOTCOMMAND "bootm 04080000 04200000" /* autoboot command*/
	88
	89	#define CONFIG_BOOTARGS "root=/dev/ram rw"
	90
37e4f24b	91	#if defined(CONFIG_CMD_KGDB)
0f8c9768 WD	92	#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
	93	#undef CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
	94	#define CONFIG_KGDB_NONE /* define if kgdb on something else */
	95	#define CONFIG_KGDB_INDEX 2 /* which SMC/SCC channel for kgdb */
	96	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	97	#endif
	98
	99	#define CONFIG_WATCHDOG /* turn on platform specific watchdog */
	100
	101	/*
	102	* Miscellaneous configurable options
	103	*/
6d0f6bcf JCPV	104	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	105	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
37e4f24b	106	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	107	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
0f8c9768	108	#else
6d0f6bcf	109	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
0f8c9768	110	#endif
6d0f6bcf JCPV	111	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	112	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	113	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
0f8c9768	114
6d0f6bcf JCPV	115	#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
6d0f6bcf JCPV	116	#define CONFIG_SYS_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */
0f8c9768	117
6d0f6bcf	118	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
0f8c9768	119
6d0f6bcf	120	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
0f8c9768	121
6d0f6bcf	122	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
0f8c9768	123
6d0f6bcf	124	#define CONFIG_SYS_ALLOC_DPRAM
0f8c9768 WD	125
	126	/*
	127	* Low Level Configuration Settings
	128	* (address mappings, register initial values, etc.)
	129	* You should know what you are doing if you make changes here.
	130	*/
	131
	132	/*-----------------------------------------------------------------------
	133	* Low Level Cogent settings
6d0f6bcf	134	* if CONFIG_SYS_CMA_CONS_SERIAL is defined, make sure the 8xx CPM serial is not.
0f8c9768 WD	135	* also, make sure CONFIG_CONS_INDEX is still defined - the index will be
	136	* 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B
	137	* (second 2 for CMA120 only)
	138	*/
6d0f6bcf	139	#define CONFIG_SYS_CMA_MB_BASE 0x00000000 /* base of m/b address space */
0f8c9768 WD	140
	141	#include <configs/cogent_common.h>
	142
6d0f6bcf	143	#define CONFIG_SYS_CMA_CONS_SERIAL /* use Cogent motherboard serial for console */
0f8c9768	144	#define CONFIG_CONS_INDEX 1
6d0f6bcf	145	#define CONFIG_SYS_CMA_LCD_HEARTBEAT /* define for sec rotator in lcd corner */
a8c7c708	146	#define CONFIG_SHOW_ACTIVITY
0f8c9768 WD	147	#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
	148	/*
	149	* flash exists on the motherboard
	150	* set these four according to TOP dipsw:
	151	* TOP on => ..._FLLOW_... (boot EPROM space is high so FLASH is low )
	152	* TOP off => ..._FLHIGH_... (boot EPROM space is low so FLASH is high)
	153	*/
	154	#define CMA_MB_FLASH_EXEC_BASE CMA_MB_FLLOW_EXEC_BASE
	155	#define CMA_MB_FLASH_EXEC_SIZE CMA_MB_FLLOW_EXEC_SIZE
	156	#define CMA_MB_FLASH_RDWR_BASE CMA_MB_FLLOW_RDWR_BASE
	157	#define CMA_MB_FLASH_RDWR_SIZE CMA_MB_FLLOW_RDWR_SIZE
	158	#endif
	159	#define CMA_MB_FLASH_BASE CMA_MB_FLASH_EXEC_BASE
	160	#define CMA_MB_FLASH_SIZE CMA_MB_FLASH_EXEC_SIZE
	161
	162	/*-----------------------------------------------------------------------
	163	* Internal Memory Mapped Register
	164	*/
6d0f6bcf	165	#define CONFIG_SYS_IMMR 0xFF000000
0f8c9768 WD	166
	167	/*-----------------------------------------------------------------------
	168	* Definitions for initial stack pointer and data area (in DPRAM)
	169	*/
6d0f6bcf JCPV	170	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
	171	#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
	172	#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
	173	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	174	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
0f8c9768 WD	175
	176	/*-----------------------------------------------------------------------
	177	* Start addresses for the final memory configuration
	178	* (Set up by the startup code)
6d0f6bcf	179	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
0f8c9768	180	*/
6d0f6bcf	181	#define CONFIG_SYS_SDRAM_BASE CMA_MB_RAM_BASE
0f8c9768	182	#ifdef CONFIG_CMA302
6d0f6bcf	183	#define CONFIG_SYS_FLASH_BASE CMA_MB_SLOT2_BASE /* cma302 in slot 2 */
0f8c9768	184	#else
6d0f6bcf	185	#define CONFIG_SYS_FLASH_BASE CMA_MB_FLASH_BASE /* flash on m/b */
0f8c9768	186	#endif
6d0f6bcf JCPV	187	#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
	188	#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
	189	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
0f8c9768 WD	190
	191	/*
	192	* For booting Linux, the board info and command line data
	193	* have to be in the first 8 MB of memory, since this is
	194	* the maximum mapped by the Linux kernel during initialization.
	195	*/
6d0f6bcf	196	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
0f8c9768 WD	197	/*-----------------------------------------------------------------------
	198	* FLASH organization
	199	*/
6d0f6bcf JCPV	200	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
6d0f6bcf JCPV	201	#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
0f8c9768	202
6d0f6bcf JCPV	203	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	204	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
0f8c9768	205
5a1aceb0	206	#define CONFIG_ENV_IS_IN_FLASH 1
6d0f6bcf	207	#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE /* Addr of Environment Sector */
0f8c9768	208	#ifdef CONFIG_CMA302
0e8d1586 JCPV	209	#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
0e8d1586 JCPV	210	#define CONFIG_ENV_SECT_SIZE (5121024) / see README - env sect real size */
0f8c9768	211	#else
0e8d1586	212	#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
0f8c9768 WD	213	#endif
	214	/*-----------------------------------------------------------------------
	215	* Cache Configuration
	216	*/
6d0f6bcf	217	#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
37e4f24b	218	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	219	#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
0f8c9768 WD	220	#endif
	221
	222
	223	/*-----------------------------------------------------------------------
	224	* SYPCR - System Protection Control 11-9
	225	* SYPCR can only be written once after reset!
	226	*-----------------------------------------------------------------------
	227	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	228	*/
	229	#if defined(CONFIG_WATCHDOG)
6d0f6bcf	230	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
0f8c9768 WD	231	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
0f8c9768 WD	232	#else
6d0f6bcf	233	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
0f8c9768 WD	234	#endif /* CONFIG_WATCHDOG */
	235
	236	/*-----------------------------------------------------------------------
	237	* SIUMCR - SIU Module Configuration 11-6
	238	*-----------------------------------------------------------------------
	239	* PCMCIA config., multi-function pin tri-state
	240	*/
6d0f6bcf	241	#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01)
0f8c9768 WD	242
	243	/*-----------------------------------------------------------------------
	244	* TBSCR - Time Base Status and Control 11-26
	245	*-----------------------------------------------------------------------
	246	* Clear Reference Interrupt Status, Timebase freezing enabled
	247	*/
6d0f6bcf	248	#define CONFIG_SYS_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
0f8c9768 WD	249
	250	/*-----------------------------------------------------------------------
	251	* PISCR - Periodic Interrupt Status and Control 11-31
	252	*-----------------------------------------------------------------------
	253	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	254	*/
6d0f6bcf	255	#define CONFIG_SYS_PISCR (PISCR_PS \| PISCR_PITF)
0f8c9768 WD	256
	257	/*-----------------------------------------------------------------------
	258	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	259	*-----------------------------------------------------------------------
	260	* Reset PLL lock status sticky bit, timer expired status bit and timer
	261	* interrupt status bit - leave PLL multiplication factor unchanged !
	262	*/
6d0f6bcf	263	#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS \| PLPRCR_TEXPS \| PLPRCR_TMIST)
0f8c9768 WD	264
	265	/*-----------------------------------------------------------------------
	266	* SCCR - System Clock and reset Control Register 15-27
	267	*-----------------------------------------------------------------------
	268	* Set clock output, timebase and RTC source and divider,
	269	* power management and some other internal clocks
	270	*/
	271	#define SCCR_MASK SCCR_EBDF11
6d0f6bcf	272	#define CONFIG_SYS_SCCR (SCCR_TBS \| SCCR_RTDIV \| SCCR_RTSEL \| \
0f8c9768 WD	273	SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
	274	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
	275	SCCR_DFALCD00)
	276
	277	/*-----------------------------------------------------------------------
	278	* PCMCIA stuff
	279	*-----------------------------------------------------------------------
	280	*
	281	*/
6d0f6bcf JCPV	282	#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
	283	#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
	284	#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
	285	#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
	286	#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
	287	#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
	288	#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
	289	#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
0f8c9768 WD	290
	291	/*-----------------------------------------------------------------------
	292	*
	293	*-----------------------------------------------------------------------
	294	*
	295	*/
6d0f6bcf JCPV	296	/#define CONFIG_SYS_DER 0x2002000F/
6d0f6bcf JCPV	297	#define CONFIG_SYS_DER 0
0f8c9768 WD	298
	299	#if defined(CONFIG_CMA286_60_OLD)
	300
	301	/*
	302	* Init Memory Controller:
	303	*
6d0f6bcf	304	* NOTE: although the names (CONFIG_SYS_xRn_PRELIM) suggest preliminary settings,
0f8c9768 WD	305	* they are actually the final settings for this cpu/board, because the
	306	* flash and RAM are on the motherboard, accessed via the CMAbus, and the
	307	* mappings are pretty much fixed.
	308	*
	309	* (the *_SIZE vars must be a power of 2)
	310	*/
	311
6d0f6bcf JCPV	312	#define CONFIG_SYS_CMA_CS0_BASE TEXT_BASE /* EPROM */
	313	#define CONFIG_SYS_CMA_CS0_SIZE (1 << 20)
	314	#define CONFIG_SYS_CMA_CS1_BASE CMA_MB_RAM_BASE /* RAM + I/O SLOT 1 */
	315	#define CONFIG_SYS_CMA_CS1_SIZE (64 << 20)
	316	#define CONFIG_SYS_CMA_CS2_BASE CMA_MB_SLOT2_BASE /* I/O SLOTS 2 + 3 */
	317	#define CONFIG_SYS_CMA_CS2_SIZE (64 << 20)
	318	#define CONFIG_SYS_CMA_CS3_BASE CMA_MB_ROMLOW_BASE /* M/B I/O */
	319	#define CONFIG_SYS_CMA_CS3_SIZE (32 << 20)
0f8c9768 WD	320
	321	/*
	322	* CS0 maps the EPROM on the cpu module
6d0f6bcf	323	* Set it for 4 wait states, address CONFIG_SYS_MONITOR_BASE and size 1M
0f8c9768 WD	324	*
	325	* Note: We must have already transferred control to the final location
	326	* of the EPROM before these are used, because when BR0/OR0 are set, the
	327	* mirror of the eprom at any other addresses will disappear.
	328	*/
	329
6d0f6bcf JCPV	330	/* base address = CONFIG_SYS_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm */
	331	#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_CMA_CS0_BASE&BR_BA_MSK)\|BR_PS_16\|BR_WP\|BR_V)
	332	/* mask size CONFIG_SYS_CMA_CS0_SIZE, CS time normal, burst inhibit, 4-wait states */
	333	#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_CMA_CS0_SIZE-1)&OR_AM_MSK)\|OR_BI\|OR_SCY_4_CLK)
0f8c9768 WD	334
	335	/*
	336	* CS1 maps motherboard DRAM and motherboard I/O slot 1
	337	* (each 32Mbyte in size)
	338	*/
	339
6d0f6bcf JCPV	340	/* base address = CONFIG_SYS_CMA_CS1_BASE, 32-bit, no parity, r/w, gpcm */
	341	#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_CMA_CS1_BASE&BR_BA_MSK)\|BR_V)
	342	/* mask size CONFIG_SYS_CMA_CS1_SIZE, CS time normal, burst ok, ext xfer ack */
	343	#define CONFIG_SYS_OR1_PRELIM ((~(CONFIG_SYS_CMA_CS1_SIZE-1)&OR_AM_MSK)\|OR_SETA)
0f8c9768 WD	344
	345	/*
	346	* CS2 maps motherboard I/O slots 2 and 3
	347	* (each 32Mbyte in size)
	348	*/
	349
6d0f6bcf JCPV	350	/* base address = CONFIG_SYS_CMA_CS2_BASE, 32-bit, no parity, r/w, gpcm */
	351	#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_CMA_CS2_BASE&BR_BA_MSK)\|BR_V)
	352	/* mask size CONFIG_SYS_CMA_CS2_SIZE, CS time normal, burst ok, ext xfer ack */
	353	#define CONFIG_SYS_OR2_PRELIM ((~(CONFIG_SYS_CMA_CS2_SIZE-1)&OR_AM_MSK)\|OR_SETA)
0f8c9768 WD	354
	355	/*
	356	* CS3 maps motherboard I/O
	357	* (32Mbyte in size)
	358	*/
	359
6d0f6bcf JCPV	360	/* base address = CONFIG_SYS_CMA_CS3_BASE, 32-bit, no parity, r/w, gpcm */
	361	#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_CMA_CS3_BASE&BR_BA_MSK)\|BR_V)
	362	/* mask size CONFIG_SYS_CMA_CS3_SIZE, CS time normal, burst inhibit, ext xfer ack */
	363	#define CONFIG_SYS_OR3_PRELIM ((~(CONFIG_SYS_CMA_CS3_SIZE-1)&OR_AM_MSK)\|OR_BI\|OR_SETA)
0f8c9768 WD	364
	365	#endif
	366
	367	/*
	368	* Internal Definitions
	369	*
	370	* Boot Flags
	371	*/
	372	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	373	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	374
	375	#endif /* __CONFIG_H */