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1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net | |
4 | * | |
5 | * (C) Copyright 2002 | |
6 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
7 | * Marius Groeger <mgroeger@sysgo.de> | |
8 | * | |
9 | * See file CREDITS for list of people who contributed to this | |
10 | * project. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of | |
15 | * the License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
25 | * MA 02111-1307 USA | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /* | |
32 | * If we are developing, we might want to start armboot from ram | |
33 | * so we MUST NOT initialize critical regs like mem-timing ... | |
34 | */ | |
400558b5 | 35 | #define CONFIG_INIT_CRITICAL |
d9fd6ff5 WD |
36 | |
37 | /* | |
38 | * High Level Configuration Options | |
39 | * (easy to change) | |
40 | */ | |
41 | #define CONFIG_PXA250 1 /* This is an PXA250 CPU */ | |
42 | #define CONFIG_HHP_CRADLE 1 /* on an Cradle Board */ | |
43 | ||
44 | #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ | |
45 | ||
46 | /* | |
47 | * Size of malloc() pool | |
48 | */ | |
699b13a6 | 49 | #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) |
a8c7c708 | 50 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
d9fd6ff5 WD |
51 | |
52 | /* | |
53 | * Hardware drivers | |
54 | */ | |
55 | #define CONFIG_DRIVER_SMC91111 | |
56 | #define CONFIG_SMC91111_BASE 0x10000300 | |
57 | #define CONFIG_SMC91111_EXT_PHY | |
58 | #define CONFIG_SMC_USE_32_BIT | |
59 | ||
60 | /* | |
61 | * select serial console configuration | |
62 | */ | |
63 | #define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */ | |
64 | ||
65 | /* allow to overwrite serial and ethaddr */ | |
66 | #define CONFIG_ENV_OVERWRITE | |
67 | ||
68 | #define CONFIG_BAUDRATE 115200 | |
69 | ||
70 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL) | |
71 | ||
72 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ | |
73 | #include <cmd_confdefs.h> | |
74 | ||
75 | #define CONFIG_BOOTDELAY 3 | |
76 | #define CONFIG_BOOTARGS "root=/dev/mtdblock2 console=ttyS0,115200" | |
77 | #define CONFIG_ETHADDR 08:00:3e:26:0a:5b | |
78 | #define CONFIG_NETMASK 255.255.0.0 | |
79 | #define CONFIG_IPADDR 192.168.0.21 | |
80 | #define CONFIG_SERVERIP 192.168.0.250 | |
81 | #define CONFIG_BOOTCOMMAND "bootm 40000" | |
82 | #define CONFIG_CMDLINE_TAG | |
83 | ||
84 | /* | |
85 | * Miscellaneous configurable options | |
86 | */ | |
87 | #define CFG_LONGHELP /* undef to save memory */ | |
88 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
89 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
90 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
91 | #define CFG_MAXARGS 16 /* max number of command args */ | |
92 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
93 | ||
94 | #define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ | |
95 | #define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ | |
96 | ||
97 | #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ | |
98 | ||
99 | #define CFG_LOAD_ADDR 0xa2000000 /* default load address */ | |
100 | ||
101 | #define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ | |
102 | #define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */ | |
103 | ||
8bde7f77 | 104 | /* valid baudrates */ |
d9fd6ff5 WD |
105 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
106 | ||
107 | /* | |
108 | * Stack sizes | |
109 | * | |
110 | * The stack sizes are set up in start.S using the settings below | |
111 | */ | |
112 | #define CONFIG_STACKSIZE (128*1024) /* regular stack */ | |
113 | #ifdef CONFIG_USE_IRQ | |
114 | #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ | |
115 | #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ | |
116 | #endif | |
117 | ||
118 | /* | |
119 | * Physical Memory Map | |
120 | */ | |
121 | #define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ | |
122 | #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ | |
123 | #define PHYS_SDRAM_1_SIZE 0x01000000 /* 64 MB */ | |
124 | #define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ | |
125 | #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ | |
126 | #define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ | |
127 | #define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ | |
128 | #define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ | |
129 | #define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ | |
130 | ||
131 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ | |
132 | #define PHYS_FLASH_2 0x04000000 /* Flash Bank #1 */ | |
133 | #define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ | |
134 | ||
135 | #define CFG_DRAM_BASE 0xa0000000 | |
136 | #define CFG_DRAM_SIZE 0x04000000 | |
137 | ||
138 | #define CFG_FLASH_BASE PHYS_FLASH_1 | |
139 | ||
140 | /* | |
141 | * FLASH and environment organization | |
142 | */ | |
143 | #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
144 | #define CFG_MAX_FLASH_SECT 32 /* max number of sectors on one chip */ | |
145 | ||
146 | /* timeout values are in ticks */ | |
147 | #define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ | |
148 | #define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ | |
149 | ||
150 | #define CFG_ENV_IS_IN_FLASH 1 | |
151 | #define CFG_ENV_ADDR 0x00020000 /* absolute address for now */ | |
152 | #define CFG_ENV_SIZE 0x20000 /* 8K ouch, this may later be */ | |
153 | ||
154 | /****************************************************************************** | |
155 | * | |
156 | * CPU specific defines | |
157 | * | |
158 | ******************************************************************************/ | |
159 | ||
160 | /* | |
161 | * GPIO settings | |
162 | * | |
163 | * GPIO pin assignments | |
164 | * GPIO Name Dir Out AF | |
165 | * 0 NC | |
166 | * 1 NC | |
167 | * 2 SIRQ1 I | |
168 | * 3 SIRQ2 I | |
169 | * 4 SIRQ3 I | |
170 | * 5 DMAACK1 O 0 | |
171 | * 6 DMAACK2 O 0 | |
172 | * 7 DMAACK3 O 0 | |
173 | * 8 TC1 O 0 | |
174 | * 9 TC2 O 0 | |
175 | * 10 TC3 O 0 | |
176 | * 11 nDMAEN O 1 | |
177 | * 12 AENCTRL O 0 | |
178 | * 13 PLDTC O 0 | |
179 | * 14 ETHIRQ I | |
180 | * 15 NC | |
181 | * 16 NC | |
182 | * 17 NC | |
183 | * 18 RDY I | |
184 | * 19 DMASIO I | |
185 | * 20 ETHIRQ NC | |
186 | * 21 NC | |
187 | * 22 PGMEN O 1 FIXME for debug only enable flash | |
188 | * 23 NC | |
189 | * 24 NC | |
190 | * 25 NC | |
191 | * 26 NC | |
192 | * 27 NC | |
193 | * 28 NC | |
194 | * 29 NC | |
195 | * 30 NC | |
196 | * 31 NC | |
197 | * 32 NC | |
198 | * 33 NC | |
199 | * 34 FFRXD I 01 | |
200 | * 35 FFCTS I 01 | |
201 | * 36 FFDCD I 01 | |
202 | * 37 FFDSR I 01 | |
203 | * 38 FFRI I 01 | |
204 | * 39 FFTXD O 1 10 | |
205 | * 40 FFDTR O 0 10 | |
206 | * 41 FFRTS O 0 10 | |
207 | * 42 RS232FOFF O 0 00 | |
208 | * 43 NC | |
209 | * 44 NC | |
210 | * 45 IRSL0 O 0 | |
211 | * 46 IRRX0 I 01 | |
212 | * 47 IRTX0 O 0 10 | |
213 | * 48 NC | |
214 | * 49 nIOWE O 0 | |
215 | * 50 NC | |
216 | * 51 NC | |
217 | * 52 NC | |
218 | * 53 NC | |
219 | * 54 NC | |
220 | * 55 NC | |
221 | * 56 NC | |
222 | * 57 NC | |
223 | * 58 DKDIRQ I | |
224 | * 59 NC | |
225 | * 60 NC | |
226 | * 61 NC | |
227 | * 62 NC | |
228 | * 63 NC | |
229 | * 64 COMLED O 0 | |
230 | * 65 COMLED O 0 | |
231 | * 66 COMLED O 0 | |
232 | * 67 COMLED O 0 | |
233 | * 68 COMLED O 0 | |
234 | * 69 COMLED O 0 | |
235 | * 70 COMLED O 0 | |
236 | * 71 COMLED O 0 | |
237 | * 72 NC | |
238 | * 73 NC | |
239 | * 74 NC | |
240 | * 75 NC | |
241 | * 76 NC | |
242 | * 77 NC | |
243 | * 78 CSIO O 1 | |
244 | * 79 NC | |
245 | * 80 CSETH O 1 | |
246 | * | |
247 | * NOTE: All NC's are defined to be outputs | |
248 | * | |
249 | */ | |
250 | /* Pin direction control */ | |
251 | /* NOTE GPIO 0, 61, 62 are set for inputs due to CPLD SPAREs */ | |
252 | #define CFG_GPDR0_VAL 0xfff3bf02 | |
253 | #define CFG_GPDR1_VAL 0xfbffbf83 | |
254 | #define CFG_GPDR2_VAL 0x0001ffff | |
255 | /* Set and Clear registers */ | |
256 | #define CFG_GPSR0_VAL 0x00400800 | |
257 | #define CFG_GPSR1_VAL 0x00000480 | |
258 | #define CFG_GPSR2_VAL 0x00014000 | |
259 | #define CFG_GPCR0_VAL 0x00000000 | |
260 | #define CFG_GPCR1_VAL 0x00000000 | |
261 | #define CFG_GPCR2_VAL 0x00000000 | |
262 | /* Edge detect registers (these are set by the kernel) */ | |
263 | #define CFG_GRER0_VAL 0x00000000 | |
264 | #define CFG_GRER1_VAL 0x00000000 | |
265 | #define CFG_GRER2_VAL 0x00000000 | |
266 | #define CFG_GFER0_VAL 0x00000000 | |
267 | #define CFG_GFER1_VAL 0x00000000 | |
268 | #define CFG_GFER2_VAL 0x00000000 | |
269 | /* Alternate function registers */ | |
270 | #define CFG_GAFR0_L_VAL 0x00000000 | |
271 | #define CFG_GAFR0_U_VAL 0x00000010 | |
272 | #define CFG_GAFR1_L_VAL 0x900a9550 | |
273 | #define CFG_GAFR1_U_VAL 0x00000008 | |
274 | #define CFG_GAFR2_L_VAL 0x20000000 | |
275 | #define CFG_GAFR2_U_VAL 0x00000002 | |
276 | ||
277 | /* | |
278 | * Clocks, power control and interrupts | |
279 | */ | |
280 | #define CFG_PSSR_VAL 0x00000020 | |
281 | #define CFG_CCCR_VAL 0x00000141 /* 100 MHz memory, 200 MHz CPU */ | |
282 | #define CFG_CKEN_VAL 0x00000060 /* FFUART and STUART enabled */ | |
283 | #define CFG_ICMR_VAL 0x00000000 /* No interrupts enabled */ | |
284 | ||
285 | /* FIXME | |
286 | * | |
287 | * RTC settings | |
288 | * Watchdog | |
289 | * | |
290 | */ | |
291 | ||
292 | /* | |
293 | * Memory settings | |
294 | * | |
295 | * FIXME Can ethernet be burst read and/or write?? This is set for lubbock | |
296 | * Verify timings on all | |
297 | */ | |
298 | #define CFG_MSC0_VAL 0x000023FA /* flash bank (cs0) */ | |
299 | /*#define CFG_MSC1_VAL 0x00003549 / * SuperIO bank (cs2) */ | |
300 | #define CFG_MSC1_VAL 0x0000354c /* SuperIO bank (cs2) */ | |
301 | #define CFG_MSC2_VAL 0x00001224 /* Ethernet bank (cs4) */ | |
302 | #ifdef REDBOOT_WAY | |
303 | #define CFG_MDCNFG_VAL 0x00001aa1 /* FIXME can DTC be 01? */ | |
304 | #define CFG_MDMRS_VAL 0x00000000 | |
305 | #define CFG_MDREFR_VAL 0x00018018 | |
306 | #else | |
307 | #define CFG_MDCNFG_VAL 0x00001aa1 /* FIXME can DTC be 01? */ | |
308 | #define CFG_MDMRS_VAL 0x00000000 | |
400558b5 | 309 | #define CFG_MDREFR_VAL 0x00403018 /* Initial setting, individual bits set in lowlevel_init.S */ |
d9fd6ff5 WD |
310 | #endif |
311 | ||
312 | /* | |
313 | * PCMCIA and CF Interfaces (NOT USED, these values from lubbock init) | |
314 | */ | |
315 | #define CFG_MECR_VAL 0x00000000 | |
316 | #define CFG_MCMEM0_VAL 0x00010504 | |
317 | #define CFG_MCMEM1_VAL 0x00010504 | |
318 | #define CFG_MCATT0_VAL 0x00010504 | |
319 | #define CFG_MCATT1_VAL 0x00010504 | |
320 | #define CFG_MCIO0_VAL 0x00004715 | |
321 | #define CFG_MCIO1_VAL 0x00004715 | |
322 | ||
323 | /* Board specific defines */ | |
324 | ||
325 | /* LED defines */ | |
326 | #define YELLOW 0x03 | |
327 | #define RED 0x02 | |
328 | #define GREEN 0x01 | |
329 | #define OFF 0x00 | |
330 | #define LED_IRDA0 0 | |
331 | #define LED_IRDA1 2 | |
332 | #define LED_IRDA2 4 | |
333 | #define LED_IRDA3 6 | |
334 | #define CRADLE_LED_SET_REG GPSR2 | |
335 | #define CRADLE_LED_CLR_REG GPCR2 | |
336 | ||
337 | /* SuperIO defines */ | |
338 | #define CRADLE_SIO_INDEX 0x2e | |
339 | #define CRADLE_SIO_DATA 0x2f | |
340 | ||
341 | /* IO defines */ | |
342 | #define CRADLE_CPLD_PHYS 0x08000000 | |
343 | #define CRADLE_SIO1_PHYS 0x08100000 | |
344 | #define CRADLE_SIO2_PHYS 0x08200000 | |
345 | #define CRADLE_SIO3_PHYS 0x08300000 | |
346 | #define CRADLE_ETH_PHYS 0x10000000 | |
347 | ||
348 | #ifndef __ASSEMBLY__ | |
349 | ||
350 | /* global prototypes */ | |
351 | void led_code(int code, int color); | |
352 | ||
353 | #endif | |
354 | ||
355 | #endif /* __CONFIG_H */ |