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f9162b15 AB |
1 | /* |
2 | * Copyright (C) 2015 Timesys Corporation | |
3 | * Copyright (C) 2015 General Electric Company | |
4 | * Copyright (C) 2014 Advantech | |
5 | * Copyright (C) 2012 Freescale Semiconductor, Inc. | |
6 | * | |
7 | * Configuration settings for the GE MX6Q Bx50v3 boards. | |
8 | * | |
9 | * SPDX-License-Identifier: GPL-2.0+ | |
10 | */ | |
11 | ||
12 | #ifndef __GE_BX50V3_CONFIG_H | |
13 | #define __GE_BX50V3_CONFIG_H | |
14 | ||
15 | #include <asm/arch/imx-regs.h> | |
552a848e | 16 | #include <asm/mach-imx/gpio.h> |
f9162b15 | 17 | |
3dddc793 | 18 | #define BX50V3_BOOTARGS_EXTRA |
f9162b15 AB |
19 | #if defined(CONFIG_TARGET_GE_B450V3) |
20 | #define CONFIG_BOARD_NAME "General Electric B450v3" | |
f9162b15 AB |
21 | #elif defined(CONFIG_TARGET_GE_B650V3) |
22 | #define CONFIG_BOARD_NAME "General Electric B650v3" | |
f9162b15 AB |
23 | #elif defined(CONFIG_TARGET_GE_B850V3) |
24 | #define CONFIG_BOARD_NAME "General Electric B850v3" | |
3dddc793 KL |
25 | #undef BX50V3_BOOTARGS_EXTRA |
26 | #define BX50V3_BOOTARGS_EXTRA "video=DP-1:1024x768@60 " \ | |
27 | "video=HDMI-A-1:1024x768@60 " | |
f9162b15 AB |
28 | #else |
29 | #define CONFIG_BOARD_NAME "General Electric BA16 Generic" | |
f9162b15 AB |
30 | #endif |
31 | ||
32 | #define CONFIG_MXC_UART_BASE UART3_BASE | |
12ca05a3 | 33 | #define CONSOLE_DEV "ttymxc2" |
f9162b15 | 34 | |
f9162b15 AB |
35 | #define CONFIG_SUPPORT_EMMC_BOOT |
36 | ||
f9162b15 AB |
37 | |
38 | #include "mx6_common.h" | |
39 | #include <linux/sizes.h> | |
40 | ||
f9162b15 AB |
41 | #define CONFIG_CMDLINE_TAG |
42 | #define CONFIG_SETUP_MEMORY_TAGS | |
43 | #define CONFIG_INITRD_TAG | |
44 | #define CONFIG_REVISION_TAG | |
45 | #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) | |
46 | ||
6d656495 MW |
47 | #define CONFIG_HW_WATCHDOG |
48 | #define CONFIG_IMX_WATCHDOG | |
49 | #define CONFIG_WATCHDOG_TIMEOUT_MSECS 6000 | |
50 | ||
cf678b31 MW |
51 | #define CONFIG_LAST_STAGE_INIT |
52 | ||
f9162b15 AB |
53 | #define CONFIG_MXC_GPIO |
54 | #define CONFIG_MXC_UART | |
55 | ||
f9162b15 AB |
56 | #define CONFIG_MXC_OCOTP |
57 | ||
58 | /* SATA Configs */ | |
aacc10c5 | 59 | #ifdef CONFIG_CMD_SATA |
f9162b15 AB |
60 | #define CONFIG_SYS_SATA_MAX_DEVICE 1 |
61 | #define CONFIG_DWC_AHSATA_PORT_ID 0 | |
62 | #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR | |
63 | #define CONFIG_LBA48 | |
aacc10c5 | 64 | #endif |
f9162b15 AB |
65 | |
66 | /* MMC Configs */ | |
67 | #define CONFIG_FSL_ESDHC | |
68 | #define CONFIG_FSL_USDHC | |
69 | #define CONFIG_SYS_FSL_ESDHC_ADDR 0 | |
f9162b15 | 70 | #define CONFIG_BOUNCE_BUFFER |
f9162b15 AB |
71 | |
72 | /* USB Configs */ | |
fc44902a | 73 | #ifdef CONFIG_USB |
f9162b15 AB |
74 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
75 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
76 | #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) | |
77 | #define CONFIG_MXC_USB_FLAGS 0 | |
f9162b15 | 78 | |
f9162b15 | 79 | #define CONFIG_USBD_HS |
f9162b15 | 80 | #define CONFIG_USB_GADGET_MASS_STORAGE |
fc44902a | 81 | #endif |
f9162b15 AB |
82 | |
83 | /* Networking Configs */ | |
c26ffd9b | 84 | #ifdef CONFIG_NET |
f9162b15 AB |
85 | #define CONFIG_FEC_MXC |
86 | #define CONFIG_MII | |
87 | #define IMX_FEC_BASE ENET_BASE_ADDR | |
88 | #define CONFIG_FEC_XCV_TYPE RGMII | |
89 | #define CONFIG_ETHPRIME "FEC" | |
90 | #define CONFIG_FEC_MXC_PHYADDR 4 | |
f9162b15 | 91 | #define CONFIG_PHY_ATHEROS |
c26ffd9b | 92 | #endif |
f9162b15 AB |
93 | |
94 | /* Serial Flash */ | |
f9162b15 AB |
95 | #ifdef CONFIG_CMD_SF |
96 | #define CONFIG_MXC_SPI | |
97 | #define CONFIG_SF_DEFAULT_BUS 0 | |
98 | #define CONFIG_SF_DEFAULT_CS 0 | |
99 | #define CONFIG_SF_DEFAULT_SPEED 20000000 | |
100 | #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 | |
101 | #endif | |
102 | ||
103 | /* allow to overwrite serial and ethaddr */ | |
104 | #define CONFIG_ENV_OVERWRITE | |
105 | #define CONFIG_CONS_INDEX 1 | |
f9162b15 | 106 | |
f9162b15 AB |
107 | #define CONFIG_LOADADDR 0x12000000 |
108 | #define CONFIG_SYS_TEXT_BASE 0x17800000 | |
109 | ||
110 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
111 | "script=boot.scr\0" \ | |
44395c85 | 112 | "bootlimit=10\0" \ |
f07b3148 | 113 | "image=/boot/fitImage\0" \ |
12ca05a3 | 114 | "console=" CONSOLE_DEV "\0" \ |
f9162b15 | 115 | "fdt_high=0xffffffff\0" \ |
f9162b15 AB |
116 | "sddev=0\0" \ |
117 | "emmcdev=1\0" \ | |
118 | "partnum=1\0" \ | |
f9162b15 | 119 | "setargs=setenv bootargs console=${console},${baudrate} " \ |
f41a4583 | 120 | "root=/dev/${rootdev} ro rootwait cma=128M " \ |
3dddc793 | 121 | BX50V3_BOOTARGS_EXTRA "\0" \ |
f9162b15 AB |
122 | "loadimage=" \ |
123 | "ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \ | |
f9162b15 | 124 | "tryboot=" \ |
f07b3148 IR |
125 | "if run loadimage; then " \ |
126 | "run doboot; " \ | |
f9162b15 AB |
127 | "fi;\0" \ |
128 | "doboot=echo Booting from ${dev}:${devnum}:${partnum} ...; " \ | |
129 | "run setargs; " \ | |
f07b3148 | 130 | "bootm ${loadaddr}#conf@${confidx};\0 " \ |
f9162b15 | 131 | |
fc44902a | 132 | #define CONFIG_MMCBOOTCOMMAND \ |
f9162b15 | 133 | "setenv dev mmc; " \ |
78ca3350 | 134 | "setenv devnum ${emmcdev}; " \ |
f9162b15 | 135 | \ |
78ca3350 IR |
136 | "if ext2load ${dev} ${devnum}:5 0x7000A000 /boot/active/boot.img ; " \ |
137 | "then " \ | |
138 | "source 0x7000A000; " \ | |
f9162b15 AB |
139 | "fi; " \ |
140 | \ | |
78ca3350 IR |
141 | "setenv rootdev mmcblk0p${partnum}; " \ |
142 | \ | |
f9162b15 AB |
143 | "if mmc dev ${devnum}; then " \ |
144 | "run tryboot; " \ | |
145 | "fi; " \ | |
fc44902a AS |
146 | |
147 | #define CONFIG_USBBOOTCOMMAND \ | |
f07b3148 | 148 | "echo Unsupported; " \ |
f9162b15 | 149 | |
fc44902a AS |
150 | #ifdef CONFIG_CMD_USB |
151 | #define CONFIG_BOOTCOMMAND CONFIG_USBBOOTCOMMAND | |
152 | #else | |
153 | #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND | |
154 | #endif | |
155 | ||
f9162b15 AB |
156 | #define CONFIG_ARP_TIMEOUT 200UL |
157 | ||
158 | /* Miscellaneous configurable options */ | |
159 | #define CONFIG_SYS_LONGHELP | |
f9162b15 AB |
160 | #define CONFIG_AUTO_COMPLETE |
161 | ||
f9162b15 AB |
162 | #define CONFIG_SYS_MEMTEST_START 0x10000000 |
163 | #define CONFIG_SYS_MEMTEST_END 0x10010000 | |
164 | #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 | |
165 | ||
166 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | |
167 | ||
168 | #define CONFIG_CMDLINE_EDITING | |
f9162b15 AB |
169 | |
170 | /* Physical Memory Map */ | |
171 | #define CONFIG_NR_DRAM_BANKS 1 | |
172 | #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR | |
173 | ||
174 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM | |
175 | #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR | |
176 | #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE | |
177 | ||
178 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
179 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
180 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
181 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
182 | ||
e856bdcf | 183 | /* environment organization */ |
f9162b15 AB |
184 | #define CONFIG_ENV_SIZE (8 * 1024) |
185 | #define CONFIG_ENV_OFFSET (768 * 1024) | |
186 | #define CONFIG_ENV_SECT_SIZE (64 * 1024) | |
187 | #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS | |
188 | #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS | |
189 | #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE | |
190 | #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED | |
191 | ||
f9162b15 | 192 | #ifndef CONFIG_SYS_DCACHE_OFF |
f9162b15 AB |
193 | #endif |
194 | ||
195 | #define CONFIG_SYS_FSL_USDHC_NUM 3 | |
196 | ||
197 | /* Framebuffer */ | |
07aa030a | 198 | #ifdef CONFIG_VIDEO |
f9162b15 | 199 | #define CONFIG_VIDEO_IPUV3 |
f9162b15 AB |
200 | #define CONFIG_VIDEO_BMP_RLE8 |
201 | #define CONFIG_SPLASH_SCREEN | |
202 | #define CONFIG_SPLASH_SCREEN_ALIGN | |
203 | #define CONFIG_BMP_16BPP | |
204 | #define CONFIG_VIDEO_LOGO | |
205 | #define CONFIG_VIDEO_BMP_LOGO | |
f9162b15 AB |
206 | #define CONFIG_IMX_HDMI |
207 | #define CONFIG_IMX_VIDEO_SKIP | |
07aa030a | 208 | #endif |
f9162b15 | 209 | |
54971ac6 AB |
210 | #define CONFIG_PWM_IMX |
211 | #define CONFIG_IMX6_PWM_PER_CLK 66000000 | |
212 | ||
3414913c IR |
213 | #define CONFIG_PCI |
214 | #define CONFIG_PCI_PNP | |
f9162b15 AB |
215 | #define CONFIG_PCI_SCAN_SHOW |
216 | #define CONFIG_PCIE_IMX | |
217 | #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) | |
218 | #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(1, 5) | |
f9162b15 AB |
219 | |
220 | /* I2C Configs */ | |
f9162b15 AB |
221 | #define CONFIG_SYS_I2C |
222 | #define CONFIG_SYS_I2C_MXC | |
223 | #define CONFIG_SYS_I2C_SPEED 100000 | |
224 | #define CONFIG_SYS_I2C_MXC_I2C1 | |
225 | #define CONFIG_SYS_I2C_MXC_I2C2 | |
226 | #define CONFIG_SYS_I2C_MXC_I2C3 | |
227 | ||
87da89e8 | 228 | #define CONFIG_SYS_NUM_I2C_BUSES 11 |
be2808c3 IR |
229 | #define CONFIG_SYS_I2C_MAX_HOPS 1 |
230 | #define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ | |
87da89e8 MW |
231 | {1, {I2C_NULL_HOP} }, \ |
232 | {2, {I2C_NULL_HOP} }, \ | |
be2808c3 IR |
233 | {0, {{I2C_MUX_PCA9547, 0x70, 0} } }, \ |
234 | {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ | |
235 | {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ | |
236 | {0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \ | |
237 | {0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \ | |
238 | {0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \ | |
239 | {0, {{I2C_MUX_PCA9547, 0x70, 6} } }, \ | |
240 | {0, {{I2C_MUX_PCA9547, 0x70, 7} } }, \ | |
241 | } | |
242 | ||
243 | #define CONFIG_BCH | |
244 | ||
44395c85 IR |
245 | #define CONFIG_BOOTCOUNT_LIMIT |
246 | #define CONFIG_BOOTCOUNT_EXT | |
247 | #define CONFIG_SYS_BOOTCOUNT_EXT_INTERFACE "mmc" | |
248 | #define CONFIG_SYS_BOOTCOUNT_EXT_DEVPART "1:5" | |
249 | #define CONFIG_SYS_BOOTCOUNT_EXT_NAME "/boot/failures" | |
250 | #define CONFIG_SYS_BOOTCOUNT_ADDR 0x7000A000 | |
251 | ||
f9162b15 | 252 | #endif /* __GE_BX50V3_CONFIG_H */ |