[people/ms/u-boot.git] / include / configs / imx31_litekit.h

/*
 * (C) Copyright 2004
 * Texas Instruments.
 * Richard Woodruff <r-woodruff2@ti.com>
 * Kshitij Gupta <kshitij@ti.com>
 *
 * Configuration settings for the LogicPD i.MX31 Litekit board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <asm/arch/mx31-regs.h>

 /* High Level Configuration Options */
#define CONFIG_ARM1136		1    /* This is an arm1136 CPU core */
#define CONFIG_MX31		1    /* in a mx31 */
#define CONFIG_MX31_HCLK_FREQ	26000000
#define CONFIG_MX31_CLK32	32000

#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

/* Temporarily disabled */
#if 0
#define CONFIG_OF_LIBFDT		1
#define CONFIG_FIT			1
#define CONFIG_FIT_VERBOSE		1
#endif

#define CONFIG_CMDLINE_TAG		1    /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_INITRD_TAG		1

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
#define CONFIG_SYS_GBL_DATA_SIZE	128  /* size in bytes reserved for initial data */

/*
 * Hardware drivers
 */

#define CONFIG_MXC_UART	1
#define CONFIG_SYS_MX31_UART1		1

#define CONFIG_HARD_SPI		1
#define CONFIG_MXC_SPI		1
#define CONFIG_DEFAULT_SPI_BUS	1
#define CONFIG_DEFAULT_SPI_MODE	(SPI_MODE_0 | SPI_CS_HIGH)

#define CONFIG_FSL_PMIC
#define CONFIG_FSL_PMIC_BUS	1
#define CONFIG_FSL_PMIC_CS	0
#define CONFIG_FSL_PMIC_CLK	1000000
#define CONFIG_FSL_PMIC_MODE	(SPI_MODE_0 | SPI_CS_HIGH)

#define CONFIG_RTC_MC13783	1

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX	1
#define CONFIG_BAUDRATE		115200
#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}

/***********************************************************
 * Command definition
 ***********************************************************/

#include <config_cmd_default.h>

#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_SPI
#define CONFIG_CMD_DATE
#define CONFIG_CMD_NAND

#define CONFIG_BOOTDELAY	3

#define CONFIG_NETMASK		255.255.255.0
#define CONFIG_IPADDR		192.168.23.168
#define CONFIG_SERVERIP		192.168.23.2

#define	CONFIG_EXTRA_ENV_SETTINGS											\
	"bootargs_base=setenv bootargs console=ttySMX0,115200\0"							\
	"bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0"	\
	"bootcmd=run bootcmd_net\0"											\
	"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; tftpboot 0x80000000 uImage-mx31; bootm\0"		\
	"prg_uboot=tftpboot 0x80000000 u-boot-imx31_litekit.bin; protect off all; erase 0xa00d0000 0xa01effff; cp.b 0x80000000 0xa00d0000 $(filesize)\0"


#define CONFIG_NET_MULTI
#define CONFIG_SMC911X		1
#define CONFIG_SMC911X_BASE	(CS4_BASE + 0x00020000)
#define CONFIG_SMC911X_32_BIT	1

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_PROMPT		"uboot> "
#define CONFIG_SYS_CBSIZE		256  /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS		16          /* max number of command args */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size */

#define CONFIG_SYS_MEMTEST_START	0  /* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x10000

#define CONFIG_SYS_LOAD_ADDR		0 /* default load address */

#define CONFIG_SYS_HZ			1000

#define CONFIG_CMDLINE_EDITING	1

/*-----------------------------------------------------------------------
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE	(128 * 1024) /* regular stack */

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	1
#define PHYS_SDRAM_1		CSD0_BASE
#define PHYS_SDRAM_1_SIZE	(128 * 1024 * 1024)

#undef CONFIG_SYS_ARM_WITHOUT_RELOC
#define CONFIG_SYS_SDRAM_BASE		CSD0_BASE
#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE		IRAM_SIZE
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */
#define CONFIG_SYS_FLASH_BASE		CS0_BASE
#define CONFIG_SYS_MAX_FLASH_BANKS	1           /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT	128	     /* max number of sectors on one chip */
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */

#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x001f0000)
#define	CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_SECT_SIZE	(64 * 1024)
#define CONFIG_ENV_SIZE		(64 * 1024)

/*-----------------------------------------------------------------------
 * CFI FLASH driver setup
 */
#define CONFIG_SYS_FLASH_CFI		1	/* Flash memory is CFI compliant */
#define CONFIG_FLASH_CFI_DRIVER	1	/* Use drivers/cfi_flash.c */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* Use buffered writes (~10x faster) */
#define CONFIG_SYS_FLASH_PROTECTION	1	/* Use hardware sector protection */

/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(100*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
#define CONFIG_SYS_FLASH_WRITE_TOUT	(100*CONFIG_SYS_HZ) /* Timeout for Flash Write */

/*
 * JFFS2 partitions
 */
#undef CONFIG_CMD_MTDPARTS
#define CONFIG_JFFS2_DEV	"nor0"

/*
 * NAND flash
 */
#define CONFIG_NAND_MXC
#define CONFIG_MXC_NAND_REGS_BASE	NFC_BASE_ADDR
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BASE		NFC_BASE_ADDR
#define CONFIG_MXC_NAND_HWECC

#endif /* __CONFIG_H */
Commit	Line	Data
caebc95b SH	1	/*
	2	* (C) Copyright 2004
	3	* Texas Instruments.
	4	* Richard Woodruff <r-woodruff2@ti.com>
	5	* Kshitij Gupta <kshitij@ti.com>
	6	*
7064122c	7	* Configuration settings for the LogicPD i.MX31 Litekit board.
caebc95b SH	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
e7ae84d6 ML	31	#include <asm/arch/mx31-regs.h>
e7ae84d6 ML	32
caebc95b SH	33	/* High Level Configuration Options */
	34	#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
	35	#define CONFIG_MX31 1 /* in a mx31 */
	36	#define CONFIG_MX31_HCLK_FREQ 26000000
	37	#define CONFIG_MX31_CLK32 32000
	38
	39	#define CONFIG_DISPLAY_CPUINFO
	40	#define CONFIG_DISPLAY_BOARDINFO
	41
	42	/* Temporarily disabled */
	43	#if 0
	44	#define CONFIG_OF_LIBFDT 1
	45	#define CONFIG_FIT 1
	46	#define CONFIG_FIT_VERBOSE 1
	47	#endif
	48
	49	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	50	#define CONFIG_SETUP_MEMORY_TAGS 1
	51	#define CONFIG_INITRD_TAG 1
	52
	53	/*
	54	* Size of malloc() pool
	55	*/
6d0f6bcf JCPV	56	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
6d0f6bcf JCPV	57	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
caebc95b SH	58
	59	/*
	60	* Hardware drivers
	61	*/
	62
47d19da4	63	#define CONFIG_MXC_UART 1
6d0f6bcf	64	#define CONFIG_SYS_MX31_UART1 1
caebc95b	65
f9204e15 ML	66	#define CONFIG_HARD_SPI 1
f9204e15 ML	67	#define CONFIG_MXC_SPI 1
d255bb0e	68	#define CONFIG_DEFAULT_SPI_BUS 1
9f481e95	69	#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 \| SPI_CS_HIGH)
f9204e15	70
dfe5e14f SB	71	#define CONFIG_FSL_PMIC
	72	#define CONFIG_FSL_PMIC_BUS 1
	73	#define CONFIG_FSL_PMIC_CS 0
	74	#define CONFIG_FSL_PMIC_CLK 1000000
9f481e95	75	#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 \| SPI_CS_HIGH)
dfe5e14f	76
f9204e15 ML	77	#define CONFIG_RTC_MC13783 1
f9204e15 ML	78
caebc95b SH	79	/* allow to overwrite serial and ethaddr */
	80	#define CONFIG_ENV_OVERWRITE
	81	#define CONFIG_CONS_INDEX 1
	82	#define CONFIG_BAUDRATE 115200
6d0f6bcf	83	#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
caebc95b SH	84
	85	/***********************************************************
	86	* Command definition
	87	***********************************************************/
	88
	89	#include <config_cmd_default.h>
	90
	91	#define CONFIG_CMD_MII
	92	#define CONFIG_CMD_PING
f9204e15 ML	93	#define CONFIG_CMD_SPI
f9204e15 ML	94	#define CONFIG_CMD_DATE
ba6adeb4	95	#define CONFIG_CMD_NAND
caebc95b SH	96
	97	#define CONFIG_BOOTDELAY 3
	98
	99	#define CONFIG_NETMASK 255.255.255.0
	100	#define CONFIG_IPADDR 192.168.23.168
	101	#define CONFIG_SERVERIP 192.168.23.2
	102
	103	#define CONFIG_EXTRA_ENV_SETTINGS \
	104	"bootargs_base=setenv bootargs console=ttySMX0,115200\0" \
	105	"bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
	106	"bootcmd=run bootcmd_net\0" \
	107	"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; tftpboot 0x80000000 uImage-mx31; bootm\0" \
	108	"prg_uboot=tftpboot 0x80000000 u-boot-imx31_litekit.bin; protect off all; erase 0xa00d0000 0xa01effff; cp.b 0x80000000 0xa00d0000 $(filesize)\0"
	109
	110
736fead8 BW	111	#define CONFIG_NET_MULTI
	112	#define CONFIG_SMC911X 1
	113	#define CONFIG_SMC911X_BASE (CS4_BASE + 0x00020000)
	114	#define CONFIG_SMC911X_32_BIT 1
caebc95b SH	115
	116	/*
	117	* Miscellaneous configurable options
	118	*/
6d0f6bcf JCPV	119	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	120	#define CONFIG_SYS_PROMPT "uboot> "
	121	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
caebc95b	122	/* Print Buffer Size */
6d0f6bcf JCPV	123	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
	124	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	125	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
caebc95b	126
6d0f6bcf JCPV	127	#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
6d0f6bcf JCPV	128	#define CONFIG_SYS_MEMTEST_END 0x10000
caebc95b	129
6d0f6bcf	130	#define CONFIG_SYS_LOAD_ADDR 0 /* default load address */
caebc95b	131
6d0f6bcf	132	#define CONFIG_SYS_HZ 1000
caebc95b SH	133
	134	#define CONFIG_CMDLINE_EDITING 1
	135
	136	/*-----------------------------------------------------------------------
	137	* Stack sizes
	138	*
	139	* The stack sizes are set up in start.S using the settings below
	140	*/
	141	#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
	142
	143	/*-----------------------------------------------------------------------
	144	* Physical Memory Map
	145	*/
	146	#define CONFIG_NR_DRAM_BANKS 1
e7ae84d6	147	#define PHYS_SDRAM_1 CSD0_BASE
caebc95b SH	148	#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
caebc95b SH	149
68a75d0b ML	150	#undef CONFIG_SYS_ARM_WITHOUT_RELOC
	151	#define CONFIG_SYS_SDRAM_BASE CSD0_BASE
	152	#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
553f0982 WD	153	#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
553f0982 WD	154	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
68a75d0b ML	155	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
68a75d0b ML	156
caebc95b SH	157	/*-----------------------------------------------------------------------
	158	* FLASH and environment organization
	159	*/
6d0f6bcf JCPV	160	#define CONFIG_SYS_FLASH_BASE CS0_BASE
	161	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	162	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
	163	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
caebc95b	164
6d0f6bcf	165	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x001f0000)
5a1aceb0	166	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	167	#define CONFIG_ENV_SECT_SIZE (64 * 1024)
0e8d1586 JCPV	168	#define CONFIG_ENV_SIZE (64 * 1024)
caebc95b SH	169
	170	/*-----------------------------------------------------------------------
	171	* CFI FLASH driver setup
	172	*/
6d0f6bcf	173	#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */
00b1883a	174	#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
6d0f6bcf JCPV	175	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
6d0f6bcf JCPV	176	#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */
caebc95b SH	177
caebc95b SH	178	/* timeout values are in ticks */
6d0f6bcf JCPV	179	#define CONFIG_SYS_FLASH_ERASE_TOUT (100CONFIG_SYS_HZ) / Timeout for Flash Erase */
6d0f6bcf JCPV	180	#define CONFIG_SYS_FLASH_WRITE_TOUT (100CONFIG_SYS_HZ) / Timeout for Flash Write */
caebc95b SH	181
	182	/*
	183	* JFFS2 partitions
	184	*/
68d7d651	185	#undef CONFIG_CMD_MTDPARTS
caebc95b SH	186	#define CONFIG_JFFS2_DEV "nor0"
caebc95b SH	187
ba6adeb4 ML	188	/*
	189	* NAND flash
	190	*/
	191	#define CONFIG_NAND_MXC
	192	#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR
	193	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	194	#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
	195	#define CONFIG_MXC_NAND_HWECC
	196
caebc95b	197	#endif /* __CONFIG_H */