projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 550e3dc0 WH |
1 | /* |
| 2 | * Copyright 2014 Freescale Semiconductor, Inc. | |
| 3 | * | |
| 4 | * SPDX-License-Identifier: GPL-2.0+ | |
| 5 | */ | |
| 6 | ||
| 7 | #ifndef __CONFIG_H | |
| 8 | #define __CONFIG_H | |
| 9 | ||
| 550e3dc0 WH |
10 | #define CONFIG_LS102XA |
| 11 | ||
| 340848b1 WD |
12 | #define CONFIG_ARMV7_PSCI |
| 13 | ||
| 18fb0e3c | 14 | #define CONFIG_SYS_FSL_CLK |
| 550e3dc0 WH |
15 | |
| 16 | #define CONFIG_DISPLAY_CPUINFO | |
| 17 | #define CONFIG_DISPLAY_BOARDINFO | |
| 18 | ||
| 19 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
| 20 | #define CONFIG_BOARD_EARLY_INIT_F | |
| 21 | ||
| 41ba57d0 | 22 | #define CONFIG_DEEP_SLEEP |
| 23 | #if defined(CONFIG_DEEP_SLEEP) | |
| 24 | #define CONFIG_SILENT_CONSOLE | |
| 25 | #endif | |
| 26 | ||
| 550e3dc0 WH |
27 | /* |
| 28 | * Size of malloc() pool | |
| 29 | */ | |
| 30 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) | |
| 31 | ||
| 32 | #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR | |
| 33 | #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE | |
| 34 | ||
| 35 | /* | |
| 36 | * Generic Timer Definitions | |
| 37 | */ | |
| 38 | #define GENERIC_TIMER_CLK 12500000 | |
| 39 | ||
| 40 | #ifndef __ASSEMBLY__ | |
| 41 | unsigned long get_board_sys_clk(void); | |
| 42 | unsigned long get_board_ddr_clk(void); | |
| 43 | #endif | |
| 44 | ||
| d612f0ab AW |
45 | #ifdef CONFIG_QSPI_BOOT |
| 46 | #define CONFIG_SYS_CLK_FREQ 100000000 | |
| 47 | #define CONFIG_DDR_CLK_FREQ 100000000 | |
| 48 | #define CONFIG_QIXIS_I2C_ACCESS | |
| 49 | #else | |
| 550e3dc0 WH |
50 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() |
| 51 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() | |
| d612f0ab | 52 | #endif |
| 550e3dc0 | 53 | |
| 86949c2b AW |
54 | #ifdef CONFIG_RAMBOOT_PBL |
| 55 | #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg | |
| 56 | #endif | |
| 57 | ||
| 58 | #ifdef CONFIG_SD_BOOT | |
| 59 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg | |
| 60 | #define CONFIG_SPL_FRAMEWORK | |
| 61 | #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" | |
| 62 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
| 63 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
| 64 | #define CONFIG_SPL_ENV_SUPPORT | |
| 65 | #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT | |
| 66 | #define CONFIG_SPL_I2C_SUPPORT | |
| 67 | #define CONFIG_SPL_WATCHDOG_SUPPORT | |
| 68 | #define CONFIG_SPL_SERIAL_SUPPORT | |
| 69 | #define CONFIG_SPL_DRIVERS_MISC_SUPPORT | |
| 70 | #define CONFIG_SPL_MMC_SUPPORT | |
| 71 | #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 | |
| 7ee52af4 | 72 | #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x600 |
| 86949c2b AW |
73 | |
| 74 | #define CONFIG_SPL_TEXT_BASE 0x10000000 | |
| 75 | #define CONFIG_SPL_MAX_SIZE 0x1a000 | |
| 76 | #define CONFIG_SPL_STACK 0x1001d000 | |
| 77 | #define CONFIG_SPL_PAD_TO 0x1c000 | |
| 78 | #define CONFIG_SYS_TEXT_BASE 0x82000000 | |
| 79 | ||
| 41ba57d0 | 80 | #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ |
| 81 | CONFIG_SYS_MONITOR_LEN) | |
| 86949c2b AW |
82 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 |
| 83 | #define CONFIG_SPL_BSS_START_ADDR 0x80100000 | |
| 84 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 | |
| 7ee52af4 | 85 | #define CONFIG_SYS_MONITOR_LEN 0xc0000 |
| 86949c2b AW |
86 | #endif |
| 87 | ||
| d612f0ab AW |
88 | #ifdef CONFIG_QSPI_BOOT |
| 89 | #define CONFIG_SYS_TEXT_BASE 0x40010000 | |
| 90 | #define CONFIG_SYS_NO_FLASH | |
| 91 | #endif | |
| 92 | ||
| 8ab967b6 AW |
93 | #ifdef CONFIG_NAND_BOOT |
| 94 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg | |
| 95 | #define CONFIG_SPL_FRAMEWORK | |
| 96 | #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" | |
| 97 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
| 98 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
| 99 | #define CONFIG_SPL_ENV_SUPPORT | |
| 100 | #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT | |
| 101 | #define CONFIG_SPL_I2C_SUPPORT | |
| 102 | #define CONFIG_SPL_WATCHDOG_SUPPORT | |
| 103 | #define CONFIG_SPL_SERIAL_SUPPORT | |
| 104 | #define CONFIG_SPL_NAND_SUPPORT | |
| 105 | #define CONFIG_SPL_DRIVERS_MISC_SUPPORT | |
| 106 | ||
| 107 | #define CONFIG_SPL_TEXT_BASE 0x10000000 | |
| 108 | #define CONFIG_SPL_MAX_SIZE 0x1a000 | |
| 109 | #define CONFIG_SPL_STACK 0x1001d000 | |
| 110 | #define CONFIG_SPL_PAD_TO 0x1c000 | |
| 111 | #define CONFIG_SYS_TEXT_BASE 0x82000000 | |
| 112 | ||
| 113 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10) | |
| 114 | #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO | |
| 115 | #define CONFIG_SYS_NAND_PAGE_SIZE 2048 | |
| 116 | #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE | |
| 117 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE | |
| 118 | ||
| 119 | #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 | |
| 120 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 | |
| 121 | #define CONFIG_SPL_BSS_START_ADDR 0x80100000 | |
| 122 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 | |
| 123 | #define CONFIG_SYS_MONITOR_LEN 0x80000 | |
| 124 | #endif | |
| 125 | ||
| 550e3dc0 | 126 | #ifndef CONFIG_SYS_TEXT_BASE |
| 1c69a51c | 127 | #define CONFIG_SYS_TEXT_BASE 0x60100000 |
| 550e3dc0 WH |
128 | #endif |
| 129 | ||
| 130 | #define CONFIG_NR_DRAM_BANKS 1 | |
| 131 | ||
| 132 | #define CONFIG_DDR_SPD | |
| 133 | #define SPD_EEPROM_ADDRESS 0x51 | |
| 134 | #define CONFIG_SYS_SPD_BUS_NUM 0 | |
| 550e3dc0 WH |
135 | |
| 136 | #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ | |
| c7eae7fc | 137 | #ifndef CONFIG_SYS_FSL_DDR4 |
| 550e3dc0 | 138 | #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ |
| c7eae7fc YS |
139 | #define CONFIG_SYS_DDR_RAW_TIMING |
| 140 | #endif | |
| 550e3dc0 WH |
141 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| 142 | #define CONFIG_CHIP_SELECTS_PER_CTRL 4 | |
| 143 | ||
| 144 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL | |
| 145 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
| 146 | ||
| 147 | #define CONFIG_DDR_ECC | |
| 148 | #ifdef CONFIG_DDR_ECC | |
| 149 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
| 150 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
| 151 | #endif | |
| 152 | ||
| 153 | #define CONFIG_SYS_HAS_SERDES | |
| 154 | ||
| 4ba4a095 | 155 | #define CONFIG_FSL_CAAM /* Enable CAAM */ |
| 63e75fd7 | 156 | |
| 4c59ab9c AW |
157 | #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ |
| 158 | !defined(CONFIG_QSPI_BOOT) | |
| 63e75fd7 ZQ |
159 | #define CONFIG_U_QE |
| 160 | #endif | |
| 161 | ||
| 550e3dc0 WH |
162 | /* |
| 163 | * IFC Definitions | |
| 164 | */ | |
| d612f0ab | 165 | #ifndef CONFIG_QSPI_BOOT |
| 550e3dc0 WH |
166 | #define CONFIG_FSL_IFC |
| 167 | #define CONFIG_SYS_FLASH_BASE 0x60000000 | |
| 168 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
| 169 | ||
| 170 | #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) | |
| 171 | #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
| 172 | CSPR_PORT_SIZE_16 | \ | |
| 173 | CSPR_MSEL_NOR | \ | |
| 174 | CSPR_V) | |
| 175 | #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) | |
| 176 | #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ | |
| 177 | + 0x8000000) | \ | |
| 178 | CSPR_PORT_SIZE_16 | \ | |
| 179 | CSPR_MSEL_NOR | \ | |
| 180 | CSPR_V) | |
| 181 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) | |
| 182 | ||
| 183 | #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ | |
| 184 | CSOR_NOR_TRHZ_80) | |
| 185 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ | |
| 186 | FTIM0_NOR_TEADC(0x5) | \ | |
| 187 | FTIM0_NOR_TEAHC(0x5)) | |
| 188 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ | |
| 189 | FTIM1_NOR_TRAD_NOR(0x1a) | \ | |
| 190 | FTIM1_NOR_TSEQRAD_NOR(0x13)) | |
| 191 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ | |
| 192 | FTIM2_NOR_TCH(0x4) | \ | |
| 193 | FTIM2_NOR_TWPH(0xe) | \ | |
| 194 | FTIM2_NOR_TWP(0x1c)) | |
| 195 | #define CONFIG_SYS_NOR_FTIM3 0 | |
| 196 | ||
| 197 | #define CONFIG_FLASH_CFI_DRIVER | |
| 198 | #define CONFIG_SYS_FLASH_CFI | |
| 199 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
| 200 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
| 201 | #define CONFIG_FLASH_SHOW_PROGRESS 45 | |
| 202 | #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS | |
| 272c5265 | 203 | #define CONFIG_SYS_WRITE_SWAPPED_DATA |
| 550e3dc0 WH |
204 | |
| 205 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
| 206 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
| 207 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 208 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 209 | ||
| 210 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
| 211 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ | |
| 212 | CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} | |
| 213 | ||
| 214 | /* | |
| 215 | * NAND Flash Definitions | |
| 216 | */ | |
| 217 | #define CONFIG_NAND_FSL_IFC | |
| 218 | ||
| 219 | #define CONFIG_SYS_NAND_BASE 0x7e800000 | |
| 220 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
| 221 | ||
| 222 | #define CONFIG_SYS_NAND_CSPR_EXT (0x0) | |
| 223 | ||
| 224 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
| 225 | | CSPR_PORT_SIZE_8 \ | |
| 226 | | CSPR_MSEL_NAND \ | |
| 227 | | CSPR_V) | |
| 228 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) | |
| 229 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | |
| 230 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
| 231 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
| 232 | | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ | |
| 233 | | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ | |
| 234 | | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ | |
| 235 | | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ | |
| 236 | ||
| 237 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
| 238 | ||
| 239 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ | |
| 240 | FTIM0_NAND_TWP(0x18) | \ | |
| 241 | FTIM0_NAND_TWCHT(0x7) | \ | |
| 242 | FTIM0_NAND_TWH(0xa)) | |
| 243 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ | |
| 244 | FTIM1_NAND_TWBE(0x39) | \ | |
| 245 | FTIM1_NAND_TRR(0xe) | \ | |
| 246 | FTIM1_NAND_TRP(0x18)) | |
| 247 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ | |
| 248 | FTIM2_NAND_TREH(0xa) | \ | |
| 249 | FTIM2_NAND_TWHRE(0x1e)) | |
| 250 | #define CONFIG_SYS_NAND_FTIM3 0x0 | |
| 251 | ||
| 252 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
| 253 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
| 550e3dc0 WH |
254 | #define CONFIG_CMD_NAND |
| 255 | ||
| 256 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
| d612f0ab | 257 | #endif |
| 550e3dc0 WH |
258 | |
| 259 | /* | |
| 260 | * QIXIS Definitions | |
| 261 | */ | |
| 262 | #define CONFIG_FSL_QIXIS | |
| 263 | ||
| 264 | #ifdef CONFIG_FSL_QIXIS | |
| 265 | #define QIXIS_BASE 0x7fb00000 | |
| 266 | #define QIXIS_BASE_PHYS QIXIS_BASE | |
| 267 | #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 | |
| 268 | #define QIXIS_LBMAP_SWITCH 6 | |
| 269 | #define QIXIS_LBMAP_MASK 0x0f | |
| 270 | #define QIXIS_LBMAP_SHIFT 0 | |
| 271 | #define QIXIS_LBMAP_DFLTBANK 0x00 | |
| 272 | #define QIXIS_LBMAP_ALTBANK 0x04 | |
| 273 | #define QIXIS_RST_CTL_RESET 0x44 | |
| 274 | #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 | |
| 275 | #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 | |
| 276 | #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 | |
| 277 | ||
| 278 | #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) | |
| 279 | #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ | |
| 280 | CSPR_PORT_SIZE_8 | \ | |
| 281 | CSPR_MSEL_GPCM | \ | |
| 282 | CSPR_V) | |
| 283 | #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) | |
| 284 | #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ | |
| 285 | CSOR_NOR_NOR_MODE_AVD_NOR | \ | |
| 286 | CSOR_NOR_TRHZ_80) | |
| 287 | ||
| 288 | /* | |
| 289 | * QIXIS Timing parameters for IFC GPCM | |
| 290 | */ | |
| 291 | #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \ | |
| 292 | FTIM0_GPCM_TEADC(0xe) | \ | |
| 293 | FTIM0_GPCM_TEAHC(0xe)) | |
| 294 | #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \ | |
| 295 | FTIM1_GPCM_TRAD(0x1f)) | |
| 296 | #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \ | |
| 297 | FTIM2_GPCM_TCH(0xe) | \ | |
| 298 | FTIM2_GPCM_TWP(0xf0)) | |
| 299 | #define CONFIG_SYS_FPGA_FTIM3 0x0 | |
| 300 | #endif | |
| 301 | ||
| 8ab967b6 AW |
302 | #if defined(CONFIG_NAND_BOOT) |
| 303 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT | |
| 304 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR | |
| 305 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
| 306 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
| 307 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
| 308 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
| 309 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
| 310 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
| 311 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
| 312 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR | |
| 313 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
| 314 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
| 315 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 316 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 317 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 318 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 319 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT | |
| 320 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR | |
| 321 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK | |
| 322 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR | |
| 323 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 324 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 325 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 326 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 327 | #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT | |
| 328 | #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR | |
| 329 | #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK | |
| 330 | #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR | |
| 331 | #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 | |
| 332 | #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 | |
| 333 | #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 | |
| 334 | #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 | |
| 335 | #else | |
| 550e3dc0 WH |
336 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT |
| 337 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR | |
| 338 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
| 339 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
| 340 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 341 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 342 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 343 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 344 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT | |
| 345 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR | |
| 346 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
| 347 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
| 348 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
| 349 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
| 350 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
| 351 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
| 352 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT | |
| 353 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR | |
| 354 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK | |
| 355 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR | |
| 356 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
| 357 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
| 358 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
| 359 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
| 360 | #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT | |
| 361 | #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR | |
| 362 | #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK | |
| 363 | #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR | |
| 364 | #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 | |
| 365 | #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 | |
| 366 | #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 | |
| 367 | #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 | |
| 8ab967b6 | 368 | #endif |
| 550e3dc0 WH |
369 | |
| 370 | /* | |
| 371 | * Serial Port | |
| 372 | */ | |
| 8fc2121a AW |
373 | #ifdef CONFIG_LPUART |
| 374 | #define CONFIG_FSL_LPUART | |
| 375 | #define CONFIG_LPUART_32B_REG | |
| 376 | #else | |
| 550e3dc0 | 377 | #define CONFIG_CONS_INDEX 1 |
| 550e3dc0 WH |
378 | #define CONFIG_SYS_NS16550_SERIAL |
| 379 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 380 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
| 8fc2121a | 381 | #endif |
| 550e3dc0 WH |
382 | |
| 383 | #define CONFIG_BAUDRATE 115200 | |
| 384 | ||
| 385 | /* | |
| 386 | * I2C | |
| 387 | */ | |
| 388 | #define CONFIG_CMD_I2C | |
| 389 | #define CONFIG_SYS_I2C | |
| 390 | #define CONFIG_SYS_I2C_MXC | |
| 03544c66 AA |
391 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
| 392 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ | |
| f8cb101e | 393 | #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ |
| 550e3dc0 WH |
394 | |
| 395 | /* | |
| 396 | * I2C bus multiplexer | |
| 397 | */ | |
| 398 | #define I2C_MUX_PCA_ADDR_PRI 0x77 | |
| 399 | #define I2C_MUX_CH_DEFAULT 0x8 | |
| dd04832d | 400 | #define I2C_MUX_CH_CH7301 0xC |
| 550e3dc0 WH |
401 | |
| 402 | /* | |
| 403 | * MMC | |
| 404 | */ | |
| 405 | #define CONFIG_MMC | |
| 406 | #define CONFIG_CMD_MMC | |
| 407 | #define CONFIG_FSL_ESDHC | |
| 408 | #define CONFIG_GENERIC_MMC | |
| 409 | ||
| 8251ed23 AW |
410 | #define CONFIG_CMD_FAT |
| 411 | #define CONFIG_DOS_PARTITION | |
| 412 | ||
| e5493d4e | 413 | /* SPI */ |
| d612f0ab | 414 | #ifdef CONFIG_QSPI_BOOT |
| e5493d4e | 415 | /* QSPI */ |
| d612f0ab AW |
416 | #define CONFIG_FSL_QSPI |
| 417 | #define QSPI0_AMBA_BASE 0x40000000 | |
| 418 | #define FSL_QSPI_FLASH_SIZE (1 << 24) | |
| 419 | #define FSL_QSPI_FLASH_NUM 2 | |
| e5493d4e | 420 | #define CONFIG_SPI_FLASH_SPANSION |
| d612f0ab | 421 | |
| e5493d4e HW |
422 | /* DSPI */ |
| 423 | #define CONFIG_FSL_DSPI | |
| 424 | ||
| 425 | /* DM SPI */ | |
| 426 | #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) | |
| d612f0ab | 427 | #define CONFIG_CMD_SF |
| e5493d4e | 428 | #define CONFIG_DM_SPI_FLASH |
| 6812484a | 429 | #define CONFIG_SPI_FLASH_DATAFLASH |
| e5493d4e | 430 | #endif |
| d612f0ab AW |
431 | #endif |
| 432 | ||
| 8776cb20 NB |
433 | /* |
| 434 | * USB | |
| 435 | */ | |
| 081a1b73 RM |
436 | /* EHCI Support - disbaled by default */ |
| 437 | /*#define CONFIG_HAS_FSL_DR_USB*/ | |
| 8776cb20 NB |
438 | |
| 439 | #ifdef CONFIG_HAS_FSL_DR_USB | |
| 440 | #define CONFIG_USB_EHCI | |
| 081a1b73 RM |
441 | #define CONFIG_USB_EHCI_FSL |
| 442 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
| 443 | #endif | |
| 8776cb20 | 444 | |
| 081a1b73 RM |
445 | /*XHCI Support - enabled by default*/ |
| 446 | #define CONFIG_HAS_FSL_XHCI_USB | |
| 447 | ||
| 448 | #ifdef CONFIG_HAS_FSL_XHCI_USB | |
| 449 | #define CONFIG_USB_XHCI_FSL | |
| 450 | #define CONFIG_USB_XHCI_DWC3 | |
| 451 | #define CONFIG_USB_XHCI | |
| 452 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 | |
| 453 | #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 | |
| 454 | #endif | |
| 455 | ||
| 456 | #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB) | |
| 8776cb20 NB |
457 | #define CONFIG_CMD_USB |
| 458 | #define CONFIG_USB_STORAGE | |
| 8776cb20 NB |
459 | #define CONFIG_CMD_EXT2 |
| 460 | #endif | |
| 8776cb20 | 461 | |
| dd04832d XL |
462 | /* |
| 463 | * Video | |
| 464 | */ | |
| 465 | #define CONFIG_FSL_DCU_FB | |
| 466 | ||
| 467 | #ifdef CONFIG_FSL_DCU_FB | |
| 468 | #define CONFIG_VIDEO | |
| 469 | #define CONFIG_CMD_BMP | |
| 470 | #define CONFIG_CFB_CONSOLE | |
| 471 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
| 472 | #define CONFIG_VIDEO_LOGO | |
| 473 | #define CONFIG_VIDEO_BMP_LOGO | |
| 474 | ||
| 475 | #define CONFIG_FSL_DIU_CH7301 | |
| 476 | #define CONFIG_SYS_I2C_DVI_BUS_NUM 0 | |
| 477 | #define CONFIG_SYS_I2C_QIXIS_ADDR 0x66 | |
| 478 | #define CONFIG_SYS_I2C_DVI_ADDR 0x75 | |
| 479 | #endif | |
| 480 | ||
| 550e3dc0 WH |
481 | /* |
| 482 | * eTSEC | |
| 483 | */ | |
| 484 | #define CONFIG_TSEC_ENET | |
| 485 | ||
| 486 | #ifdef CONFIG_TSEC_ENET | |
| 487 | #define CONFIG_MII | |
| 488 | #define CONFIG_MII_DEFAULT_TSEC 3 | |
| 489 | #define CONFIG_TSEC1 1 | |
| 490 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
| 491 | #define CONFIG_TSEC2 1 | |
| 492 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
| 493 | #define CONFIG_TSEC3 1 | |
| 494 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
| 495 | ||
| 496 | #define TSEC1_PHY_ADDR 1 | |
| 497 | #define TSEC2_PHY_ADDR 2 | |
| 498 | #define TSEC3_PHY_ADDR 3 | |
| 499 | ||
| 500 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 501 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 502 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 503 | ||
| 504 | #define TSEC1_PHYIDX 0 | |
| 505 | #define TSEC2_PHYIDX 0 | |
| 506 | #define TSEC3_PHYIDX 0 | |
| 507 | ||
| 508 | #define CONFIG_ETHPRIME "eTSEC1" | |
| 509 | ||
| 510 | #define CONFIG_PHY_GIGE | |
| 511 | #define CONFIG_PHYLIB | |
| 512 | #define CONFIG_PHY_REALTEK | |
| 513 | ||
| 514 | #define CONFIG_HAS_ETH0 | |
| 515 | #define CONFIG_HAS_ETH1 | |
| 516 | #define CONFIG_HAS_ETH2 | |
| 517 | ||
| 518 | #define CONFIG_FSL_SGMII_RISER 1 | |
| 519 | #define SGMII_RISER_PHY_OFFSET 0x1b | |
| 520 | ||
| 521 | #ifdef CONFIG_FSL_SGMII_RISER | |
| 522 | #define CONFIG_SYS_TBIPA_VALUE 8 | |
| 523 | #endif | |
| 524 | ||
| 525 | #endif | |
| da419027 ML |
526 | |
| 527 | /* PCIe */ | |
| 528 | #define CONFIG_PCI /* Enable PCI/PCIE */ | |
| 529 | #define CONFIG_PCIE1 /* PCIE controler 1 */ | |
| 530 | #define CONFIG_PCIE2 /* PCIE controler 2 */ | |
| 531 | #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ | |
| 532 | #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" | |
| 533 | ||
| 180b8688 ML |
534 | #define CONFIG_SYS_PCI_64BIT |
| 535 | ||
| 536 | #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 | |
| 537 | #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ | |
| 538 | #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 | |
| 539 | #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ | |
| 540 | ||
| 541 | #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 | |
| 542 | #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 | |
| 543 | #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ | |
| 544 | ||
| 545 | #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 | |
| 546 | #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 | |
| 547 | #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ | |
| 548 | ||
| 549 | #ifdef CONFIG_PCI | |
| 180b8688 | 550 | #define CONFIG_PCI_PNP |
| 180b8688 ML |
551 | #define CONFIG_PCI_SCAN_SHOW |
| 552 | #define CONFIG_CMD_PCI | |
| 180b8688 ML |
553 | #endif |
| 554 | ||
| 550e3dc0 WH |
555 | #define CONFIG_CMD_PING |
| 556 | #define CONFIG_CMD_DHCP | |
| 557 | #define CONFIG_CMD_MII | |
| 550e3dc0 WH |
558 | |
| 559 | #define CONFIG_CMDLINE_TAG | |
| 560 | #define CONFIG_CMDLINE_EDITING | |
| 86949c2b | 561 | |
| 1a2826f6 XL |
562 | #define CONFIG_ARMV7_NONSEC |
| 563 | #define CONFIG_ARMV7_VIRT | |
| 564 | #define CONFIG_PEN_ADDR_BIG_ENDIAN | |
| 435acd83 | 565 | #define CONFIG_LAYERSCAPE_NS_ACCESS |
| 1a2826f6 XL |
566 | #define CONFIG_SMP_PEN_ADDR 0x01ee0200 |
| 567 | #define CONFIG_TIMER_CLK_FREQ 12500000 | |
| 1a2826f6 | 568 | |
| 550e3dc0 | 569 | #define CONFIG_HWCONFIG |
| 03c22449 ZZ |
570 | #define HWCONFIG_BUFFER_SIZE 256 |
| 571 | ||
| 572 | #define CONFIG_FSL_DEVICE_DISABLE | |
| 550e3dc0 WH |
573 | |
| 574 | #define CONFIG_BOOTDELAY 3 | |
| 575 | ||
| 713bf94f | 576 | #define CONFIG_SYS_QE_FW_ADDR 0x600c0000 |
| 63e75fd7 | 577 | |
| 8fc2121a AW |
578 | #ifdef CONFIG_LPUART |
| 579 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 580 | "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ | |
| 581 | "fdt_high=0xcfffffff\0" \ | |
| 582 | "initrd_high=0xcfffffff\0" \ | |
| 583 | "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" | |
| 584 | #else | |
| 550e3dc0 WH |
585 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 586 | "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ | |
| 587 | "fdt_high=0xcfffffff\0" \ | |
| 588 | "initrd_high=0xcfffffff\0" \ | |
| 589 | "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" | |
| 8fc2121a | 590 | #endif |
| 550e3dc0 WH |
591 | |
| 592 | /* | |
| 593 | * Miscellaneous configurable options | |
| 594 | */ | |
| 595 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
| 596 | #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ | |
| 597 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
| 550e3dc0 WH |
598 | #define CONFIG_AUTO_COMPLETE |
| 599 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 600 | #define CONFIG_SYS_PBSIZE \ | |
| 601 | (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
| 602 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 603 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
| 604 | ||
| 550e3dc0 WH |
605 | #define CONFIG_CMD_GREPENV |
| 606 | #define CONFIG_CMD_MEMINFO | |
| 607 | #define CONFIG_CMD_MEMTEST | |
| 608 | #define CONFIG_SYS_MEMTEST_START 0x80000000 | |
| 609 | #define CONFIG_SYS_MEMTEST_END 0x9fffffff | |
| 610 | ||
| 611 | #define CONFIG_SYS_LOAD_ADDR 0x82000000 | |
| 550e3dc0 | 612 | |
| 660673af XL |
613 | #define CONFIG_LS102XA_STREAM_ID |
| 614 | ||
| 550e3dc0 WH |
615 | /* |
| 616 | * Stack sizes | |
| 617 | * The stack sizes are set up in start.S using the settings below | |
| 618 | */ | |
| 619 | #define CONFIG_STACKSIZE (30 * 1024) | |
| 620 | ||
| 621 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
| 622 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
| 623 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
| 624 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
| 625 | ||
| 86949c2b AW |
626 | #ifdef CONFIG_SPL_BUILD |
| 627 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE | |
| 628 | #else | |
| 550e3dc0 | 629 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
| 86949c2b | 630 | #endif |
| 550e3dc0 WH |
631 | |
| 632 | /* | |
| 633 | * Environment | |
| 634 | */ | |
| 635 | #define CONFIG_ENV_OVERWRITE | |
| 636 | ||
| 86949c2b AW |
637 | #if defined(CONFIG_SD_BOOT) |
| 638 | #define CONFIG_ENV_OFFSET 0x100000 | |
| 639 | #define CONFIG_ENV_IS_IN_MMC | |
| 640 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
| 641 | #define CONFIG_ENV_SIZE 0x2000 | |
| d612f0ab AW |
642 | #elif defined(CONFIG_QSPI_BOOT) |
| 643 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
| 644 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ | |
| 645 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ | |
| 646 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
| 8ab967b6 AW |
647 | #elif defined(CONFIG_NAND_BOOT) |
| 648 | #define CONFIG_ENV_IS_IN_NAND | |
| 649 | #define CONFIG_ENV_SIZE 0x2000 | |
| 650 | #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) | |
| 86949c2b | 651 | #else |
| 550e3dc0 WH |
652 | #define CONFIG_ENV_IS_IN_FLASH |
| 653 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
| 654 | #define CONFIG_ENV_SIZE 0x2000 | |
| 655 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
| 86949c2b | 656 | #endif |
| 550e3dc0 WH |
657 | |
| 658 | #define CONFIG_OF_LIBFDT | |
| 659 | #define CONFIG_OF_BOARD_SETUP | |
| 6b6db0d5 | 660 | #define CONFIG_OF_STDOUT_VIA_ALIAS |
| 550e3dc0 WH |
661 | #define CONFIG_CMD_BOOTZ |
| 662 | ||
| 4ba4a095 RG |
663 | #define CONFIG_MISC_INIT_R |
| 664 | ||
| 665 | /* Hash command with SHA acceleration supported in hardware */ | |
| 666 | #define CONFIG_CMD_HASH | |
| 667 | #define CONFIG_SHA_HW_ACCEL | |
| 668 | ||
| ba474020 RG |
669 | #ifdef CONFIG_SECURE_BOOT |
| 670 | #define CONFIG_CMD_BLOB | |
| 98cb0efd | 671 | #include <asm/fsl_secure_boot.h> |
| ba474020 RG |
672 | #endif |
| 673 | ||
| 550e3dc0 | 674 | #endif |