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Commit | Line | Data |
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c8a7d9da WH |
1 | /* |
2 | * Copyright 2014 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #ifndef __CONFIG_H | |
8 | #define __CONFIG_H | |
9 | ||
aeb901f2 | 10 | #define CONFIG_ARMV7_PSCI_1_0 |
340848b1 | 11 | |
3288628a HZ |
12 | #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR |
13 | ||
18fb0e3c | 14 | #define CONFIG_SYS_FSL_CLK |
c8a7d9da | 15 | |
c8a7d9da | 16 | #define CONFIG_SKIP_LOWLEVEL_INIT |
99e1bd42 | 17 | #define CONFIG_DEEP_SLEEP |
c8a7d9da WH |
18 | |
19 | /* | |
20 | * Size of malloc() pool | |
21 | */ | |
22 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) | |
23 | ||
24 | #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR | |
25 | #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE | |
26 | ||
10a28644 RM |
27 | /* |
28 | * USB | |
29 | */ | |
30 | ||
31 | /* | |
32 | * EHCI Support - disbaled by default as | |
33 | * there is no signal coming out of soc on | |
34 | * this board for this controller. However, | |
35 | * the silicon still has this controller, | |
36 | * and anyone can use this controller by | |
37 | * taking signals out on their board. | |
38 | */ | |
39 | ||
40 | /*#define CONFIG_HAS_FSL_DR_USB*/ | |
41 | ||
42 | #ifdef CONFIG_HAS_FSL_DR_USB | |
10a28644 RM |
43 | #define CONFIG_USB_EHCI_FSL |
44 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
45 | #endif | |
46 | ||
47 | /* XHCI Support - enabled by default */ | |
48 | #define CONFIG_HAS_FSL_XHCI_USB | |
49 | ||
50 | #ifdef CONFIG_HAS_FSL_XHCI_USB | |
51 | #define CONFIG_USB_XHCI_FSL | |
10a28644 | 52 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
10a28644 RM |
53 | #endif |
54 | ||
c8a7d9da WH |
55 | #define CONFIG_SYS_CLK_FREQ 100000000 |
56 | #define CONFIG_DDR_CLK_FREQ 100000000 | |
57 | ||
a88cc3bd YS |
58 | #define DDR_SDRAM_CFG 0x470c0008 |
59 | #define DDR_CS0_BNDS 0x008000bf | |
60 | #define DDR_CS0_CONFIG 0x80014302 | |
61 | #define DDR_TIMING_CFG_0 0x50550004 | |
62 | #define DDR_TIMING_CFG_1 0xbcb38c56 | |
63 | #define DDR_TIMING_CFG_2 0x0040d120 | |
64 | #define DDR_TIMING_CFG_3 0x010e1000 | |
65 | #define DDR_TIMING_CFG_4 0x00000001 | |
66 | #define DDR_TIMING_CFG_5 0x03401400 | |
67 | #define DDR_SDRAM_CFG_2 0x00401010 | |
68 | #define DDR_SDRAM_MODE 0x00061c60 | |
69 | #define DDR_SDRAM_MODE_2 0x00180000 | |
70 | #define DDR_SDRAM_INTERVAL 0x18600618 | |
71 | #define DDR_DDR_WRLVL_CNTL 0x8655f605 | |
72 | #define DDR_DDR_WRLVL_CNTL_2 0x05060607 | |
73 | #define DDR_DDR_WRLVL_CNTL_3 0x05050505 | |
74 | #define DDR_DDR_CDR1 0x80040000 | |
75 | #define DDR_DDR_CDR2 0x00000001 | |
76 | #define DDR_SDRAM_CLK_CNTL 0x02000000 | |
77 | #define DDR_DDR_ZQ_CNTL 0x89080600 | |
78 | #define DDR_CS0_CONFIG_2 0 | |
79 | #define DDR_SDRAM_CFG_MEM_EN 0x80000000 | |
99e1bd42 TY |
80 | #define SDRAM_CFG2_D_INIT 0x00000010 |
81 | #define DDR_CDR2_VREF_TRAIN_EN 0x00000080 | |
82 | #define SDRAM_CFG2_FRC_SR 0x80000000 | |
83 | #define SDRAM_CFG_BI 0x00000001 | |
a88cc3bd | 84 | |
8415bb68 AW |
85 | #ifdef CONFIG_RAMBOOT_PBL |
86 | #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg | |
87 | #endif | |
88 | ||
89 | #ifdef CONFIG_SD_BOOT | |
947cee11 AW |
90 | #ifdef CONFIG_SD_BOOT_QSPI |
91 | #define CONFIG_SYS_FSL_PBL_RCW \ | |
92 | board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg | |
93 | #else | |
94 | #define CONFIG_SYS_FSL_PBL_RCW \ | |
95 | board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg | |
96 | #endif | |
8415bb68 | 97 | #define CONFIG_SPL_FRAMEWORK |
e7e720c2 SG |
98 | |
99 | #ifdef CONFIG_SECURE_BOOT | |
e7e720c2 SG |
100 | /* |
101 | * HDR would be appended at end of image and copied to DDR along | |
102 | * with U-Boot image. | |
103 | */ | |
693d4c9f | 104 | #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) |
e7e720c2 | 105 | #endif /* ifdef CONFIG_SECURE_BOOT */ |
8415bb68 AW |
106 | |
107 | #define CONFIG_SPL_TEXT_BASE 0x10000000 | |
108 | #define CONFIG_SPL_MAX_SIZE 0x1a000 | |
109 | #define CONFIG_SPL_STACK 0x1001d000 | |
110 | #define CONFIG_SPL_PAD_TO 0x1c000 | |
111 | #define CONFIG_SYS_TEXT_BASE 0x82000000 | |
112 | ||
99e1bd42 TY |
113 | #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ |
114 | CONFIG_SYS_MONITOR_LEN) | |
8415bb68 AW |
115 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 |
116 | #define CONFIG_SPL_BSS_START_ADDR 0x80100000 | |
117 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 | |
e7e720c2 SG |
118 | |
119 | #ifdef CONFIG_U_BOOT_HDR_SIZE | |
120 | /* | |
121 | * HDR would be appended at end of image and copied to DDR along | |
122 | * with U-Boot image. Here u-boot max. size is 512K. So if binary | |
123 | * size increases then increase this size in case of secure boot as | |
124 | * it uses raw u-boot image instead of fit image. | |
125 | */ | |
9b6639fa | 126 | #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) |
e7e720c2 | 127 | #else |
9b6639fa | 128 | #define CONFIG_SYS_MONITOR_LEN 0x100000 |
e7e720c2 | 129 | #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ |
8415bb68 AW |
130 | #endif |
131 | ||
d612f0ab | 132 | #ifdef CONFIG_QSPI_BOOT |
615bfce5 | 133 | #define CONFIG_SYS_TEXT_BASE 0x40100000 |
947cee11 AW |
134 | #endif |
135 | ||
c8a7d9da | 136 | #ifndef CONFIG_SYS_TEXT_BASE |
1c69a51c | 137 | #define CONFIG_SYS_TEXT_BASE 0x60100000 |
c8a7d9da WH |
138 | #endif |
139 | ||
140 | #define CONFIG_NR_DRAM_BANKS 1 | |
141 | #define PHYS_SDRAM 0x80000000 | |
142 | #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) | |
143 | ||
144 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL | |
145 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
146 | ||
4c59ab9c AW |
147 | #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ |
148 | !defined(CONFIG_QSPI_BOOT) | |
eaa859e7 | 149 | #define CONFIG_U_QE |
5aa03ddd | 150 | #define CONFIG_SYS_QE_FMAN_FW_IN_NOR |
eaa859e7 ZQ |
151 | #endif |
152 | ||
c8a7d9da WH |
153 | /* |
154 | * IFC Definitions | |
155 | */ | |
947cee11 | 156 | #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) |
c8a7d9da WH |
157 | #define CONFIG_FSL_IFC |
158 | #define CONFIG_SYS_FLASH_BASE 0x60000000 | |
159 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
160 | ||
161 | #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) | |
162 | #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
163 | CSPR_PORT_SIZE_16 | \ | |
164 | CSPR_MSEL_NOR | \ | |
165 | CSPR_V) | |
166 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) | |
167 | ||
168 | /* NOR Flash Timing Params */ | |
169 | #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ | |
170 | CSOR_NOR_TRHZ_80) | |
171 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ | |
172 | FTIM0_NOR_TEADC(0x5) | \ | |
173 | FTIM0_NOR_TAVDS(0x0) | \ | |
174 | FTIM0_NOR_TEAHC(0x5)) | |
175 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ | |
176 | FTIM1_NOR_TRAD_NOR(0x1A) | \ | |
177 | FTIM1_NOR_TSEQRAD_NOR(0x13)) | |
178 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ | |
179 | FTIM2_NOR_TCH(0x4) | \ | |
180 | FTIM2_NOR_TWP(0x1c) | \ | |
181 | FTIM2_NOR_TWPH(0x0e)) | |
182 | #define CONFIG_SYS_NOR_FTIM3 0 | |
183 | ||
184 | #define CONFIG_FLASH_CFI_DRIVER | |
185 | #define CONFIG_SYS_FLASH_CFI | |
186 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
187 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
188 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
189 | ||
190 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
191 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
192 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
193 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
194 | ||
195 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
196 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } | |
197 | ||
198 | #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS | |
272c5265 | 199 | #define CONFIG_SYS_WRITE_SWAPPED_DATA |
d612f0ab | 200 | #endif |
c8a7d9da WH |
201 | |
202 | /* CPLD */ | |
203 | ||
204 | #define CONFIG_SYS_CPLD_BASE 0x7fb00000 | |
205 | #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE | |
206 | ||
207 | #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) | |
208 | #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ | |
209 | CSPR_PORT_SIZE_8 | \ | |
210 | CSPR_MSEL_GPCM | \ | |
211 | CSPR_V) | |
212 | #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) | |
213 | #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ | |
214 | CSOR_NOR_NOR_MODE_AVD_NOR | \ | |
215 | CSOR_NOR_TRHZ_80) | |
216 | ||
217 | /* CPLD Timing parameters for IFC GPCM */ | |
218 | #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ | |
219 | FTIM0_GPCM_TEADC(0xf) | \ | |
220 | FTIM0_GPCM_TEAHC(0xf)) | |
221 | #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ | |
222 | FTIM1_GPCM_TRAD(0x3f)) | |
223 | #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ | |
224 | FTIM2_GPCM_TCH(0xf) | \ | |
225 | FTIM2_GPCM_TWP(0xff)) | |
226 | #define CONFIG_SYS_FPGA_FTIM3 0x0 | |
227 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
228 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR | |
229 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
230 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
231 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
232 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
233 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
234 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
235 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT | |
236 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR | |
237 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK | |
238 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR | |
239 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0 | |
240 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1 | |
241 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2 | |
242 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3 | |
243 | ||
244 | /* | |
245 | * Serial Port | |
246 | */ | |
55d53ab4 | 247 | #ifdef CONFIG_LPUART |
55d53ab4 AW |
248 | #define CONFIG_LPUART_32B_REG |
249 | #else | |
c8a7d9da | 250 | #define CONFIG_CONS_INDEX 1 |
c8a7d9da | 251 | #define CONFIG_SYS_NS16550_SERIAL |
f833cd62 | 252 | #ifndef CONFIG_DM_SERIAL |
c8a7d9da | 253 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
f833cd62 | 254 | #endif |
c8a7d9da | 255 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() |
55d53ab4 | 256 | #endif |
c8a7d9da | 257 | |
c8a7d9da WH |
258 | /* |
259 | * I2C | |
260 | */ | |
c8a7d9da WH |
261 | #define CONFIG_SYS_I2C |
262 | #define CONFIG_SYS_I2C_MXC | |
03544c66 AA |
263 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
264 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ | |
f8cb101e | 265 | #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ |
c8a7d9da | 266 | |
5175a288 | 267 | /* EEPROM */ |
5175a288 AW |
268 | #define CONFIG_ID_EEPROM |
269 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
270 | #define CONFIG_SYS_EEPROM_BUS_NUM 1 | |
271 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 | |
272 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
273 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
274 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 | |
5175a288 | 275 | |
c8a7d9da WH |
276 | /* |
277 | * MMC | |
278 | */ | |
c8a7d9da | 279 | #define CONFIG_FSL_ESDHC |
c8a7d9da | 280 | |
9dd3d3c0 | 281 | /* SPI */ |
947cee11 | 282 | #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) |
9dd3d3c0 | 283 | /* QSPI */ |
d612f0ab AW |
284 | #define QSPI0_AMBA_BASE 0x40000000 |
285 | #define FSL_QSPI_FLASH_SIZE (1 << 24) | |
286 | #define FSL_QSPI_FLASH_NUM 2 | |
287 | ||
03d1d568 | 288 | /* DSPI */ |
03d1d568 YY |
289 | #endif |
290 | ||
9dd3d3c0 HW |
291 | /* DM SPI */ |
292 | #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) | |
9dd3d3c0 HW |
293 | #define CONFIG_DM_SPI_FLASH |
294 | #endif | |
d612f0ab | 295 | |
b4ecc8c6 WH |
296 | /* |
297 | * Video | |
298 | */ | |
b215fb3f | 299 | #ifdef CONFIG_VIDEO_FSL_DCU_FB |
b4ecc8c6 WH |
300 | #define CONFIG_VIDEO_LOGO |
301 | #define CONFIG_VIDEO_BMP_LOGO | |
302 | ||
303 | #define CONFIG_FSL_DCU_SII9022A | |
304 | #define CONFIG_SYS_I2C_DVI_BUS_NUM 1 | |
305 | #define CONFIG_SYS_I2C_DVI_ADDR 0x39 | |
306 | #endif | |
307 | ||
c8a7d9da WH |
308 | /* |
309 | * eTSEC | |
310 | */ | |
311 | #define CONFIG_TSEC_ENET | |
312 | ||
313 | #ifdef CONFIG_TSEC_ENET | |
314 | #define CONFIG_MII | |
315 | #define CONFIG_MII_DEFAULT_TSEC 1 | |
316 | #define CONFIG_TSEC1 1 | |
317 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
318 | #define CONFIG_TSEC2 1 | |
319 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
320 | #define CONFIG_TSEC3 1 | |
321 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
322 | ||
323 | #define TSEC1_PHY_ADDR 2 | |
324 | #define TSEC2_PHY_ADDR 0 | |
325 | #define TSEC3_PHY_ADDR 1 | |
326 | ||
327 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
328 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
329 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
330 | ||
331 | #define TSEC1_PHYIDX 0 | |
332 | #define TSEC2_PHYIDX 0 | |
333 | #define TSEC3_PHYIDX 0 | |
334 | ||
335 | #define CONFIG_ETHPRIME "eTSEC1" | |
336 | ||
c8a7d9da WH |
337 | #define CONFIG_PHY_ATHEROS |
338 | ||
339 | #define CONFIG_HAS_ETH0 | |
340 | #define CONFIG_HAS_ETH1 | |
341 | #define CONFIG_HAS_ETH2 | |
342 | #endif | |
343 | ||
da419027 | 344 | /* PCIe */ |
b38eaec5 RD |
345 | #define CONFIG_PCIE1 /* PCIE controller 1 */ |
346 | #define CONFIG_PCIE2 /* PCIE controller 2 */ | |
da419027 | 347 | |
180b8688 | 348 | #ifdef CONFIG_PCI |
180b8688 | 349 | #define CONFIG_PCI_SCAN_SHOW |
180b8688 ML |
350 | #endif |
351 | ||
c8a7d9da | 352 | #define CONFIG_CMDLINE_TAG |
8415bb68 | 353 | |
1a2826f6 | 354 | #define CONFIG_PEN_ADDR_BIG_ENDIAN |
435acd83 | 355 | #define CONFIG_LAYERSCAPE_NS_ACCESS |
1a2826f6 | 356 | #define CONFIG_SMP_PEN_ADDR 0x01ee0200 |
e4916e85 | 357 | #define COUNTER_FREQUENCY 12500000 |
1a2826f6 | 358 | |
c8a7d9da | 359 | #define CONFIG_HWCONFIG |
03c22449 ZZ |
360 | #define HWCONFIG_BUFFER_SIZE 256 |
361 | ||
362 | #define CONFIG_FSL_DEVICE_DISABLE | |
c8a7d9da | 363 | |
a65d7408 AW |
364 | #include <config_distro_defaults.h> |
365 | #define BOOT_TARGET_DEVICES(func) \ | |
366 | func(MMC, mmc, 0) \ | |
367 | func(USB, usb, 0) | |
368 | #include <config_distro_bootcmd.h> | |
c8a7d9da | 369 | |
55d53ab4 AW |
370 | #ifdef CONFIG_LPUART |
371 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
372 | "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ | |
7ff7166c | 373 | "initrd_high=0xffffffff\0" \ |
a65d7408 AW |
374 | "fdt_high=0xffffffff\0" \ |
375 | "fdt_addr=0x64f00000\0" \ | |
376 | "kernel_addr=0x65000000\0" \ | |
377 | "scriptaddr=0x80000000\0" \ | |
b8ae6798 | 378 | "scripthdraddr=0x80080000\0" \ |
a65d7408 AW |
379 | "fdtheader_addr_r=0x80100000\0" \ |
380 | "kernelheader_addr_r=0x80200000\0" \ | |
381 | "kernel_addr_r=0x81000000\0" \ | |
382 | "fdt_addr_r=0x90000000\0" \ | |
383 | "ramdisk_addr_r=0xa0000000\0" \ | |
384 | "load_addr=0xa0000000\0" \ | |
385 | "kernel_size=0x2800000\0" \ | |
386 | BOOTENV \ | |
387 | "boot_scripts=ls1021atwr_boot.scr\0" \ | |
b8ae6798 | 388 | "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \ |
a65d7408 AW |
389 | "scan_dev_for_boot_part=" \ |
390 | "part list ${devtype} ${devnum} devplist; " \ | |
391 | "env exists devplist || setenv devplist 1; " \ | |
392 | "for distro_bootpart in ${devplist}; do " \ | |
393 | "if fstype ${devtype} " \ | |
394 | "${devnum}:${distro_bootpart} " \ | |
395 | "bootfstype; then " \ | |
396 | "run scan_dev_for_boot; " \ | |
397 | "fi; " \ | |
398 | "done\0" \ | |
b8ae6798 SG |
399 | "scan_dev_for_boot=" \ |
400 | "echo Scanning ${devtype} " \ | |
401 | "${devnum}:${distro_bootpart}...; " \ | |
402 | "for prefix in ${boot_prefixes}; do " \ | |
403 | "run scan_dev_for_scripts; " \ | |
404 | "done;" \ | |
405 | "\0" \ | |
406 | "boot_a_script=" \ | |
407 | "load ${devtype} ${devnum}:${distro_bootpart} " \ | |
408 | "${scriptaddr} ${prefix}${script}; " \ | |
409 | "env exists secureboot && load ${devtype} " \ | |
410 | "${devnum}:${distro_bootpart} " \ | |
411 | "${scripthdraddr} ${prefix}${boot_script_hdr} " \ | |
412 | "&& esbc_validate ${scripthdraddr};" \ | |
413 | "source ${scriptaddr}\0" \ | |
a65d7408 AW |
414 | "installer=load mmc 0:2 $load_addr " \ |
415 | "/flex_installer_arm32.itb; " \ | |
416 | "bootm $load_addr#ls1021atwr\0" \ | |
417 | "qspi_bootcmd=echo Trying load from qspi..;" \ | |
418 | "sf probe && sf read $load_addr " \ | |
419 | "$kernel_addr $kernel_size && bootm $load_addr#$board\0" \ | |
420 | "nor_bootcmd=echo Trying load from nor..;" \ | |
421 | "cp.b $kernel_addr $load_addr " \ | |
422 | "$kernel_size && bootm $load_addr#$board\0" | |
55d53ab4 | 423 | #else |
c8a7d9da WH |
424 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
425 | "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ | |
7ff7166c | 426 | "initrd_high=0xffffffff\0" \ |
a65d7408 AW |
427 | "fdt_high=0xffffffff\0" \ |
428 | "fdt_addr=0x64f00000\0" \ | |
429 | "kernel_addr=0x65000000\0" \ | |
430 | "scriptaddr=0x80000000\0" \ | |
b8ae6798 | 431 | "scripthdraddr=0x80080000\0" \ |
a65d7408 AW |
432 | "fdtheader_addr_r=0x80100000\0" \ |
433 | "kernelheader_addr_r=0x80200000\0" \ | |
434 | "kernel_addr_r=0x81000000\0" \ | |
435 | "fdt_addr_r=0x90000000\0" \ | |
436 | "ramdisk_addr_r=0xa0000000\0" \ | |
437 | "load_addr=0xa0000000\0" \ | |
438 | "kernel_size=0x2800000\0" \ | |
439 | BOOTENV \ | |
440 | "boot_scripts=ls1021atwr_boot.scr\0" \ | |
b8ae6798 | 441 | "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \ |
a65d7408 AW |
442 | "scan_dev_for_boot_part=" \ |
443 | "part list ${devtype} ${devnum} devplist; " \ | |
444 | "env exists devplist || setenv devplist 1; " \ | |
445 | "for distro_bootpart in ${devplist}; do " \ | |
446 | "if fstype ${devtype} " \ | |
447 | "${devnum}:${distro_bootpart} " \ | |
448 | "bootfstype; then " \ | |
449 | "run scan_dev_for_boot; " \ | |
450 | "fi; " \ | |
451 | "done\0" \ | |
b8ae6798 SG |
452 | "scan_dev_for_boot=" \ |
453 | "echo Scanning ${devtype} " \ | |
454 | "${devnum}:${distro_bootpart}...; " \ | |
455 | "for prefix in ${boot_prefixes}; do " \ | |
456 | "run scan_dev_for_scripts; " \ | |
457 | "done;" \ | |
458 | "\0" \ | |
459 | "boot_a_script=" \ | |
460 | "load ${devtype} ${devnum}:${distro_bootpart} " \ | |
461 | "${scriptaddr} ${prefix}${script}; " \ | |
462 | "env exists secureboot && load ${devtype} " \ | |
463 | "${devnum}:${distro_bootpart} " \ | |
464 | "${scripthdraddr} ${prefix}${boot_script_hdr} " \ | |
465 | "&& esbc_validate ${scripthdraddr};" \ | |
466 | "source ${scriptaddr}\0" \ | |
a65d7408 AW |
467 | "installer=load mmc 0:2 $load_addr " \ |
468 | "/flex_installer_arm32.itb; " \ | |
469 | "bootm $load_addr#ls1021atwr\0" \ | |
470 | "qspi_bootcmd=echo Trying load from qspi..;" \ | |
471 | "sf probe && sf read $load_addr " \ | |
472 | "$kernel_addr $kernel_size && bootm $load_addr#$board\0" \ | |
473 | "nor_bootcmd=echo Trying load from nor..;" \ | |
474 | "cp.b $kernel_addr $load_addr " \ | |
475 | "$kernel_size && bootm $load_addr#$board\0" | |
55d53ab4 | 476 | #endif |
c8a7d9da | 477 | |
a65d7408 AW |
478 | #undef CONFIG_BOOTCOMMAND |
479 | #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) | |
b8ae6798 SG |
480 | #define CONFIG_BOOTCOMMAND "run distro_bootcmd; env exists secureboot" \ |
481 | "&& esbc_halt; run qspi_bootcmd;" | |
a65d7408 | 482 | #else |
b8ae6798 SG |
483 | #define CONFIG_BOOTCOMMAND "run distro_bootcmd; env exists secureboot" \ |
484 | "&& esbc_halt; run nor_bootcmd;" | |
a65d7408 AW |
485 | #endif |
486 | ||
c8a7d9da WH |
487 | /* |
488 | * Miscellaneous configurable options | |
489 | */ | |
490 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
c8a7d9da | 491 | #define CONFIG_AUTO_COMPLETE |
c8a7d9da WH |
492 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
493 | ||
c8a7d9da WH |
494 | #define CONFIG_SYS_MEMTEST_START 0x80000000 |
495 | #define CONFIG_SYS_MEMTEST_END 0x9fffffff | |
496 | ||
497 | #define CONFIG_SYS_LOAD_ADDR 0x82000000 | |
c8a7d9da | 498 | |
660673af XL |
499 | #define CONFIG_LS102XA_STREAM_ID |
500 | ||
c8a7d9da WH |
501 | #define CONFIG_SYS_INIT_SP_OFFSET \ |
502 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
503 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
504 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
505 | ||
8415bb68 AW |
506 | #ifdef CONFIG_SPL_BUILD |
507 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE | |
508 | #else | |
c8a7d9da | 509 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
8415bb68 | 510 | #endif |
c8a7d9da | 511 | |
615bfce5 | 512 | #define CONFIG_SYS_QE_FW_ADDR 0x60940000 |
eaa859e7 | 513 | |
c8a7d9da WH |
514 | /* |
515 | * Environment | |
516 | */ | |
517 | #define CONFIG_ENV_OVERWRITE | |
518 | ||
8415bb68 | 519 | #if defined(CONFIG_SD_BOOT) |
615bfce5 | 520 | #define CONFIG_ENV_OFFSET 0x300000 |
8415bb68 AW |
521 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
522 | #define CONFIG_ENV_SIZE 0x20000 | |
d612f0ab | 523 | #elif defined(CONFIG_QSPI_BOOT) |
d612f0ab | 524 | #define CONFIG_ENV_SIZE 0x2000 |
615bfce5 | 525 | #define CONFIG_ENV_OFFSET 0x300000 |
d612f0ab | 526 | #define CONFIG_ENV_SECT_SIZE 0x10000 |
8415bb68 | 527 | #else |
615bfce5 | 528 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) |
c8a7d9da WH |
529 | #define CONFIG_ENV_SIZE 0x20000 |
530 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
8415bb68 | 531 | #endif |
c8a7d9da | 532 | |
4ba4a095 RG |
533 | #define CONFIG_MISC_INIT_R |
534 | ||
ef6c55a2 | 535 | #include <asm/fsl_secure_boot.h> |
cc7b8b9a | 536 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
4ba4a095 | 537 | |
c8a7d9da | 538 | #endif |