projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| f3a8e2b7 MH |
1 | /* |
| 2 | * Copyright (C) 2015 Freescale Semiconductor | |
| 3 | * | |
| 4 | * SPDX-License-Identifier: GPL-2.0+ | |
| 5 | */ | |
| 6 | ||
| 7 | #ifndef __LS1043A_COMMON_H | |
| 8 | #define __LS1043A_COMMON_H | |
| 9 | ||
| 4139b170 SG |
10 | /* SPL build */ |
| 11 | #ifdef CONFIG_SPL_BUILD | |
| 12 | #define SPL_NO_FMAN | |
| 13 | #define SPL_NO_DSPI | |
| 14 | #define SPL_NO_PCIE | |
| 15 | #define SPL_NO_ENV | |
| 16 | #define SPL_NO_MISC | |
| 17 | #define SPL_NO_USB | |
| 18 | #define SPL_NO_SATA | |
| 19 | #define SPL_NO_QE | |
| 20 | #define SPL_NO_EEPROM | |
| 21 | #endif | |
| 22 | #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT)) | |
| 23 | #define SPL_NO_MMC | |
| 24 | #endif | |
| 25 | #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT)) | |
| 26 | #define SPL_NO_IFC | |
| 27 | #endif | |
| 28 | ||
| f3a8e2b7 MH |
29 | #define CONFIG_REMAKE_ELF |
| 30 | #define CONFIG_FSL_LAYERSCAPE | |
| 831c068f | 31 | #define CONFIG_MP |
| f3a8e2b7 MH |
32 | #define CONFIG_GICV2 |
| 33 | ||
| 5344c7b7 | 34 | #include <asm/arch/stream_id_lsch2.h> |
| f3a8e2b7 | 35 | #include <asm/arch/config.h> |
| f3a8e2b7 MH |
36 | |
| 37 | /* Link Definitions */ | |
| 38 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) | |
| 39 | ||
| 40 | #define CONFIG_SUPPORT_RAW_INITRD | |
| 41 | ||
| 42 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
| f3a8e2b7 | 43 | |
| f3a8e2b7 MH |
44 | #define CONFIG_VERY_BIG_RAM |
| 45 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 | |
| 46 | #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 | |
| 47 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
| e994dddb | 48 | #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL |
| f3a8e2b7 | 49 | |
| 831c068f HZ |
50 | #define CPU_RELEASE_ADDR secondary_boot_func |
| 51 | ||
| f3a8e2b7 MH |
52 | /* Generic Timer Definitions */ |
| 53 | #define COUNTER_FREQUENCY 25000000 /* 25MHz */ | |
| 54 | ||
| 55 | /* Size of malloc() pool */ | |
| 56 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) | |
| 57 | ||
| 58 | /* Serial Port */ | |
| 59 | #define CONFIG_CONS_INDEX 1 | |
| f3a8e2b7 MH |
60 | #define CONFIG_SYS_NS16550_SERIAL |
| 61 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 904110c7 | 62 | #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) |
| f3a8e2b7 | 63 | |
| f3a8e2b7 MH |
64 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
| 65 | ||
| c7ca8b07 GQ |
66 | /* SD boot SPL */ |
| 67 | #ifdef CONFIG_SD_BOOT | |
| 68 | #define CONFIG_SPL_FRAMEWORK | |
| 69 | #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" | |
| 70 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
| c7ca8b07 GQ |
71 | |
| 72 | #define CONFIG_SPL_TEXT_BASE 0x10000000 | |
| 70f9661c | 73 | #define CONFIG_SPL_MAX_SIZE 0x17000 |
| c7ca8b07 GQ |
74 | #define CONFIG_SPL_STACK 0x1001e000 |
| 75 | #define CONFIG_SPL_PAD_TO 0x1d000 | |
| 76 | ||
| 77 | #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ | |
| 78 | CONFIG_SYS_MONITOR_LEN) | |
| 79 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 | |
| 80 | #define CONFIG_SPL_BSS_START_ADDR 0x80100000 | |
| 81 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 | |
| 70f9661c RG |
82 | |
| 83 | #ifdef CONFIG_SECURE_BOOT | |
| 84 | #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) | |
| 85 | /* | |
| 86 | * HDR would be appended at end of image and copied to DDR along | |
| 87 | * with U-Boot image. Here u-boot max. size is 512K. So if binary | |
| 88 | * size increases then increase this size in case of secure boot as | |
| 89 | * it uses raw u-boot image instead of fit image. | |
| 90 | */ | |
| 91 | #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) | |
| 92 | #else | |
| 93 | #define CONFIG_SYS_MONITOR_LEN 0x100000 | |
| 94 | #endif /* ifdef CONFIG_SECURE_BOOT */ | |
| c7ca8b07 GQ |
95 | #endif |
| 96 | ||
| 3ad44729 GQ |
97 | /* NAND SPL */ |
| 98 | #ifdef CONFIG_NAND_BOOT | |
| 99 | #define CONFIG_SPL_PBL_PAD | |
| 100 | #define CONFIG_SPL_FRAMEWORK | |
| 101 | #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" | |
| 102 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
| 3ad44729 GQ |
103 | #define CONFIG_SPL_TEXT_BASE 0x10000000 |
| 104 | #define CONFIG_SPL_MAX_SIZE 0x1a000 | |
| 105 | #define CONFIG_SPL_STACK 0x1001d000 | |
| 106 | #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE | |
| 107 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE | |
| 108 | #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 | |
| 109 | #define CONFIG_SPL_BSS_START_ADDR 0x80100000 | |
| 110 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 | |
| 111 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 | |
| 762f92a6 RG |
112 | |
| 113 | #ifdef CONFIG_SECURE_BOOT | |
| 114 | #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) | |
| 115 | #endif /* ifdef CONFIG_SECURE_BOOT */ | |
| 116 | ||
| 117 | #ifdef CONFIG_U_BOOT_HDR_SIZE | |
| 118 | /* | |
| 119 | * HDR would be appended at end of image and copied to DDR along | |
| 120 | * with U-Boot image. Here u-boot max. size is 512K. So if binary | |
| 121 | * size increases then increase this size in case of secure boot as | |
| 122 | * it uses raw u-boot image instead of fit image. | |
| 123 | */ | |
| 124 | #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) | |
| 125 | #else | |
| 126 | #define CONFIG_SYS_MONITOR_LEN 0x100000 | |
| 127 | #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ | |
| 128 | ||
| 3ad44729 GQ |
129 | #endif |
| 130 | ||
| f3a8e2b7 | 131 | /* IFC */ |
| 4139b170 | 132 | #ifndef SPL_NO_IFC |
| b0f20caf | 133 | #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) |
| f3a8e2b7 MH |
134 | #define CONFIG_FSL_IFC |
| 135 | /* | |
| 136 | * CONFIG_SYS_FLASH_BASE has the final address (core view) | |
| 137 | * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) | |
| 138 | * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address | |
| 139 | * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting | |
| 140 | */ | |
| 141 | #define CONFIG_SYS_FLASH_BASE 0x60000000 | |
| 142 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
| 143 | #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 | |
| 144 | ||
| e856bdcf | 145 | #ifdef CONFIG_MTD_NOR_FLASH |
| f3a8e2b7 MH |
146 | #define CONFIG_FLASH_CFI_DRIVER |
| 147 | #define CONFIG_SYS_FLASH_CFI | |
| 148 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
| 149 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
| 150 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
| 151 | #endif | |
| 166ef1e9 | 152 | #endif |
| 4139b170 | 153 | #endif |
| f3a8e2b7 MH |
154 | |
| 155 | /* I2C */ | |
| f3a8e2b7 MH |
156 | #define CONFIG_SYS_I2C |
| 157 | #define CONFIG_SYS_I2C_MXC | |
| 158 | #define CONFIG_SYS_I2C_MXC_I2C1 | |
| 159 | #define CONFIG_SYS_I2C_MXC_I2C2 | |
| 160 | #define CONFIG_SYS_I2C_MXC_I2C3 | |
| 161 | #define CONFIG_SYS_I2C_MXC_I2C4 | |
| 162 | ||
| 163 | /* PCIe */ | |
| 4139b170 | 164 | #ifndef SPL_NO_PCIE |
| f3a8e2b7 MH |
165 | #define CONFIG_PCIE1 /* PCIE controller 1 */ |
| 166 | #define CONFIG_PCIE2 /* PCIE controller 2 */ | |
| 167 | #define CONFIG_PCIE3 /* PCIE controller 3 */ | |
| f3a8e2b7 | 168 | |
| f3a8e2b7 MH |
169 | #ifdef CONFIG_PCI |
| 170 | #define CONFIG_NET_MULTI | |
| f3a8e2b7 MH |
171 | #define CONFIG_PCI_SCAN_SHOW |
| 172 | #define CONFIG_CMD_PCI | |
| 173 | #endif | |
| 4139b170 | 174 | #endif |
| f3a8e2b7 MH |
175 | |
| 176 | /* Command line configuration */ | |
| 4139b170 | 177 | #ifndef SPL_NO_ENV |
| f3a8e2b7 | 178 | #define CONFIG_CMD_ENV |
| 4139b170 | 179 | #endif |
| f3a8e2b7 | 180 | |
| 8ef0d5c4 | 181 | /* MMC */ |
| 4139b170 | 182 | #ifndef SPL_NO_MMC |
| 8ef0d5c4 | 183 | #ifdef CONFIG_MMC |
| 8ef0d5c4 YL |
184 | #define CONFIG_FSL_ESDHC |
| 185 | #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 | |
| 8ef0d5c4 | 186 | #endif |
| 4139b170 | 187 | #endif |
| 8ef0d5c4 | 188 | |
| e0579a58 | 189 | /* DSPI */ |
| 4139b170 | 190 | #ifndef SPL_NO_DSPI |
| e0579a58 GQ |
191 | #define CONFIG_FSL_DSPI |
| 192 | #ifdef CONFIG_FSL_DSPI | |
| e0579a58 GQ |
193 | #define CONFIG_DM_SPI_FLASH |
| 194 | #define CONFIG_SPI_FLASH_STMICRO /* cs0 */ | |
| 195 | #define CONFIG_SPI_FLASH_SST /* cs1 */ | |
| 196 | #define CONFIG_SPI_FLASH_EON /* cs2 */ | |
| b0f20caf | 197 | #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) |
| e0579a58 GQ |
198 | #define CONFIG_SF_DEFAULT_BUS 1 |
| 199 | #define CONFIG_SF_DEFAULT_CS 0 | |
| 200 | #endif | |
| 166ef1e9 | 201 | #endif |
| 4139b170 | 202 | #endif |
| e0579a58 | 203 | |
| e8297341 | 204 | /* FMan ucode */ |
| 4139b170 | 205 | #ifndef SPL_NO_FMAN |
| e8297341 SX |
206 | #define CONFIG_SYS_DPAA_FMAN |
| 207 | #ifdef CONFIG_SYS_DPAA_FMAN | |
| 208 | #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 | |
| 209 | ||
| fd1b147c QG |
210 | #ifdef CONFIG_NAND_BOOT |
| 211 | /* Store Fman ucode at offeset 0x160000(11 blocks). */ | |
| 212 | #define CONFIG_SYS_QE_FMAN_FW_IN_NAND | |
| 213 | #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) | |
| 2a555839 QG |
214 | #elif defined(CONFIG_SD_BOOT) |
| 215 | /* | |
| 216 | * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is | |
| 217 | * about 1MB (2040 blocks), Env is stored after the image, and the env size is | |
| 218 | * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 2080(0x820). | |
| 219 | */ | |
| 220 | #define CONFIG_SYS_QE_FMAN_FW_IN_MMC | |
| 221 | #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) | |
| 222 | #elif defined(CONFIG_QSPI_BOOT) | |
| 166ef1e9 GQ |
223 | #define CONFIG_SYS_QE_FW_IN_SPIFLASH |
| 224 | #define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 | |
| 225 | #define CONFIG_ENV_SPI_BUS 0 | |
| 226 | #define CONFIG_ENV_SPI_CS 0 | |
| 227 | #define CONFIG_ENV_SPI_MAX_HZ 1000000 | |
| 228 | #define CONFIG_ENV_SPI_MODE 0x03 | |
| 229 | #else | |
| e8297341 SX |
230 | #define CONFIG_SYS_QE_FMAN_FW_IN_NOR |
| 231 | /* FMan fireware Pre-load address */ | |
| 232 | #define CONFIG_SYS_FMAN_FW_ADDR 0x60300000 | |
| 166ef1e9 | 233 | #endif |
| e8297341 SX |
234 | #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 |
| 235 | #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) | |
| 236 | #endif | |
| 4139b170 | 237 | #endif |
| e8297341 | 238 | |
| f3a8e2b7 MH |
239 | /* Miscellaneous configurable options */ |
| 240 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) | |
| f3a8e2b7 MH |
241 | |
| 242 | #define CONFIG_HWCONFIG | |
| 243 | #define HWCONFIG_BUFFER_SIZE 128 | |
| 244 | ||
| 4139b170 | 245 | #ifndef SPL_NO_MISC |
| dbe18f16 WS |
246 | #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) |
| 247 | #define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \ | |
| 248 | "5m(kernel),1m(dtb),9m(file_system)" | |
| 249 | #else | |
| 7f339632 WS |
250 | #define MTDPARTS_DEFAULT "mtdparts=60000000.nor:" \ |
| 251 | "2m@0x100000(nor_bank0_uboot),"\ | |
| 252 | "40m@0x1100000(nor_bank0_fit)," \ | |
| 253 | "7m(nor_bank0_user)," \ | |
| 254 | "2m@0x4100000(nor_bank4_uboot)," \ | |
| 255 | "40m@0x5100000(nor_bank4_fit),"\ | |
| 256 | "-(nor_bank4_user);" \ | |
| 257 | "7e800000.flash:" \ | |
| dbe18f16 WS |
258 | "1m(nand_uboot),1m(nand_uboot_env)," \ |
| 259 | "20m(nand_fit);spi0.0:1m(uboot)," \ | |
| 260 | "5m(kernel),1m(dtb),9m(file_system)" | |
| 261 | #endif | |
| 262 | ||
| f3a8e2b7 MH |
263 | /* Initial environment variables */ |
| 264 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 265 | "hwconfig=fsl_ddr:bank_intlv=auto\0" \ | |
| 266 | "loadaddr=0x80100000\0" \ | |
| f3a8e2b7 MH |
267 | "fdt_high=0xffffffffffffffff\0" \ |
| 268 | "initrd_high=0xffffffffffffffff\0" \ | |
| ad6767b6 QG |
269 | "kernel_start=0x61100000\0" \ |
| 270 | "kernel_load=0xa0000000\0" \ | |
| 271 | "kernel_size=0x2800000\0" \ | |
| dbe18f16 WS |
272 | "console=ttyS0,115200\0" \ |
| 273 | "mtdparts=" MTDPARTS_DEFAULT "\0" | |
| f3a8e2b7 MH |
274 | |
| 275 | #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ | |
| dbe18f16 WS |
276 | "earlycon=uart8250,mmio,0x21c0500 " \ |
| 277 | MTDPARTS_DEFAULT | |
| 278 | ||
| 1297cdb4 QG |
279 | #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) |
| 280 | #define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \ | |
| 281 | "e0000 f00000 && bootm $kernel_load" | |
| 282 | #else | |
| f3a8e2b7 MH |
283 | #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ |
| 284 | "$kernel_size && bootm $kernel_load" | |
| 1297cdb4 | 285 | #endif |
| 4139b170 | 286 | #endif |
| f3a8e2b7 MH |
287 | |
| 288 | /* Monitor Command Prompt */ | |
| 289 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ | |
| f3a8e2b7 MH |
290 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
| 291 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
| f3a8e2b7 MH |
292 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ |
| 293 | #define CONFIG_SYS_LONGHELP | |
| 4139b170 SG |
294 | |
| 295 | #ifndef SPL_NO_MISC | |
| f3a8e2b7 | 296 | #define CONFIG_CMDLINE_EDITING 1 |
| 4139b170 SG |
297 | #endif |
| 298 | ||
| f3a8e2b7 MH |
299 | #define CONFIG_AUTO_COMPLETE |
| 300 | #define CONFIG_SYS_MAXARGS 64 /* max command args */ | |
| 301 | ||
| 302 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
| 303 | ||
| ef6c55a2 AB |
304 | /* Hash command with SHA acceleration supported in hardware */ |
| 305 | #ifdef CONFIG_FSL_CAAM | |
| 306 | #define CONFIG_CMD_HASH | |
| ef6c55a2 AB |
307 | #endif |
| 308 | ||
| f3a8e2b7 | 309 | #endif /* __LS1043A_COMMON_H */ |