]>
Commit | Line | Data |
---|---|---|
53d4a498 BS |
1 | /* |
2 | * (C) Copyright 2003-2007 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
0ffb941c | 5 | * Based on Motion-PRO board config file by Robert McCullough, rob@promessinc.com |
53d4a498 | 6 | * |
3765b3e7 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
53d4a498 BS |
8 | */ |
9 | ||
10 | #ifndef __CONFIG_H | |
11 | #define __CONFIG_H | |
12 | ||
53d4a498 BS |
13 | /* |
14 | * High Level Configuration Options | |
15 | */ | |
16 | ||
53d4a498 | 17 | /* CPU and board */ |
b2a6dfe4 | 18 | #define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */ |
53d4a498 BS |
19 | #define CONFIG_MOTIONPRO 1 /* ... on Promess Motion-PRO board */ |
20 | ||
31d82672 | 21 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
53d4a498 | 22 | |
2ae18241 WD |
23 | #define CONFIG_SYS_TEXT_BASE 0xfff00000 |
24 | ||
079a136c JL |
25 | /* |
26 | * BOOTP options | |
27 | */ | |
28 | #define CONFIG_BOOTP_BOOTFILESIZE | |
29 | #define CONFIG_BOOTP_BOOTPATH | |
30 | #define CONFIG_BOOTP_GATEWAY | |
31 | #define CONFIG_BOOTP_HOSTNAME | |
32 | ||
53d4a498 | 33 | /* |
5dc11a51 | 34 | * Command line configuration. |
53d4a498 | 35 | */ |
7a8ddeea WD |
36 | #define CONFIG_CMD_BEDBUG |
37 | #define CONFIG_CMD_DATE | |
7a8ddeea WD |
38 | #define CONFIG_CMD_DTT |
39 | #define CONFIG_CMD_EEPROM | |
7a8ddeea WD |
40 | #define CONFIG_CMD_IDE |
41 | #define CONFIG_CMD_IMMAP | |
42 | #define CONFIG_CMD_JFFS2 | |
7a8ddeea | 43 | #define CONFIG_CMD_REGINFO |
53d4a498 BS |
44 | |
45 | /* | |
46 | * Serial console configuration | |
47 | */ | |
48 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ | |
49 | #define CONFIG_NETCONSOLE 1 /* network console */ | |
50 | #define CONFIG_BAUDRATE 115200 | |
6d0f6bcf | 51 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
53d4a498 | 52 | |
53d4a498 BS |
53 | /* |
54 | * Ethernet configuration | |
55 | */ | |
56 | #define CONFIG_MPC5xxx_FEC 1 | |
86321fc1 | 57 | #define CONFIG_MPC5xxx_FEC_MII100 |
53d4a498 BS |
58 | #define CONFIG_PHY_ADDR 0x2 |
59 | #define CONFIG_PHY_TYPE 0x79c874 | |
c00125e0 | 60 | #define CONFIG_RESET_PHY_R 1 |
53d4a498 BS |
61 | |
62 | /* | |
63 | * Autobooting | |
64 | */ | |
53d4a498 | 65 | #undef CONFIG_BOOTARGS |
53d4a498 | 66 | |
7a8ddeea | 67 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
7a8ddeea | 68 | |
53d4a498 BS |
69 | /* |
70 | * Default environment settings | |
71 | */ | |
72 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
53d4a498 BS |
73 | "netdev=eth0\0" \ |
74 | "hostname=motionpro\0" \ | |
0ffb941c WG |
75 | "netmask=255.255.255.0\0" \ |
76 | "ipaddr=192.168.1.106\0" \ | |
77 | "serverip=192.168.1.100\0" \ | |
78 | "gatewayip=192.168.1.100\0" \ | |
1f1369c3 | 79 | "console=ttyPSC0,115200\0" \ |
7a8ddeea WD |
80 | "u-boot_addr=400000\0" \ |
81 | "kernel_addr=400000\0" \ | |
82 | "fdt_addr=700000\0" \ | |
83 | "ramdisk_addr=800000\0" \ | |
fa5c2ba1 | 84 | "multi_image_addr=800000\0" \ |
0ffb941c WG |
85 | "rootpath=/opt/eldk-4.2/ppc_6xx\0" \ |
86 | "u-boot=/tftpboot/motionpro/u-boot.bin\0" \ | |
87 | "bootfile=/tftpboot/motionpro/uImage\0" \ | |
88 | "fdt_file=/tftpboot/motionpro/motionpro.dtb\0" \ | |
89 | "ramdisk_file=/tftpboot/motionpro/uRamdisk\0" \ | |
fa5c2ba1 | 90 | "multi_image_file=kernel+initrd+dtb.img\0" \ |
7049288f | 91 | "load=tftp ${u-boot_addr} ${u-boot}\0" \ |
7a8ddeea WD |
92 | "update=prot off fff00000 +${filesize};" \ |
93 | "era fff00000 +${filesize}; " \ | |
7049288f | 94 | "cp.b ${u-boot_addr} fff00000 ${filesize};" \ |
7a8ddeea | 95 | "prot on fff00000 +${filesize}\0" \ |
53d4a498 | 96 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
53d4a498 | 97 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
7049288f | 98 | "nfsroot=${serverip}:${rootpath}\0" \ |
0ffb941c WG |
99 | "fat_args=setenv bootargs root=/dev/sda rw\0" \ |
100 | "mtdids=nor0=ff000000.flash\0" \ | |
101 | "mtdparts=ff000000.flash:13m(fs),2m(kernel),384k(uboot)," \ | |
102 | "128k(env),128k(redund_env)," \ | |
103 | "128k(dtb),128k(user_data)\0" \ | |
104 | "addcons=setenv bootargs ${bootargs} console=${console}\0" \ | |
105 | "addmtd=setenv bootargs ${bootargs} mtdparts=${mtdparts}\0" \ | |
7049288f BS |
106 | "addip=setenv bootargs ${bootargs} " \ |
107 | "ip=${ipaddr}:${serverip}:${gatewayip}:" \ | |
108 | "${netmask}:${hostname}:${netdev}:off panic=1 " \ | |
109 | "console=${console}\0" \ | |
110 | "net_nfs=tftp ${kernel_addr} ${bootfile}; " \ | |
0ffb941c WG |
111 | "tftp ${fdt_addr} ${fdt_file}; " \ |
112 | "run nfsargs addip addmtd; " \ | |
7049288f BS |
113 | "bootm ${kernel_addr} - ${fdt_addr}\0" \ |
114 | "net_self=tftp ${kernel_addr} ${bootfile}; " \ | |
115 | "tftp ${fdt_addr} ${fdt_file}; " \ | |
116 | "tftp ${ramdisk_addr} ${ramdisk_file}; " \ | |
0ffb941c WG |
117 | "nfs ${ramdisk_addr} ${serverip}:${rootpath}/images/uRamdisk; " \ |
118 | "run ramargs addip addcons addmtd; " \ | |
7049288f | 119 | "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ |
0ffb941c | 120 | "fat_multi=run fat_args addip addmtd; fatload ide 0:1 " \ |
fa5c2ba1 BS |
121 | "${multi_image_addr} ${multi_image_file}; " \ |
122 | "bootm ${multi_image_addr}\0" \ | |
53d4a498 | 123 | "" |
0ffb941c | 124 | #define CONFIG_BOOTCOMMAND "run fat_multi" |
53d4a498 | 125 | |
53d4a498 BS |
126 | /* |
127 | * do board-specific init | |
128 | */ | |
129 | #define CONFIG_BOARD_EARLY_INIT_R 1 | |
130 | ||
53d4a498 BS |
131 | /* |
132 | * Low level configuration | |
133 | */ | |
134 | ||
53d4a498 | 135 | /* |
d3afa1ee | 136 | * Clock configuration: SYS_XTALIN = 33MHz |
53d4a498 | 137 | */ |
6d0f6bcf | 138 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 |
53d4a498 | 139 | |
06241d50 | 140 | /* |
c99512d6 | 141 | * Set IPB speed to 100MHz |
06241d50 | 142 | */ |
6d0f6bcf | 143 | #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK |
06241d50 | 144 | |
53d4a498 BS |
145 | /* |
146 | * Memory map | |
147 | */ | |
148 | /* | |
149 | * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000. | |
150 | * Setting MBAR to otherwise will cause system hang when using SmartDMA such | |
151 | * as network commands. | |
152 | */ | |
7a8ddeea | 153 | #define CONFIG_SYS_MBAR 0xf0000000 |
6d0f6bcf | 154 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
53d4a498 BS |
155 | |
156 | /* | |
157 | * If building for running out of SDRAM, then MBAR has been set up beforehand | |
158 | * (e.g., by the BDI). Otherwise we must specify the default boot-up value of | |
159 | * MBAR, as given in the doccumentation. | |
160 | */ | |
14d0a02a | 161 | #if CONFIG_SYS_TEXT_BASE == 0x00100000 |
6d0f6bcf | 162 | #define CONFIG_SYS_DEFAULT_MBAR 0xf0000000 |
14d0a02a | 163 | #else /* CONFIG_SYS_TEXT_BASE != 0x00100000 */ |
6d0f6bcf JCPV |
164 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 |
165 | #define CONFIG_SYS_LOWBOOT 1 | |
14d0a02a | 166 | #endif /* CONFIG_SYS_TEXT_BASE == 0x00100000 */ |
53d4a498 BS |
167 | |
168 | /* Use SRAM until RAM will be available */ | |
6d0f6bcf | 169 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
553f0982 | 170 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE |
53d4a498 | 171 | |
25ddd1fb | 172 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 173 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
53d4a498 | 174 | |
14d0a02a | 175 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
176 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
177 | #define CONFIG_SYS_RAMBOOT 1 | |
53d4a498 BS |
178 | #endif |
179 | ||
0ffb941c | 180 | #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* 384 kB for Monitor */ |
6d0f6bcf JCPV |
181 | #define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* 1 MiB for malloc() */ |
182 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* initial mem map for Linux */ | |
53d4a498 | 183 | |
53d4a498 BS |
184 | /* |
185 | * Chip selects configuration | |
186 | */ | |
187 | /* Boot Chipselect */ | |
6d0f6bcf JCPV |
188 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
189 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
190 | #define CONFIG_SYS_BOOTCS_CFG 0x00045D00 | |
53d4a498 BS |
191 | |
192 | /* Flash memory addressing */ | |
6d0f6bcf JCPV |
193 | #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE |
194 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE | |
195 | #define CONFIG_SYS_CS0_CFG CONFIG_SYS_BOOTCS_CFG | |
53d4a498 BS |
196 | |
197 | /* Dual Port SRAM -- Kollmorgen Drive memory addressing */ | |
6d0f6bcf JCPV |
198 | #define CONFIG_SYS_CS1_START 0x50000000 |
199 | #define CONFIG_SYS_CS1_SIZE 0x10000 | |
200 | #define CONFIG_SYS_CS1_CFG 0x05055800 | |
53d4a498 BS |
201 | |
202 | /* Local register access */ | |
6d0f6bcf JCPV |
203 | #define CONFIG_SYS_CS2_START 0x50010000 |
204 | #define CONFIG_SYS_CS2_SIZE 0x10000 | |
205 | #define CONFIG_SYS_CS2_CFG 0x05055800 | |
53d4a498 BS |
206 | |
207 | /* Anybus CompactCom Module memory addressing */ | |
6d0f6bcf JCPV |
208 | #define CONFIG_SYS_CS3_START 0x50020000 |
209 | #define CONFIG_SYS_CS3_SIZE 0x10000 | |
210 | #define CONFIG_SYS_CS3_CFG 0x05055800 | |
53d4a498 BS |
211 | |
212 | /* No burst and dead cycle = 2 for all CSs */ | |
6d0f6bcf JCPV |
213 | #define CONFIG_SYS_CS_BURST 0x00000000 |
214 | #define CONFIG_SYS_CS_DEADCYCLE 0x22222222 | |
53d4a498 | 215 | |
53d4a498 BS |
216 | /* |
217 | * SDRAM configuration | |
218 | */ | |
d3afa1ee BS |
219 | /* 2 x MT48LC16M16A2BG-75 IT:D, CASL 3, 32 bit data bus */ |
220 | #define SDRAM_CONFIG1 0x62322900 | |
221 | #define SDRAM_CONFIG2 0x88c70000 | |
222 | #define SDRAM_CONTROL 0x504f0000 | |
223 | #define SDRAM_MODE 0x00cd0000 | |
53d4a498 | 224 | |
53d4a498 BS |
225 | /* |
226 | * Flash configuration | |
227 | */ | |
6d0f6bcf | 228 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
00b1883a | 229 | #define CONFIG_FLASH_CFI_DRIVER 1 |
6d0f6bcf JCPV |
230 | #define CONFIG_SYS_FLASH_BASE 0xff000000 |
231 | #define CONFIG_SYS_FLASH_SIZE 0x01000000 | |
232 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ | |
233 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
234 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ | |
53d4a498 BS |
235 | #define CONFIG_FLASH_16BIT /* Flash is 16-bit */ |
236 | ||
7d98ba77 PK |
237 | /* |
238 | * MTD configuration | |
239 | */ | |
68d7d651 | 240 | #define CONFIG_CMD_MTDPARTS |
942556a9 SR |
241 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
242 | #define CONFIG_FLASH_CFI_MTD | |
7d98ba77 PK |
243 | #define MTDIDS_DEFAULT "nor0=motionpro-0" |
244 | #define MTDPARTS_DEFAULT "mtdparts=motionpro-0:" \ | |
0ffb941c | 245 | "13m(fs),2m(kernel),384k(uboot)," \ |
d3afa1ee BS |
246 | "128k(env),128k(redund_env)," \ |
247 | "128k(dtb),-(user_data)" | |
53d4a498 | 248 | |
fa5c2ba1 BS |
249 | /* |
250 | * IDE/ATA configuration | |
251 | */ | |
6d0f6bcf JCPV |
252 | #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA |
253 | #define CONFIG_SYS_IDE_MAXBUS 1 | |
254 | #define CONFIG_SYS_IDE_MAXDEVICE 1 | |
fa5c2ba1 BS |
255 | #define CONFIG_IDE_PREINIT |
256 | ||
6d0f6bcf JCPV |
257 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0060 |
258 | #define CONFIG_SYS_ATA_REG_OFFSET CONFIG_SYS_ATA_DATA_OFFSET | |
259 | #define CONFIG_SYS_ATA_STRIDE 4 | |
fa5c2ba1 | 260 | |
de1de02a PK |
261 | /* |
262 | * I2C configuration | |
263 | */ | |
264 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
6d0f6bcf JCPV |
265 | #define CONFIG_SYS_I2C_MODULE 2 /* select I2C module #2 */ |
266 | #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ | |
267 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
de1de02a | 268 | |
de1de02a PK |
269 | /* |
270 | * EEPROM configuration | |
271 | */ | |
6d0f6bcf JCPV |
272 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
273 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 1 /* 2 bytes per write cycle */ | |
274 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* 2ms/cycle + 3ms extra */ | |
de1de02a | 275 | |
de1de02a PK |
276 | /* |
277 | * RTC configuration | |
278 | */ | |
279 | #define CONFIG_RTC_DS1337 1 | |
6d0f6bcf | 280 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
de1de02a | 281 | |
a11c0b85 BS |
282 | /* |
283 | * Status LED configuration | |
284 | */ | |
a11c0b85 BS |
285 | |
286 | #define ENABLE_GPIO_OUT 0x00000024 | |
287 | #define LED_ON 0x00000010 | |
288 | ||
93b78f53 BS |
289 | /* |
290 | * Temperature sensor | |
291 | */ | |
292 | #define CONFIG_DTT_LM75 1 | |
293 | #define CONFIG_DTT_SENSORS { 0x49 } | |
294 | ||
53d4a498 BS |
295 | /* |
296 | * Environment settings | |
297 | */ | |
5a1aceb0 | 298 | #define CONFIG_ENV_IS_IN_FLASH 1 |
53d4a498 | 299 | /* This has to be a multiple of the Flash sector size */ |
6d0f6bcf | 300 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
0e8d1586 JCPV |
301 | #define CONFIG_ENV_SIZE 0x1000 |
302 | #define CONFIG_ENV_SECT_SIZE 0x20000 | |
53d4a498 | 303 | |
4520fd4d | 304 | /* Configuration of redundant environment */ |
0e8d1586 JCPV |
305 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
306 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
53d4a498 BS |
307 | |
308 | /* | |
309 | * Pin multiplexing configuration | |
310 | */ | |
311 | ||
312 | /* PSC1: UART1 | |
313 | * PSC2: GPIO (default) | |
314 | * PSC3: GPIO (default) | |
315 | * USB: 2xUART4/5 | |
316 | * Ethernet: Ethernet 100Mbit with MD | |
317 | * Timer: CAN2/GPIO | |
318 | * PSC6/IRDA: GPIO (default) | |
319 | */ | |
6d0f6bcf | 320 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x1105a004 |
53d4a498 | 321 | |
c75e6396 BS |
322 | /* |
323 | * Motion-PRO's CPLD revision control register | |
324 | */ | |
6d0f6bcf | 325 | #define CPLD_REV_REGISTER (CONFIG_SYS_CS2_START + 0x06) |
c75e6396 | 326 | |
53d4a498 BS |
327 | /* |
328 | * Miscellaneous configurable options | |
329 | */ | |
6d0f6bcf | 330 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
6d0f6bcf JCPV |
331 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
332 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
333 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
334 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
53d4a498 | 335 | |
6d0f6bcf JCPV |
336 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
337 | #define CONFIG_SYS_MEMTEST_END 0x03e00000 /* 1 ... 62 MiB in DRAM */ | |
338 | #define CONFIG_SYS_ALT_MEMTEST | |
53d4a498 | 339 | |
6d0f6bcf | 340 | #define CONFIG_SYS_LOAD_ADDR 0x200000 /* default kernel load addr */ |
53d4a498 | 341 | |
53d4a498 BS |
342 | /* |
343 | * Various low-level settings | |
344 | */ | |
6d0f6bcf JCPV |
345 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
346 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
53d4a498 | 347 | |
6d0f6bcf | 348 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
53d4a498 | 349 | |
53d4a498 | 350 | /* Not needed for MPC 5xxx U-Boot, but used by tools/updater */ |
6d0f6bcf | 351 | #define CONFIG_SYS_RESET_ADDRESS 0xfff00100 |
53d4a498 | 352 | |
1f1369c3 BS |
353 | #define OF_CPU "PowerPC,5200@0" |
354 | #define OF_SOC "soc5200@f0000000" | |
355 | #define OF_TBCLK (bd->bi_busfreq / 4) | |
7049288f | 356 | #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" |
1f1369c3 | 357 | |
53d4a498 | 358 | #endif /* __CONFIG_H */ |