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eae4988b SB |
1 | /* |
2 | * (C) Copyright 2010, Stefano Babic <sbabic@denx.de> | |
3 | * | |
4 | * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. | |
5 | * | |
6 | * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> | |
7 | * | |
8 | * Configuration for the MX35pdk Freescale board. | |
9 | * | |
3765b3e7 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
eae4988b SB |
11 | */ |
12 | ||
13 | #ifndef __CONFIG_H | |
14 | #define __CONFIG_H | |
15 | ||
16 | #include <asm/arch/imx-regs.h> | |
17 | ||
18 | /* High Level Configuration Options */ | |
eae4988b | 19 | #define CONFIG_MX35 |
eae4988b | 20 | |
18fb0e3c | 21 | #define CONFIG_SYS_FSL_CLK |
eae4988b SB |
22 | |
23 | /* Set TEXT at the beginning of the NOR flash */ | |
24 | #define CONFIG_SYS_TEXT_BASE 0xA0000000 | |
25 | ||
eae4988b SB |
26 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
27 | #define CONFIG_REVISION_TAG | |
28 | #define CONFIG_SETUP_MEMORY_TAGS | |
29 | #define CONFIG_INITRD_TAG | |
30 | ||
31 | /* | |
32 | * Size of malloc() pool | |
33 | */ | |
34 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) | |
35 | ||
36 | /* | |
37 | * Hardware drivers | |
38 | */ | |
b089d039 | 39 | #define CONFIG_SYS_I2C |
40 | #define CONFIG_SYS_I2C_MXC | |
03544c66 AA |
41 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
42 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ | |
f8cb101e | 43 | #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ |
eae4988b | 44 | #define CONFIG_MXC_SPI |
a4adedd4 | 45 | #define CONFIG_MXC_GPIO |
eae4988b | 46 | |
eae4988b SB |
47 | /* |
48 | * PMIC Configs | |
49 | */ | |
be3b51aa ŁM |
50 | #define CONFIG_POWER |
51 | #define CONFIG_POWER_I2C | |
52 | #define CONFIG_POWER_FSL | |
913702ca | 53 | #define CONFIG_POWER_FSL_MC13892 |
eae4988b | 54 | #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x08 |
d28d6a96 | 55 | #define CONFIG_RTC_MC13XXX |
eae4988b SB |
56 | |
57 | /* | |
58 | * MFD MC9SDZ60 | |
59 | */ | |
60 | #define CONFIG_FSL_MC9SDZ60 | |
61 | #define CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR 0x69 | |
62 | ||
63 | /* | |
64 | * UART (console) | |
65 | */ | |
66 | #define CONFIG_MXC_UART | |
40f6fffe | 67 | #define CONFIG_MXC_UART_BASE UART1_BASE |
eae4988b SB |
68 | |
69 | /* allow to overwrite serial and ethaddr */ | |
70 | #define CONFIG_ENV_OVERWRITE | |
71 | #define CONFIG_CONS_INDEX 1 | |
eae4988b SB |
72 | |
73 | /* | |
74 | * Command definition | |
75 | */ | |
eae4988b SB |
76 | #define CONFIG_BOOTP_SUBNETMASK |
77 | #define CONFIG_BOOTP_GATEWAY | |
78 | #define CONFIG_BOOTP_DNS | |
79 | ||
eae4988b SB |
80 | #define CONFIG_NET_RETRY_COUNT 100 |
81 | ||
eae4988b SB |
82 | |
83 | #define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ | |
84 | ||
85 | /* | |
86 | * Ethernet on the debug board (SMC911) | |
87 | */ | |
88 | #define CONFIG_SMC911X | |
89 | #define CONFIG_SMC911X_16_BIT 1 | |
90 | #define CONFIG_SMC911X_BASE CS5_BASE_ADDR | |
91 | ||
92 | #define CONFIG_HAS_ETH1 | |
eae4988b SB |
93 | #define CONFIG_ETHPRIME |
94 | ||
95 | /* | |
96 | * Ethernet on SOC (FEC) | |
97 | */ | |
98 | #define CONFIG_FEC_MXC | |
99 | #define IMX_FEC_BASE FEC_BASE_ADDR | |
100 | #define CONFIG_FEC_MXC_PHYADDR 0x1F | |
101 | ||
102 | #define CONFIG_MII | |
eae4988b SB |
103 | |
104 | #define CONFIG_ARP_TIMEOUT 200UL | |
105 | ||
106 | /* | |
107 | * Miscellaneous configurable options | |
108 | */ | |
109 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
eae4988b | 110 | #define CONFIG_CMDLINE_EDITING |
eae4988b SB |
111 | |
112 | #define CONFIG_AUTO_COMPLETE | |
eae4988b SB |
113 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
114 | ||
115 | #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ | |
116 | #define CONFIG_SYS_MEMTEST_END 0x10000 | |
117 | ||
eae4988b SB |
118 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
119 | ||
eae4988b SB |
120 | /* |
121 | * Physical Memory Map | |
122 | */ | |
6b5acfc1 | 123 | #define CONFIG_NR_DRAM_BANKS 2 |
eae4988b SB |
124 | #define PHYS_SDRAM_1 CSD0_BASE_ADDR |
125 | #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) | |
6b5acfc1 SB |
126 | #define PHYS_SDRAM_2 CSD1_BASE_ADDR |
127 | #define PHYS_SDRAM_2_SIZE (128 * 1024 * 1024) | |
eae4988b SB |
128 | |
129 | #define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR | |
130 | #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR + 0x10000) | |
131 | #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE / 2) | |
132 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ | |
133 | GENERATED_GBL_DATA_SIZE) | |
134 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | |
135 | CONFIG_SYS_GBL_DATA_OFFSET) | |
136 | ||
137 | /* | |
138 | * MTD Command for mtdparts | |
139 | */ | |
eae4988b SB |
140 | #define CONFIG_MTD_DEVICE |
141 | #define CONFIG_FLASH_CFI_MTD | |
142 | #define CONFIG_MTD_PARTITIONS | |
143 | #define MTDIDS_DEFAULT "nand0=mxc_nand,nor0=physmap-flash.0" | |
144 | #define MTDPARTS_DEFAULT "mtdparts=mxc_nand:1m(boot),5m(linux)," \ | |
145 | "96m(root),8m(cfg),1938m(user);" \ | |
146 | "physmap-flash.0:512k(b),4m(k),30m(u),28m(r)" | |
147 | ||
148 | /* | |
149 | * FLASH and environment organization | |
150 | */ | |
151 | #define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR | |
152 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
153 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ | |
154 | /* Monitor at beginning of flash */ | |
155 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
156 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) | |
157 | ||
158 | #define CONFIG_ENV_SECT_SIZE (128 * 1024) | |
159 | #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE | |
160 | ||
161 | /* Address and size of Redundant Environment Sector */ | |
162 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) | |
163 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE | |
164 | ||
165 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ | |
166 | CONFIG_SYS_MONITOR_LEN) | |
167 | ||
eae4988b | 168 | #if defined(CONFIG_FSL_ENV_IN_NAND) |
eae4988b SB |
169 | #define CONFIG_ENV_OFFSET (1024 * 1024) |
170 | #endif | |
171 | ||
172 | /* | |
173 | * CFI FLASH driver setup | |
174 | */ | |
175 | #define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ | |
176 | #define CONFIG_FLASH_CFI_DRIVER | |
177 | ||
178 | /* A non-standard buffered write algorithm */ | |
179 | #define CONFIG_FLASH_SPANSION_S29WS_N | |
180 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* faster */ | |
181 | #define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */ | |
182 | ||
183 | /* | |
184 | * NAND FLASH driver setup | |
185 | */ | |
186 | #define CONFIG_NAND_MXC | |
eae4988b SB |
187 | #define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR) |
188 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
189 | #define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR) | |
190 | #define CONFIG_MXC_NAND_HWECC | |
191 | #define CONFIG_SYS_NAND_LARGEPAGE | |
192 | ||
961a7628 | 193 | /* EHCI driver */ |
961a7628 BT |
194 | #define CONFIG_EHCI_IS_TDI |
195 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
196 | #define CONFIG_USB_EHCI_MXC | |
197 | #define CONFIG_MXC_USB_PORT 0 | |
198 | #define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERFACE_DIFF_UNI | \ | |
199 | MXC_EHCI_POWER_PINS_ENABLED | \ | |
200 | MXC_EHCI_OC_PIN_ACTIVE_LOW) | |
201 | #define CONFIG_MXC_USB_PORTSC (MXC_EHCI_UTMI_16BIT | MXC_EHCI_MODE_UTMI) | |
202 | ||
3292539e | 203 | /* mmc driver */ |
3292539e SB |
204 | #define CONFIG_FSL_ESDHC |
205 | #define CONFIG_SYS_FSL_ESDHC_ADDR 0 | |
206 | #define CONFIG_SYS_FSL_ESDHC_NUM 1 | |
207 | ||
eae4988b SB |
208 | /* |
209 | * Default environment and default scripts | |
210 | * to update uboot and load kernel | |
211 | */ | |
eae4988b SB |
212 | |
213 | #define CONFIG_HOSTNAME "mx35pdk" | |
214 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
215 | "netdev=eth1\0" \ | |
216 | "ethprime=smc911x\0" \ | |
217 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
218 | "nfsroot=${serverip}:${rootpath}\0" \ | |
219 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
220 | "addip_sta=setenv bootargs ${bootargs} " \ | |
221 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
222 | ":${hostname}:${netdev}:off panic=1\0" \ | |
223 | "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ | |
224 | "addip=if test -n ${ipdyn};then run addip_dyn;" \ | |
93ea89f0 | 225 | "else run addip_sta;fi\0" \ |
eae4988b SB |
226 | "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ |
227 | "addtty=setenv bootargs ${bootargs}" \ | |
228 | " console=ttymxc0,${baudrate}\0" \ | |
229 | "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ | |
230 | "loadaddr=80800000\0" \ | |
231 | "kernel_addr_r=80800000\0" \ | |
93ea89f0 MV |
232 | "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ |
233 | "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ | |
234 | "ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/uRamdisk\0" \ | |
eae4988b SB |
235 | "flash_self=run ramargs addip addtty addmtd addmisc;" \ |
236 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
237 | "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ | |
238 | "bootm ${kernel_addr}\0" \ | |
239 | "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ | |
240 | "run nfsargs addip addtty addmtd addmisc;" \ | |
241 | "bootm ${kernel_addr_r}\0" \ | |
242 | "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \ | |
243 | "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \ | |
93ea89f0 | 244 | "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \ |
eae4988b | 245 | "load=tftp ${loadaddr} ${u-boot}\0" \ |
93ea89f0 | 246 | "uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \ |
3292539e SB |
247 | "update=protect off ${uboot_addr} +80000;" \ |
248 | "erase ${uboot_addr} +80000;" \ | |
eae4988b SB |
249 | "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \ |
250 | "upd=if run load;then echo Updating u-boot;if run update;" \ | |
251 | "then echo U-Boot updated;" \ | |
252 | "else echo Error updating u-boot !;" \ | |
253 | "echo Board without bootloader !!;" \ | |
254 | "fi;" \ | |
255 | "else echo U-Boot not downloaded..exiting;fi\0" \ | |
256 | "bootcmd=run net_nfs\0" | |
257 | ||
258 | #endif /* __CONFIG_H */ |