[people/ms/u-boot.git] / include / configs / mx35pdk.h

/*
 * (C) Copyright 2010, Stefano Babic <sbabic@denx.de>
 *
 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
 *
 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
 *
 * Configuration for the MX35pdk Freescale board.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <asm/arch/imx-regs.h>

 /* High Level Configuration Options */
#define CONFIG_MX35

#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_SYS_FSL_CLK

/* Set TEXT at the beginning of the NOR flash */
#define CONFIG_SYS_TEXT_BASE	0xA0000000

#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT

#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
#define CONFIG_REVISION_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1024 * 1024)

/*
 * Hardware drivers
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
#define CONFIG_MXC_SPI
#define CONFIG_MXC_GPIO

/*
 * PMIC Configs
 */
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_FSL
#define CONFIG_POWER_FSL_MC13892
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR	0x08
#define CONFIG_RTC_MC13XXX

/*
 * MFD MC9SDZ60
 */
#define CONFIG_FSL_MC9SDZ60
#define CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR	0x69

/*
 * UART (console)
 */
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE	UART1_BASE

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX	1
#define CONFIG_BAUDRATE		115200

/*
 * Command definition
 */
#define CONFIG_CMD_BOOTZ
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_DNS

#define CONFIG_CMD_NAND
#define CONFIG_CMD_CACHE

#define CONFIG_CMD_MII
#define CONFIG_NET_RETRY_COUNT	100
#define CONFIG_CMD_DATE

#define CONFIG_USB_STORAGE
#define CONFIG_CMD_MMC
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT

#define CONFIG_BOOTDELAY	1

#define CONFIG_LOADADDR		0x80800000	/* loadaddr env var */

/*
 * Ethernet on the debug board (SMC911)
 */
#define CONFIG_SMC911X
#define CONFIG_SMC911X_16_BIT 1
#define CONFIG_SMC911X_BASE CS5_BASE_ADDR

#define CONFIG_HAS_ETH1
#define CONFIG_ETHPRIME

/*
 * Ethernet on SOC (FEC)
 */
#define CONFIG_FEC_MXC
#define IMX_FEC_BASE	FEC_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR	0x1F

#define CONFIG_MII

#define CONFIG_ARP_TIMEOUT	200UL

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP	/* undef to save memory */
#define CONFIG_CMDLINE_EDITING

#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */

#define CONFIG_SYS_MEMTEST_START	0	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x10000

#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR

/*
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	2
#define PHYS_SDRAM_1		CSD0_BASE_ADDR
#define PHYS_SDRAM_1_SIZE	(128 * 1024 * 1024)
#define PHYS_SDRAM_2		CSD1_BASE_ADDR
#define PHYS_SDRAM_2_SIZE	(128 * 1024 * 1024)

#define CONFIG_SYS_SDRAM_BASE		CSD0_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR + 0x10000)
#define CONFIG_SYS_INIT_RAM_SIZE		(IRAM_SIZE / 2)
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
					GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
					CONFIG_SYS_GBL_DATA_OFFSET)

/*
 * MTD Command for mtdparts
 */
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE
#define CONFIG_FLASH_CFI_MTD
#define CONFIG_MTD_PARTITIONS
#define MTDIDS_DEFAULT		"nand0=mxc_nand,nor0=physmap-flash.0"
#define MTDPARTS_DEFAULT	"mtdparts=mxc_nand:1m(boot),5m(linux),"	\
				"96m(root),8m(cfg),1938m(user);"	\
				"physmap-flash.0:512k(b),4m(k),30m(u),28m(r)"

/*
 * FLASH and environment organization
 */
#define CONFIG_SYS_FLASH_BASE		CS0_BASE_ADDR
#define CONFIG_SYS_MAX_FLASH_BANKS 1	/* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 512	/* max number of sectors on one chip */
/* Monitor at beginning of flash */
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)

#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE

#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
				CONFIG_SYS_MONITOR_LEN)

#define CONFIG_ENV_IS_IN_FLASH

#if defined(CONFIG_FSL_ENV_IN_NAND)
	#define CONFIG_ENV_IS_IN_NAND
	#define CONFIG_ENV_OFFSET       (1024 * 1024)
#endif

/*
 * CFI FLASH driver setup
 */
#define CONFIG_SYS_FLASH_CFI		/* Flash memory is CFI compliant */
#define CONFIG_FLASH_CFI_DRIVER

/* A non-standard buffered write algorithm */
#define CONFIG_FLASH_SPANSION_S29WS_N
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* faster */
#define CONFIG_SYS_FLASH_PROTECTION	/* Use hardware sector protection */

/*
 * NAND FLASH driver setup
 */
#define CONFIG_NAND_MXC
#define CONFIG_MXC_NAND_REGS_BASE	(NFC_BASE_ADDR)
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BASE		(NFC_BASE_ADDR)
#define CONFIG_MXC_NAND_HWECC
#define CONFIG_SYS_NAND_LARGEPAGE

/* EHCI driver */
#define CONFIG_USB_EHCI
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	1
#define CONFIG_EHCI_IS_TDI
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_EHCI_MXC
#define CONFIG_MXC_USB_PORT	0
#define CONFIG_MXC_USB_FLAGS	(MXC_EHCI_INTERFACE_DIFF_UNI | \
				 MXC_EHCI_POWER_PINS_ENABLED | \
				 MXC_EHCI_OC_PIN_ACTIVE_LOW)
#define CONFIG_MXC_USB_PORTSC	(MXC_EHCI_UTMI_16BIT | MXC_EHCI_MODE_UTMI)

/* mmc driver */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR	0
#define CONFIG_SYS_FSL_ESDHC_NUM	1

/*
 * Default environment and default scripts
 * to update uboot and load kernel
 */

#define CONFIG_HOSTNAME "mx35pdk"
#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth1\0"							\
	"ethprime=smc911x\0"						\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip_sta=setenv bootargs ${bootargs} "			\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"		\
	"addip=if test -n ${ipdyn};then run addip_dyn;"			\
		"else run addip_sta;fi\0"				\
	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
	"addtty=setenv bootargs ${bootargs}"				\
		" console=ttymxc0,${baudrate}\0"			\
	"addmisc=setenv bootargs ${bootargs} ${misc}\0"			\
	"loadaddr=80800000\0"						\
	"kernel_addr_r=80800000\0"					\
	"hostname=" __stringify(CONFIG_HOSTNAME) "\0"			\
	"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0"		\
	"ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/uRamdisk\0"	\
	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr}\0"				\
	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
		"run nfsargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr_r}\0"				\
	"net_self_load=tftp ${kernel_addr_r} ${bootfile};"		\
		"tftp ${ramdisk_addr_r} ${ramdisk_file};\0"		\
	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0"		\
	"load=tftp ${loadaddr} ${u-boot}\0"				\
	"uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0"		\
	"update=protect off ${uboot_addr} +80000;"			\
		"erase ${uboot_addr} +80000;"				\
		"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0"		\
	"upd=if run load;then echo Updating u-boot;if run update;"	\
		"then echo U-Boot updated;"				\
			"else echo Error updating u-boot !;"		\
			"echo Board without bootloader !!;"		\
		"fi;"							\
		"else echo U-Boot not downloaded..exiting;fi\0"		\
	"bootcmd=run net_nfs\0"

#endif				/* __CONFIG_H */
Commit	Line	Data
eae4988b SB	1	/*
	2	* (C) Copyright 2010, Stefano Babic <sbabic@denx.de>
	3	*
	4	* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
	5	*
	6	* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
	7	*
	8	* Configuration for the MX35pdk Freescale board.
	9	*
3765b3e7	10	* SPDX-License-Identifier: GPL-2.0+
eae4988b SB	11	*/
	12
	13	#ifndef __CONFIG_H
	14	#define __CONFIG_H
	15
	16	#include <asm/arch/imx-regs.h>
	17
	18	/* High Level Configuration Options */
eae4988b	19	#define CONFIG_MX35
eae4988b SB	20
eae4988b SB	21	#define CONFIG_DISPLAY_CPUINFO
18fb0e3c	22	#define CONFIG_SYS_FSL_CLK
eae4988b SB	23
	24	/* Set TEXT at the beginning of the NOR flash */
	25	#define CONFIG_SYS_TEXT_BASE 0xA0000000
	26
eae4988b	27	#define CONFIG_BOARD_EARLY_INIT_F
9660e442	28	#define CONFIG_BOARD_LATE_INIT
eae4988b SB	29
	30	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	31	#define CONFIG_REVISION_TAG
	32	#define CONFIG_SETUP_MEMORY_TAGS
	33	#define CONFIG_INITRD_TAG
	34
	35	/*
	36	* Size of malloc() pool
	37	*/
	38	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
	39
	40	/*
	41	* Hardware drivers
	42	*/
b089d039	43	#define CONFIG_SYS_I2C
b089d039	44	#define CONFIG_SYS_I2C_MXC
03544c66 AA	45	#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
03544c66 AA	46	#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
f8cb101e	47	#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
eae4988b	48	#define CONFIG_MXC_SPI
a4adedd4	49	#define CONFIG_MXC_GPIO
eae4988b	50
eae4988b SB	51	/*
	52	* PMIC Configs
	53	*/
be3b51aa ŁM	54	#define CONFIG_POWER
	55	#define CONFIG_POWER_I2C
	56	#define CONFIG_POWER_FSL
913702ca	57	#define CONFIG_POWER_FSL_MC13892
eae4988b	58	#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x08
d28d6a96	59	#define CONFIG_RTC_MC13XXX
eae4988b SB	60
	61	/*
	62	* MFD MC9SDZ60
	63	*/
	64	#define CONFIG_FSL_MC9SDZ60
	65	#define CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR 0x69
	66
	67	/*
	68	* UART (console)
	69	*/
	70	#define CONFIG_MXC_UART
40f6fffe	71	#define CONFIG_MXC_UART_BASE UART1_BASE
eae4988b SB	72
	73	/* allow to overwrite serial and ethaddr */
	74	#define CONFIG_ENV_OVERWRITE
	75	#define CONFIG_CONS_INDEX 1
	76	#define CONFIG_BAUDRATE 115200
eae4988b SB	77
	78	/*
	79	* Command definition
	80	*/
ee303c96	81	#define CONFIG_CMD_BOOTZ
eae4988b SB	82	#define CONFIG_BOOTP_SUBNETMASK
	83	#define CONFIG_BOOTP_GATEWAY
	84	#define CONFIG_BOOTP_DNS
	85
	86	#define CONFIG_CMD_NAND
0792a36e	87	#define CONFIG_CMD_CACHE
eae4988b	88
eae4988b	89	#define CONFIG_CMD_MII
eae4988b	90	#define CONFIG_NET_RETRY_COUNT 100
d28d6a96	91	#define CONFIG_CMD_DATE
eae4988b	92
961a7628	93	#define CONFIG_USB_STORAGE
3292539e SB	94	#define CONFIG_CMD_MMC
	95	#define CONFIG_DOS_PARTITION
	96	#define CONFIG_EFI_PARTITION
	97	#define CONFIG_CMD_EXT2
	98	#define CONFIG_CMD_FAT
	99
ec7503bb	100	#define CONFIG_BOOTDELAY 1
eae4988b SB	101
	102	#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
	103
	104	/*
	105	* Ethernet on the debug board (SMC911)
	106	*/
	107	#define CONFIG_SMC911X
	108	#define CONFIG_SMC911X_16_BIT 1
	109	#define CONFIG_SMC911X_BASE CS5_BASE_ADDR
	110
	111	#define CONFIG_HAS_ETH1
eae4988b SB	112	#define CONFIG_ETHPRIME
	113
	114	/*
	115	* Ethernet on SOC (FEC)
	116	*/
	117	#define CONFIG_FEC_MXC
	118	#define IMX_FEC_BASE FEC_BASE_ADDR
	119	#define CONFIG_FEC_MXC_PHYADDR 0x1F
	120
	121	#define CONFIG_MII
eae4988b SB	122
	123	#define CONFIG_ARP_TIMEOUT 200UL
	124
	125	/*
	126	* Miscellaneous configurable options
	127	*/
	128	#define CONFIG_SYS_LONGHELP /* undef to save memory */
eae4988b	129	#define CONFIG_CMDLINE_EDITING
eae4988b SB	130
	131	#define CONFIG_AUTO_COMPLETE
	132	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
eae4988b SB	133	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	134	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	135
	136	#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
	137	#define CONFIG_SYS_MEMTEST_END 0x10000
	138
eae4988b SB	139	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
eae4988b SB	140
eae4988b SB	141	/*
	142	* Physical Memory Map
	143	*/
6b5acfc1	144	#define CONFIG_NR_DRAM_BANKS 2
eae4988b SB	145	#define PHYS_SDRAM_1 CSD0_BASE_ADDR
eae4988b SB	146	#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
6b5acfc1 SB	147	#define PHYS_SDRAM_2 CSD1_BASE_ADDR
6b5acfc1 SB	148	#define PHYS_SDRAM_2_SIZE (128 * 1024 * 1024)
eae4988b SB	149
	150	#define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR
	151	#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR + 0x10000)
	152	#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE / 2)
	153	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
	154	GENERATED_GBL_DATA_SIZE)
	155	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	156	CONFIG_SYS_GBL_DATA_OFFSET)
	157
	158	/*
	159	* MTD Command for mtdparts
	160	*/
	161	#define CONFIG_CMD_MTDPARTS
	162	#define CONFIG_MTD_DEVICE
	163	#define CONFIG_FLASH_CFI_MTD
	164	#define CONFIG_MTD_PARTITIONS
	165	#define MTDIDS_DEFAULT "nand0=mxc_nand,nor0=physmap-flash.0"
	166	#define MTDPARTS_DEFAULT "mtdparts=mxc_nand:1m(boot),5m(linux)," \
	167	"96m(root),8m(cfg),1938m(user);" \
	168	"physmap-flash.0:512k(b),4m(k),30m(u),28m(r)"
	169
	170	/*
	171	* FLASH and environment organization
	172	*/
	173	#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR
	174	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	175	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
	176	/* Monitor at beginning of flash */
	177	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	178	#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
	179
	180	#define CONFIG_ENV_SECT_SIZE (128 * 1024)
	181	#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
	182
	183	/* Address and size of Redundant Environment Sector */
	184	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
	185	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
	186
	187	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
	188	CONFIG_SYS_MONITOR_LEN)
	189
	190	#define CONFIG_ENV_IS_IN_FLASH
	191
	192	#if defined(CONFIG_FSL_ENV_IN_NAND)
	193	#define CONFIG_ENV_IS_IN_NAND
	194	#define CONFIG_ENV_OFFSET (1024 * 1024)
	195	#endif
	196
	197	/*
	198	* CFI FLASH driver setup
	199	*/
	200	#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
	201	#define CONFIG_FLASH_CFI_DRIVER
	202
	203	/* A non-standard buffered write algorithm */
	204	#define CONFIG_FLASH_SPANSION_S29WS_N
	205	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* faster */
	206	#define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */
	207
	208	/*
	209	* NAND FLASH driver setup
	210	*/
	211	#define CONFIG_NAND_MXC
eae4988b SB	212	#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR)
	213	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	214	#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR)
	215	#define CONFIG_MXC_NAND_HWECC
	216	#define CONFIG_SYS_NAND_LARGEPAGE
	217
961a7628 BT	218	/* EHCI driver */
	219	#define CONFIG_USB_EHCI
	220	#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
	221	#define CONFIG_EHCI_IS_TDI
	222	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
	223	#define CONFIG_USB_EHCI_MXC
	224	#define CONFIG_MXC_USB_PORT 0
	225	#define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERFACE_DIFF_UNI \| \
	226	MXC_EHCI_POWER_PINS_ENABLED \| \
	227	MXC_EHCI_OC_PIN_ACTIVE_LOW)
	228	#define CONFIG_MXC_USB_PORTSC (MXC_EHCI_UTMI_16BIT \| MXC_EHCI_MODE_UTMI)
	229
3292539e SB	230	/* mmc driver */
	231	#define CONFIG_MMC
	232	#define CONFIG_GENERIC_MMC
	233	#define CONFIG_FSL_ESDHC
	234	#define CONFIG_SYS_FSL_ESDHC_ADDR 0
	235	#define CONFIG_SYS_FSL_ESDHC_NUM 1
	236
eae4988b SB	237	/*
	238	* Default environment and default scripts
	239	* to update uboot and load kernel
	240	*/
eae4988b SB	241
	242	#define CONFIG_HOSTNAME "mx35pdk"
	243	#define CONFIG_EXTRA_ENV_SETTINGS \
	244	"netdev=eth1\0" \
	245	"ethprime=smc911x\0" \
	246	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	247	"nfsroot=${serverip}:${rootpath}\0" \
	248	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	249	"addip_sta=setenv bootargs ${bootargs} " \
	250	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	251	":${hostname}:${netdev}:off panic=1\0" \
	252	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
	253	"addip=if test -n ${ipdyn};then run addip_dyn;" \
93ea89f0	254	"else run addip_sta;fi\0" \
eae4988b SB	255	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
	256	"addtty=setenv bootargs ${bootargs}" \
	257	" console=ttymxc0,${baudrate}\0" \
	258	"addmisc=setenv bootargs ${bootargs} ${misc}\0" \
	259	"loadaddr=80800000\0" \
	260	"kernel_addr_r=80800000\0" \
93ea89f0 MV	261	"hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
	262	"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
	263	"ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/uRamdisk\0" \
eae4988b SB	264	"flash_self=run ramargs addip addtty addmtd addmisc;" \
	265	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
	266	"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
	267	"bootm ${kernel_addr}\0" \
	268	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
	269	"run nfsargs addip addtty addmtd addmisc;" \
	270	"bootm ${kernel_addr_r}\0" \
	271	"net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
	272	"tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
93ea89f0	273	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \
eae4988b	274	"load=tftp ${loadaddr} ${u-boot}\0" \
93ea89f0	275	"uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
3292539e SB	276	"update=protect off ${uboot_addr} +80000;" \
3292539e SB	277	"erase ${uboot_addr} +80000;" \
eae4988b SB	278	"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
	279	"upd=if run load;then echo Updating u-boot;if run update;" \
	280	"then echo U-Boot updated;" \
	281	"else echo Error updating u-boot !;" \
	282	"echo Board without bootloader !!;" \
	283	"fi;" \
	284	"else echo U-Boot not downloaded..exiting;fi\0" \
	285	"bootcmd=run net_nfs\0"
	286
	287	#endif /* __CONFIG_H */