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94391fbc LHR |
1 | /* |
2 | * Copyright (C) 2010 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * Configuration settings for the MX53-EVK Freescale board. | |
5 | * | |
3765b3e7 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
94391fbc LHR |
7 | */ |
8 | ||
9 | #ifndef __CONFIG_H | |
10 | #define __CONFIG_H | |
11 | ||
00e11a43 FE |
12 | #define CONFIG_MACH_TYPE MACH_TYPE_MX53_EVK |
13 | ||
94391fbc LHR |
14 | #include <asm/arch/imx-regs.h> |
15 | ||
a7abca01 | 16 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
a7abca01 FE |
17 | #define CONFIG_SETUP_MEMORY_TAGS |
18 | #define CONFIG_INITRD_TAG | |
fd622f23 | 19 | #define CONFIG_REVISION_TAG |
94391fbc | 20 | |
18fb0e3c | 21 | #define CONFIG_SYS_FSL_CLK |
851f556a | 22 | |
94391fbc LHR |
23 | /* Size of malloc() pool */ |
24 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) | |
25 | ||
94391fbc LHR |
26 | #define CONFIG_MXC_GPIO |
27 | ||
28 | #define CONFIG_MXC_UART | |
40f6fffe | 29 | #define CONFIG_MXC_UART_BASE UART1_BASE |
94391fbc LHR |
30 | |
31 | /* I2C Configs */ | |
b089d039 | 32 | #define CONFIG_SYS_I2C |
33 | #define CONFIG_SYS_I2C_MXC | |
03544c66 AA |
34 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
35 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ | |
f8cb101e | 36 | #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ |
94391fbc LHR |
37 | |
38 | /* PMIC Configs */ | |
be3b51aa ŁM |
39 | #define CONFIG_POWER |
40 | #define CONFIG_POWER_I2C | |
41 | #define CONFIG_POWER_FSL | |
94391fbc | 42 | #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 8 |
913702ca | 43 | #define CONFIG_POWER_FSL_MC13892 |
4f97c88e | 44 | #define CONFIG_RTC_MC13XXX |
94391fbc LHR |
45 | |
46 | /* MMC Configs */ | |
47 | #define CONFIG_FSL_ESDHC | |
48 | #define CONFIG_SYS_FSL_ESDHC_ADDR 0 | |
49 | #define CONFIG_SYS_FSL_ESDHC_NUM 2 | |
50 | ||
94391fbc | 51 | /* Eth Configs */ |
94391fbc | 52 | #define CONFIG_MII |
94391fbc LHR |
53 | |
54 | #define CONFIG_FEC_MXC | |
55 | #define IMX_FEC_BASE FEC_BASE_ADDR | |
56 | #define CONFIG_FEC_MXC_PHYADDR 0x1F | |
57 | ||
4f97c88e | 58 | #define CONFIG_CMD_DATE |
94391fbc | 59 | |
0aff384b TK |
60 | /* Miscellaneous commands */ |
61 | #define CONFIG_CMD_BMODE | |
62 | ||
94391fbc LHR |
63 | /* allow to overwrite serial and ethaddr */ |
64 | #define CONFIG_ENV_OVERWRITE | |
65 | #define CONFIG_CONS_INDEX 1 | |
94391fbc LHR |
66 | |
67 | /* Command definition */ | |
94391fbc | 68 | |
28b119e9 | 69 | #define CONFIG_ETHPRIME "FEC0" |
94391fbc LHR |
70 | |
71 | #define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */ | |
72 | #define CONFIG_SYS_TEXT_BASE 0x77800000 | |
73 | ||
74 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
75 | "script=boot.scr\0" \ | |
76 | "uimage=uImage\0" \ | |
77 | "mmcdev=0\0" \ | |
78 | "mmcpart=2\0" \ | |
79 | "mmcroot=/dev/mmcblk0p3 rw\0" \ | |
80 | "mmcrootfstype=ext3 rootwait\0" \ | |
81 | "mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \ | |
82 | "root=${mmcroot} " \ | |
83 | "rootfstype=${mmcrootfstype}\0" \ | |
84 | "loadbootscript=" \ | |
85 | "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ | |
86 | "bootscript=echo Running bootscript from mmc ...; " \ | |
87 | "source\0" \ | |
88 | "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ | |
89 | "mmcboot=echo Booting from mmc ...; " \ | |
90 | "run mmcargs; " \ | |
91 | "bootm\0" \ | |
92 | "netargs=setenv bootargs console=ttymxc0,${baudrate} " \ | |
93 | "root=/dev/nfs " \ | |
94 | "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ | |
95 | "netboot=echo Booting from net ...; " \ | |
96 | "run netargs; " \ | |
97 | "dhcp ${uimage}; bootm\0" \ | |
98 | ||
99 | #define CONFIG_BOOTCOMMAND \ | |
66968110 | 100 | "mmc dev ${mmcdev}; if mmc rescan; then " \ |
94391fbc LHR |
101 | "if run loadbootscript; then " \ |
102 | "run bootscript; " \ | |
103 | "else " \ | |
104 | "if run loaduimage; then " \ | |
105 | "run mmcboot; " \ | |
106 | "else run netboot; " \ | |
107 | "fi; " \ | |
108 | "fi; " \ | |
109 | "else run netboot; fi" | |
110 | ||
111 | #define CONFIG_ARP_TIMEOUT 200UL | |
112 | ||
113 | /* Miscellaneous configurable options */ | |
114 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
94391fbc LHR |
115 | #define CONFIG_AUTO_COMPLETE |
116 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
117 | ||
118 | /* Print Buffer Size */ | |
119 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
120 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
121 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
122 | ||
123 | #define CONFIG_SYS_MEMTEST_START 0x70000000 | |
bc9d5ef1 | 124 | #define CONFIG_SYS_MEMTEST_END 0x70010000 |
94391fbc LHR |
125 | |
126 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | |
127 | ||
94391fbc LHR |
128 | #define CONFIG_CMDLINE_EDITING |
129 | ||
94391fbc LHR |
130 | /* Physical Memory Map */ |
131 | #define CONFIG_NR_DRAM_BANKS 1 | |
132 | #define PHYS_SDRAM_1 CSD0_BASE_ADDR | |
133 | #define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) | |
134 | ||
135 | #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) | |
136 | #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) | |
137 | #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) | |
138 | ||
139 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
140 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
141 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
142 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
143 | ||
e856bdcf | 144 | /* environment organization */ |
94391fbc LHR |
145 | #define CONFIG_ENV_OFFSET (6 * 64 * 1024) |
146 | #define CONFIG_ENV_SIZE (8 * 1024) | |
147 | #define CONFIG_ENV_IS_IN_MMC | |
148 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
149 | ||
150 | #endif /* __CONFIG_H */ |