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1/*
2 * (C) Copyright 2006-2008
3 * Texas Instruments.
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
6 *
7 * Configuration settings for the TI OMAP3530 Beagle board.
8 *
3765b3e7 9 * SPDX-License-Identifier: GPL-2.0+
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10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
f904cdbb 14
df4dbb5d
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15#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
16
f904cdbb 17/*
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18 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
19 * 64 bytes before this address should be set aside for u-boot.img's
20 * header. That is 0x800FFFC0--0x80100000 should not be used for any
21 * other needs. We use this rather than the inherited defines from
22 * ti_armv7_common.h for backwards compatibility.
f904cdbb 23 */
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24#define CONFIG_SYS_TEXT_BASE 0x80100000
25#define CONFIG_SPL_BSS_START_ADDR 0x80000000
26#define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */
27#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
28#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
cae377b5 29
df4dbb5d 30#include <configs/ti_omap3_common.h>
f904cdbb 31
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32#define CONFIG_MISC_INIT_R
33
f904cdbb 34#define CONFIG_REVISION_TAG 1
f904cdbb 35#define CONFIG_ENV_OVERWRITE
f904cdbb 36
70d8c944 37/* Status LED */
70d8c944 38
f74fc4ae
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39/* Enable Multi Bus support for I2C */
40#define CONFIG_I2C_MULTI_BUS 1
41
42/* Probe all devices */
8c4e0ca6 43#define CONFIG_SYS_I2C_NOPROBES {{0x0, 0x0}}
f74fc4ae 44
25374bfb 45/* USB */
c2af345e 46#define CONFIG_USB_MUSB_OMAP2PLUS
95de1e2f 47#define CONFIG_USB_MUSB_PIO_ONLY
25374bfb
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48#define CONFIG_TWL4030_USB 1
49
d90859a6 50/* USB EHCI */
928c4bdf 51
29321c05
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52#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 147
53
f904cdbb 54/* commands to include */
df4dbb5d 55
25a4d017 56#define CONFIG_VIDEO_OMAP3 /* DSS Support */
f904cdbb 57
2c155130
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58/*
59 * TWL4030
60 */
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61#define CONFIG_TWL4030_LED 1
62
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63/*
64 * Board NAND Info.
65 */
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66#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
67 /* devices */
f904cdbb 68
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69#define BOOT_TARGET_DEVICES(func) \
70 func(MMC, mmc, 0)
71
72#define CONFIG_BOOTCOMMAND \
73 "run findfdt; " \
74 "run distro_bootcmd; " \
75 "mmc dev ${mmcdev}; if mmc rescan; then " \
76 "if run userbutton; then " \
77 "setenv bootenv uEnv.txt;" \
78 "else " \
79 "setenv bootenv user.txt;" \
80 "fi;" \
81 "echo SD/MMC found on device ${mmcdev};" \
82 "if run loadbootenv; then " \
83 "echo Loaded environment from ${bootenv};" \
84 "run importbootenv;" \
85 "fi;" \
86 "if test -n $uenvcmd; then " \
87 "echo Running uenvcmd ...;" \
88 "run uenvcmd;" \
89 "fi;" \
90 "if run loadbootscript; then " \
91 "run bootscript; " \
92 "else " \
93 "if run loadimage; then " \
94 "run mmcboot;" \
95 "fi;" \
96 "fi; " \
97 "fi;" \
98 "run nandboot;" \
99 "setenv bootfile zImage;" \
100 "if run loadimage; then " \
101 "run loadfdt;" \
102 "run mmcbootz; " \
103 "fi; " \
104
105#include <config_distro_bootcmd.h>
106
f904cdbb 107#define CONFIG_EXTRA_ENV_SETTINGS \
f4b36ea9 108 "loadaddr=0x80200000\0" \
c721fd6e 109 "kernel_addr_r=0x80200000\0" \
f4b36ea9 110 "rdaddr=0x81000000\0" \
c721fd6e 111 "initrd_addr_r=0x81000000\0" \
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112 "fdt_high=0xffffffff\0" \
113 "fdtaddr=0x80f80000\0" \
c721fd6e 114 "fdt_addr_r=0x80f80000\0" \
25374bfb 115 "usbtty=cdc_acm\0" \
a33e3c79 116 "bootfile=uImage\0" \
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117 "ramdisk=ramdisk.gz\0" \
118 "bootdir=/boot\0" \
119 "bootpart=0:2\0" \
27b8c8f2 120 "console=ttyO2,115200n8\0" \
f6e593bb 121 "mpurate=auto\0" \
847b83d0 122 "buddy=none\0" \
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123 "optargs=\0" \
124 "camera=none\0" \
13d2cb98 125 "vram=12M\0" \
f4b36ea9 126 "dvimode=640x480MR-16@60\0" \
13d2cb98 127 "defaultdisplay=dvi\0" \
0cd31144 128 "mmcdev=0\0" \
13d2cb98
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129 "mmcroot=/dev/mmcblk0p2 rw\0" \
130 "mmcrootfstype=ext3 rootwait\0" \
3c6e50d7
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131 "nandroot=ubi0:rootfs ubi.mtd=4\0" \
132 "nandrootfstype=ubifs\0" \
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133 "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=0x81000000,64M\0" \
134 "ramrootfstype=ext2\0" \
f904cdbb 135 "mmcargs=setenv bootargs console=${console} " \
c522eac4 136 "${optargs} " \
5af32460 137 "mpurate=${mpurate} " \
b1660314 138 "buddy=${buddy} "\
c522eac4 139 "camera=${camera} "\
13d2cb98
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140 "vram=${vram} " \
141 "omapfb.mode=dvi:${dvimode} " \
13d2cb98
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142 "omapdss.def_disp=${defaultdisplay} " \
143 "root=${mmcroot} " \
144 "rootfstype=${mmcrootfstype}\0" \
f904cdbb 145 "nandargs=setenv bootargs console=${console} " \
c522eac4 146 "${optargs} " \
5af32460 147 "mpurate=${mpurate} " \
b1660314 148 "buddy=${buddy} "\
c522eac4 149 "camera=${camera} "\
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150 "vram=${vram} " \
151 "omapfb.mode=dvi:${dvimode} " \
13d2cb98
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152 "omapdss.def_disp=${defaultdisplay} " \
153 "root=${nandroot} " \
154 "rootfstype=${nandrootfstype}\0" \
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155 "findfdt=" \
156 "if test $beaglerev = AxBx; then " \
157 "setenv fdtfile omap3-beagle.dtb; fi; " \
158 "if test $beaglerev = Cx; then " \
159 "setenv fdtfile omap3-beagle.dtb; fi; " \
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160 "if test $beaglerev = C4; then " \
161 "setenv fdtfile omap3-beagle.dtb; fi; " \
2ade496f 162 "if test $beaglerev = xMAB; then " \
3d47ffb9 163 "setenv fdtfile omap3-beagle-xm-ab.dtb; fi; " \
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164 "if test $beaglerev = xMC; then " \
165 "setenv fdtfile omap3-beagle-xm.dtb; fi; " \
166 "if test $fdtfile = undefined; then " \
167 "echo WARNING: Could not determine device tree to use; fi; \0" \
4fa2427c
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168 "validatefdt=" \
169 "if test $beaglerev = xMAB; then " \
170 "if test ! -e mmc ${bootpart} ${bootdir}/${fdtfile}; then " \
171 "setenv fdtfile omap3-beagle-xm.dtb; " \
172 "fi; " \
173 "fi; \0" \
f835ea71
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174 "bootenv=uEnv.txt\0" \
175 "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
cf073e49 176 "importbootenv=echo Importing environment from mmc ...; " \
44bd26fa 177 "env import -t -r $loadaddr $filesize\0" \
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178 "ramargs=setenv bootargs console=${console} " \
179 "${optargs} " \
180 "mpurate=${mpurate} " \
181 "buddy=${buddy} "\
182 "vram=${vram} " \
183 "omapfb.mode=dvi:${dvimode} " \
184 "omapdss.def_disp=${defaultdisplay} " \
185 "root=${ramroot} " \
186 "rootfstype=${ramrootfstype}\0" \
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187 "loadramdisk=load mmc ${bootpart} ${rdaddr} ${bootdir}/${ramdisk}\0" \
188 "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
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189 "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \
190 "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
191 "source ${loadaddr}\0" \
4fa2427c 192 "loadfdt=run validatefdt; load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
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193 "mmcboot=echo Booting from mmc ...; " \
194 "run mmcargs; " \
195 "bootm ${loadaddr}\0" \
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196 "mmcbootz=echo Booting with DT from mmc${mmcdev} ...; " \
197 "run mmcargs; " \
198 "bootz ${loadaddr} - ${fdtaddr}\0" \
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199 "nandboot=echo Booting from nand ...; " \
200 "run nandargs; " \
201 "nand read ${loadaddr} 280000 400000; " \
202 "bootm ${loadaddr}\0" \
f4b36ea9
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203 "ramboot=echo Booting from ramdisk ...; " \
204 "run ramargs; " \
205 "bootm ${loadaddr}\0" \
aae58b95
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206 "userbutton=if gpio input 173; then run userbutton_xm; " \
207 "else run userbutton_nonxm; fi;\0" \
208 "userbutton_xm=gpio input 4;\0" \
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209 "userbutton_nonxm=gpio input 7;\0" \
210 BOOTENV
f904cdbb 211
f904cdbb 212/*
d3a513c2
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213 * OMAP3 has 12 GP timers, they can be driven by the system clock
214 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
215 * This rate is divided by a local divisor.
f904cdbb 216 */
d3a513c2 217#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
f904cdbb 218
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219/*-----------------------------------------------------------------------
220 * FLASH and environment organization
221 */
222
223/* **** PISMO SUPPORT *** */
6cbec7b3 224#if defined(CONFIG_CMD_NAND)
222a3113 225#define CONFIG_SYS_FLASH_BASE NAND_BASE
6cbec7b3 226#endif
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227
228/* Monitor at start of flash */
229#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
230#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
231
df4dbb5d 232#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
f904cdbb 233#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
f904cdbb 234
6cbec7b3 235#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
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236#define CONFIG_ENV_OFFSET 0x260000
237#define CONFIG_ENV_ADDR 0x260000
f904cdbb 238
75c57a35 239/* Defines for SPL */
75c57a35
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240
241/* NAND boot config */
242#define CONFIG_SYS_NAND_5_ADDR_CYCLE
243#define CONFIG_SYS_NAND_PAGE_COUNT 64
244#define CONFIG_SYS_NAND_PAGE_SIZE 2048
245#define CONFIG_SYS_NAND_OOBSIZE 64
246#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
247#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
248#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
249 10, 11, 12, 13}
250#define CONFIG_SYS_NAND_ECCSIZE 512
251#define CONFIG_SYS_NAND_ECCBYTES 3
3f719069 252#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
75c57a35 253#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
434f2cfc 254/* NAND: SPL falcon mode configs */
255#ifdef CONFIG_SPL_OS_BOOT
434f2cfc 256#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
434f2cfc 257#endif
75c57a35 258
f904cdbb 259#endif /* __CONFIG_H */