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f904cdbb DB |
1 | /* |
2 | * (C) Copyright 2006-2008 | |
3 | * Texas Instruments. | |
4 | * Richard Woodruff <r-woodruff2@ti.com> | |
5 | * Syed Mohammed Khasim <x0khasim@ti.com> | |
6 | * | |
7 | * Configuration settings for the TI OMAP3530 Beagle board. | |
8 | * | |
3765b3e7 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
f904cdbb DB |
10 | */ |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
f904cdbb | 14 | |
df4dbb5d TR |
15 | #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ |
16 | ||
f904cdbb | 17 | /* |
df4dbb5d TR |
18 | * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM |
19 | * 64 bytes before this address should be set aside for u-boot.img's | |
20 | * header. That is 0x800FFFC0--0x80100000 should not be used for any | |
21 | * other needs. We use this rather than the inherited defines from | |
22 | * ti_armv7_common.h for backwards compatibility. | |
f904cdbb | 23 | */ |
df4dbb5d TR |
24 | #define CONFIG_SYS_TEXT_BASE 0x80100000 |
25 | #define CONFIG_SPL_BSS_START_ADDR 0x80000000 | |
26 | #define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */ | |
27 | #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 | |
28 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 | |
cae377b5 | 29 | |
df4dbb5d | 30 | #include <configs/ti_omap3_common.h> |
f904cdbb | 31 | |
6a6b62e3 SP |
32 | /* |
33 | * Display CPU and Board information | |
34 | */ | |
35 | #define CONFIG_DISPLAY_CPUINFO 1 | |
36 | #define CONFIG_DISPLAY_BOARDINFO 1 | |
37 | ||
f904cdbb DB |
38 | #define CONFIG_MISC_INIT_R |
39 | ||
f904cdbb | 40 | #define CONFIG_REVISION_TAG 1 |
f904cdbb | 41 | #define CONFIG_ENV_OVERWRITE |
f904cdbb | 42 | |
70d8c944 JK |
43 | /* Status LED */ |
44 | #define CONFIG_STATUS_LED 1 | |
45 | #define CONFIG_BOARD_SPECIFIC_LED 1 | |
46 | #define STATUS_LED_BIT 0x01 | |
47 | #define STATUS_LED_STATE STATUS_LED_ON | |
48 | #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) | |
49 | #define STATUS_LED_BIT1 0x02 | |
50 | #define STATUS_LED_STATE1 STATUS_LED_ON | |
51 | #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) | |
52 | #define STATUS_LED_BOOT STATUS_LED_BIT | |
53 | #define STATUS_LED_GREEN STATUS_LED_BIT1 | |
54 | ||
f74fc4ae JK |
55 | /* Enable Multi Bus support for I2C */ |
56 | #define CONFIG_I2C_MULTI_BUS 1 | |
57 | ||
58 | /* Probe all devices */ | |
8c4e0ca6 | 59 | #define CONFIG_SYS_I2C_NOPROBES {{0x0, 0x0}} |
f74fc4ae | 60 | |
25374bfb | 61 | /* USB */ |
c2af345e | 62 | #define CONFIG_USB_MUSB_OMAP2PLUS |
95de1e2f | 63 | #define CONFIG_USB_MUSB_PIO_ONLY |
25374bfb | 64 | #define CONFIG_TWL4030_USB 1 |
c642b151 IY |
65 | #define CONFIG_USB_ETHER |
66 | #define CONFIG_USB_ETHER_RNDIS | |
17da3c0c | 67 | #define CONFIG_USB_FUNCTION_FASTBOOT |
dd5b68fb RH |
68 | #define CONFIG_CMD_FASTBOOT |
69 | #define CONFIG_ANDROID_BOOT_IMAGE | |
a588d99a PK |
70 | #define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR |
71 | #define CONFIG_FASTBOOT_BUF_SIZE 0x07000000 | |
25374bfb | 72 | |
d90859a6 | 73 | /* USB EHCI */ |
d90859a6 | 74 | #define CONFIG_USB_EHCI |
928c4bdf | 75 | |
29321c05 | 76 | #define CONFIG_USB_EHCI_OMAP |
29321c05 IY |
77 | #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 147 |
78 | ||
d90859a6 | 79 | #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 |
2162439a | 80 | #define CONFIG_USB_HOST_ETHER |
54b62d59 | 81 | #define CONFIG_USB_ETHER_ASIX |
a743415f | 82 | #define CONFIG_USB_ETHER_MCS7830 |
eddf6d28 | 83 | #define CONFIG_USB_ETHER_SMSC95XX |
2162439a | 84 | |
ce23b18b SR |
85 | /* GPIO banks */ |
86 | #define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */ | |
87 | #define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */ | |
d90859a6 | 88 | |
f904cdbb | 89 | /* commands to include */ |
776bebb7 TR |
90 | #define CONFIG_CMD_ASKENV |
91 | ||
95c6f6d3 | 92 | #define CONFIG_CMD_CACHE |
df4dbb5d | 93 | |
917cfc70 NM |
94 | #define MTDIDS_DEFAULT "nand0=nand" |
95 | #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ | |
96 | "1920k(u-boot),128k(u-boot-env),"\ | |
97 | "4m(kernel),-(fs)" | |
f904cdbb | 98 | |
d90859a6 | 99 | #define CONFIG_USB_STORAGE /* USB storage support */ |
f904cdbb | 100 | #define CONFIG_CMD_NAND /* NAND support */ |
70d8c944 | 101 | #define CONFIG_CMD_LED /* LED support */ |
f904cdbb | 102 | |
25a4d017 | 103 | #define CONFIG_VIDEO_OMAP3 /* DSS Support */ |
f904cdbb | 104 | |
2c155130 TR |
105 | /* |
106 | * TWL4030 | |
107 | */ | |
2c155130 TR |
108 | #define CONFIG_TWL4030_LED 1 |
109 | ||
f904cdbb DB |
110 | /* |
111 | * Board NAND Info. | |
112 | */ | |
113 | #define CONFIG_NAND_OMAP_GPMC | |
f904cdbb DB |
114 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ |
115 | /* devices */ | |
f904cdbb | 116 | |
f904cdbb | 117 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
f4b36ea9 JK |
118 | "loadaddr=0x80200000\0" \ |
119 | "rdaddr=0x81000000\0" \ | |
2ade496f NM |
120 | "fdt_high=0xffffffff\0" \ |
121 | "fdtaddr=0x80f80000\0" \ | |
25374bfb | 122 | "usbtty=cdc_acm\0" \ |
a33e3c79 | 123 | "bootfile=uImage\0" \ |
102ce9ea NM |
124 | "ramdisk=ramdisk.gz\0" \ |
125 | "bootdir=/boot\0" \ | |
126 | "bootpart=0:2\0" \ | |
27b8c8f2 | 127 | "console=ttyO2,115200n8\0" \ |
f6e593bb | 128 | "mpurate=auto\0" \ |
847b83d0 | 129 | "buddy=none\0" \ |
c522eac4 JK |
130 | "optargs=\0" \ |
131 | "camera=none\0" \ | |
13d2cb98 | 132 | "vram=12M\0" \ |
f4b36ea9 | 133 | "dvimode=640x480MR-16@60\0" \ |
13d2cb98 | 134 | "defaultdisplay=dvi\0" \ |
0cd31144 | 135 | "mmcdev=0\0" \ |
13d2cb98 SS |
136 | "mmcroot=/dev/mmcblk0p2 rw\0" \ |
137 | "mmcrootfstype=ext3 rootwait\0" \ | |
3c6e50d7 SS |
138 | "nandroot=ubi0:rootfs ubi.mtd=4\0" \ |
139 | "nandrootfstype=ubifs\0" \ | |
f4b36ea9 JK |
140 | "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=0x81000000,64M\0" \ |
141 | "ramrootfstype=ext2\0" \ | |
f904cdbb | 142 | "mmcargs=setenv bootargs console=${console} " \ |
c522eac4 | 143 | "${optargs} " \ |
5af32460 | 144 | "mpurate=${mpurate} " \ |
b1660314 | 145 | "buddy=${buddy} "\ |
c522eac4 | 146 | "camera=${camera} "\ |
13d2cb98 SS |
147 | "vram=${vram} " \ |
148 | "omapfb.mode=dvi:${dvimode} " \ | |
13d2cb98 SS |
149 | "omapdss.def_disp=${defaultdisplay} " \ |
150 | "root=${mmcroot} " \ | |
151 | "rootfstype=${mmcrootfstype}\0" \ | |
f904cdbb | 152 | "nandargs=setenv bootargs console=${console} " \ |
c522eac4 | 153 | "${optargs} " \ |
5af32460 | 154 | "mpurate=${mpurate} " \ |
b1660314 | 155 | "buddy=${buddy} "\ |
c522eac4 | 156 | "camera=${camera} "\ |
13d2cb98 SS |
157 | "vram=${vram} " \ |
158 | "omapfb.mode=dvi:${dvimode} " \ | |
13d2cb98 SS |
159 | "omapdss.def_disp=${defaultdisplay} " \ |
160 | "root=${nandroot} " \ | |
161 | "rootfstype=${nandrootfstype}\0" \ | |
2ade496f NM |
162 | "findfdt=" \ |
163 | "if test $beaglerev = AxBx; then " \ | |
164 | "setenv fdtfile omap3-beagle.dtb; fi; " \ | |
165 | "if test $beaglerev = Cx; then " \ | |
166 | "setenv fdtfile omap3-beagle.dtb; fi; " \ | |
5c9038b6 RN |
167 | "if test $beaglerev = C4; then " \ |
168 | "setenv fdtfile omap3-beagle.dtb; fi; " \ | |
2ade496f | 169 | "if test $beaglerev = xMAB; then " \ |
3d47ffb9 | 170 | "setenv fdtfile omap3-beagle-xm-ab.dtb; fi; " \ |
2ade496f NM |
171 | "if test $beaglerev = xMC; then " \ |
172 | "setenv fdtfile omap3-beagle-xm.dtb; fi; " \ | |
173 | "if test $fdtfile = undefined; then " \ | |
174 | "echo WARNING: Could not determine device tree to use; fi; \0" \ | |
4fa2427c RN |
175 | "validatefdt=" \ |
176 | "if test $beaglerev = xMAB; then " \ | |
177 | "if test ! -e mmc ${bootpart} ${bootdir}/${fdtfile}; then " \ | |
178 | "setenv fdtfile omap3-beagle-xm.dtb; " \ | |
179 | "fi; " \ | |
180 | "fi; \0" \ | |
f835ea71 JK |
181 | "bootenv=uEnv.txt\0" \ |
182 | "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ | |
cf073e49 | 183 | "importbootenv=echo Importing environment from mmc ...; " \ |
44bd26fa | 184 | "env import -t -r $loadaddr $filesize\0" \ |
f4b36ea9 JK |
185 | "ramargs=setenv bootargs console=${console} " \ |
186 | "${optargs} " \ | |
187 | "mpurate=${mpurate} " \ | |
188 | "buddy=${buddy} "\ | |
189 | "vram=${vram} " \ | |
190 | "omapfb.mode=dvi:${dvimode} " \ | |
191 | "omapdss.def_disp=${defaultdisplay} " \ | |
192 | "root=${ramroot} " \ | |
193 | "rootfstype=${ramrootfstype}\0" \ | |
102ce9ea NM |
194 | "loadramdisk=load mmc ${bootpart} ${rdaddr} ${bootdir}/${ramdisk}\0" \ |
195 | "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ | |
09642269 GG |
196 | "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \ |
197 | "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ | |
198 | "source ${loadaddr}\0" \ | |
4fa2427c | 199 | "loadfdt=run validatefdt; load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ |
f904cdbb DB |
200 | "mmcboot=echo Booting from mmc ...; " \ |
201 | "run mmcargs; " \ | |
202 | "bootm ${loadaddr}\0" \ | |
ea70690d NM |
203 | "mmcbootz=echo Booting with DT from mmc${mmcdev} ...; " \ |
204 | "run mmcargs; " \ | |
205 | "bootz ${loadaddr} - ${fdtaddr}\0" \ | |
f904cdbb DB |
206 | "nandboot=echo Booting from nand ...; " \ |
207 | "run nandargs; " \ | |
208 | "nand read ${loadaddr} 280000 400000; " \ | |
209 | "bootm ${loadaddr}\0" \ | |
f4b36ea9 JK |
210 | "ramboot=echo Booting from ramdisk ...; " \ |
211 | "run ramargs; " \ | |
212 | "bootm ${loadaddr}\0" \ | |
aae58b95 JF |
213 | "userbutton=if gpio input 173; then run userbutton_xm; " \ |
214 | "else run userbutton_nonxm; fi;\0" \ | |
215 | "userbutton_xm=gpio input 4;\0" \ | |
216 | "userbutton_nonxm=gpio input 7;\0" | |
d7aff44a | 217 | /* "run userbutton" will return 1 (false) if pressed and 0 (true) if not */ |
f904cdbb | 218 | #define CONFIG_BOOTCOMMAND \ |
2ade496f | 219 | "run findfdt; " \ |
66968110 | 220 | "mmc dev ${mmcdev}; if mmc rescan; then " \ |
aae58b95 JF |
221 | "if run userbutton; then " \ |
222 | "setenv bootenv uEnv.txt;" \ | |
223 | "else " \ | |
f835ea71 JK |
224 | "setenv bootenv user.txt;" \ |
225 | "fi;" \ | |
cf073e49 AH |
226 | "echo SD/MMC found on device ${mmcdev};" \ |
227 | "if run loadbootenv; then " \ | |
f835ea71 | 228 | "echo Loaded environment from ${bootenv};" \ |
cf073e49 AH |
229 | "run importbootenv;" \ |
230 | "fi;" \ | |
231 | "if test -n $uenvcmd; then " \ | |
232 | "echo Running uenvcmd ...;" \ | |
233 | "run uenvcmd;" \ | |
234 | "fi;" \ | |
09642269 GG |
235 | "if run loadbootscript; then " \ |
236 | "run bootscript; " \ | |
237 | "else " \ | |
238 | "if run loadimage; then " \ | |
239 | "run mmcboot;" \ | |
240 | "fi;" \ | |
241 | "fi; " \ | |
cf073e49 AH |
242 | "fi;" \ |
243 | "run nandboot;" \ | |
ea70690d NM |
244 | "setenv bootfile zImage;" \ |
245 | "if run loadimage; then " \ | |
246 | "run loadfdt;" \ | |
247 | "run mmcbootz; " \ | |
248 | "fi; " \ | |
f904cdbb | 249 | |
f904cdbb | 250 | /* |
d3a513c2 MP |
251 | * OMAP3 has 12 GP timers, they can be driven by the system clock |
252 | * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). | |
253 | * This rate is divided by a local divisor. | |
f904cdbb | 254 | */ |
d3a513c2 | 255 | #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ |
f904cdbb | 256 | |
f904cdbb DB |
257 | /*----------------------------------------------------------------------- |
258 | * FLASH and environment organization | |
259 | */ | |
260 | ||
261 | /* **** PISMO SUPPORT *** */ | |
6cbec7b3 | 262 | #if defined(CONFIG_CMD_NAND) |
222a3113 | 263 | #define CONFIG_SYS_FLASH_BASE NAND_BASE |
6cbec7b3 | 264 | #endif |
f904cdbb DB |
265 | |
266 | /* Monitor at start of flash */ | |
267 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
268 | #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP | |
269 | ||
270 | #define CONFIG_ENV_IS_IN_NAND 1 | |
df4dbb5d | 271 | #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ |
f904cdbb DB |
272 | #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ |
273 | #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ | |
274 | ||
6cbec7b3 LC |
275 | #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ |
276 | #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET | |
f904cdbb DB |
277 | #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET |
278 | ||
53736baa DB |
279 | #define CONFIG_OMAP3_SPI |
280 | ||
8e40852f A |
281 | #define CONFIG_SYS_CACHELINE_SIZE 64 |
282 | ||
75c57a35 | 283 | /* Defines for SPL */ |
75c57a35 | 284 | #define CONFIG_SPL_OMAP3_ID_NAND |
75c57a35 TR |
285 | |
286 | /* NAND boot config */ | |
55f1b39f | 287 | #define CONFIG_SYS_NAND_BUSWIDTH_16BIT |
75c57a35 TR |
288 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE |
289 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 | |
290 | #define CONFIG_SYS_NAND_PAGE_SIZE 2048 | |
291 | #define CONFIG_SYS_NAND_OOBSIZE 64 | |
292 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) | |
293 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 | |
294 | #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ | |
295 | 10, 11, 12, 13} | |
296 | #define CONFIG_SYS_NAND_ECCSIZE 512 | |
297 | #define CONFIG_SYS_NAND_ECCBYTES 3 | |
3f719069 | 298 | #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW |
75c57a35 | 299 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 |
434f2cfc | 300 | /* NAND: SPL falcon mode configs */ |
301 | #ifdef CONFIG_SPL_OS_BOOT | |
302 | #define CONFIG_CMD_SPL_NAND_OFS 0x240000 | |
303 | #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 | |
304 | #define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 | |
305 | #endif | |
75c57a35 | 306 | |
f904cdbb | 307 | #endif /* __CONFIG_H */ |