[people/ms/u-boot.git] / include / configs / r0p7734.h

/*
 * Configuation settings for the Renesas Solutions r0p7734 board
 *
 * Copyright (C) 2010, 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __R0P7734_H
#define __R0P7734_H

#define CONFIG_CPU_SH7734	1
#define CONFIG_R0P7734		1
#define CONFIG_400MHZ_MODE	1
/* #define CONFIG_533MHZ_MODE	1 */

#define CONFIG_SYS_TEXT_BASE 0x8FFC0000

#define CONFIG_DISPLAY_BOARDINFO
#undef  CONFIG_SHOW_BOOT_PROGRESS

/* Ether */
#define CONFIG_SH_ETHER 1
#define CONFIG_SH_ETHER_USE_PORT (0)
#define CONFIG_SH_ETHER_PHY_ADDR (0x0)
#define CONFIG_PHY_SMSC 1
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
#define CONFIG_SH_ETHER_SH7734_MII (0x00) /* MII */
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
#ifndef CONFIG_SH_ETHER
# define CONFIG_SMC911X
# define CONFIG_SMC911X_16_BIT
# define CONFIG_SMC911X_BASE (0x84000000)
#endif

/* undef to save memory	*/
#define CONFIG_SYS_LONGHELP
/* Buffer size for Boot Arguments passed to kernel */
#define CONFIG_SYS_BARGSIZE	512
/* List of legal baudrate settings for this board */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }

/* SCIF */
#define CONFIG_SCIF			1
#define CONFIG_CONS_SCIF3	1

/* Suppress display of console information at boot */

/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE	(0x88000000)
#define CONFIG_SYS_SDRAM_SIZE	(128 * 1024 * 1024)
#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)

#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END	 (CONFIG_SYS_MEMTEST_START + 100 * 1024 * 1024)
/* Enable alternate, more extensive, memory test */
#undef  CONFIG_SYS_ALT_MEMTEST
/* Scratch address used by the alternate memory test */
#undef  CONFIG_SYS_MEMTEST_SCRATCH

/* Enable temporary baudrate change while serial download */
#undef  CONFIG_SYS_LOADS_BAUD_CHANGE

/* FLASH */
#define CONFIG_FLASH_CFI_DRIVER 1
#define CONFIG_SYS_FLASH_CFI
#undef  CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BASE	(0xA0000000)
#define CONFIG_SYS_MAX_FLASH_SECT	512

/* if you use all NOR Flash , you change dip-switch. Please see Manual. */
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }

/* Timeout for Flash erase operations (in ms) */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)
/* Timeout for Flash write operations (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)
/* Timeout for Flash set sector lock bit operations (in ms) */
#define CONFIG_SYS_FLASH_LOCK_TOUT	(3 * 1000)
/* Timeout for Flash clear lock bit operations (in ms) */
#define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)

/*
 * Use hardware flash sectors protection instead
 * of U-Boot software protection
 */
#undef  CONFIG_SYS_FLASH_PROTECTION
#undef  CONFIG_SYS_DIRECT_FLASH_TFTP

/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE)
/* Monitor size */
#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
/* Size of DRAM reserved for malloc() use */
#define CONFIG_SYS_MALLOC_LEN	(256 * 1024)
#define CONFIG_SYS_BOOTMAPSZ	(8 * 1024 * 1024)

/* ENV setting */
#define CONFIG_ENV_OVERWRITE	1
#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
#define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)

/* Board Clock */
#if defined(CONFIG_400MHZ_MODE)
#define CONFIG_SYS_CLK_FREQ 50000000
#else
#define CONFIG_SYS_CLK_FREQ 44444444
#endif
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV      4

#endif	/* __R0P7734_H */
Commit	Line	Data
8ca805e1 NI	1	/*
	2	* Configuation settings for the Renesas Solutions r0p7734 board
	3	*
	4	* Copyright (C) 2010, 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
8ca805e1 NI	7	*/
	8
	9	#ifndef __R0P7734_H
	10	#define __R0P7734_H
	11
8ca805e1 NI	12	#define CONFIG_CPU_SH7734 1
	13	#define CONFIG_R0P7734 1
	14	#define CONFIG_400MHZ_MODE 1
	15	/* #define CONFIG_533MHZ_MODE 1 */
	16
	17	#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
	18
18a40e84	19	#define CONFIG_DISPLAY_BOARDINFO
8ca805e1 NI	20	#undef CONFIG_SHOW_BOOT_PROGRESS
	21
	22	/* Ether */
	23	#define CONFIG_SH_ETHER 1
	24	#define CONFIG_SH_ETHER_USE_PORT (0)
	25	#define CONFIG_SH_ETHER_PHY_ADDR (0x0)
8ca805e1 NI	26	#define CONFIG_PHY_SMSC 1
	27	#define CONFIG_BITBANGMII
	28	#define CONFIG_BITBANGMII_MULTI
a80a6619 NI	29	#define CONFIG_SH_ETHER_SH7734_MII (0x00) /* MII */
a80a6619 NI	30	#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
8ca805e1 NI	31	#ifndef CONFIG_SH_ETHER
	32	# define CONFIG_SMC911X
	33	# define CONFIG_SMC911X_16_BIT
	34	# define CONFIG_SMC911X_BASE (0x84000000)
	35	#endif
	36
	37	/* undef to save memory */
	38	#define CONFIG_SYS_LONGHELP
8ca805e1 NI	39	/* Buffer size for Boot Arguments passed to kernel */
	40	#define CONFIG_SYS_BARGSIZE 512
	41	/* List of legal baudrate settings for this board */
	42	#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
	43
	44	/* SCIF */
8ca805e1 NI	45	#define CONFIG_SCIF 1
	46	#define CONFIG_CONS_SCIF3 1
	47
	48	/* Suppress display of console information at boot */
8ca805e1 NI	49
	50	/* SDRAM */
	51	#define CONFIG_SYS_SDRAM_BASE (0x88000000)
	52	#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)
	53	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
	54
	55	#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
	56	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 100 * 1024 * 1024)
	57	/* Enable alternate, more extensive, memory test */
	58	#undef CONFIG_SYS_ALT_MEMTEST
	59	/* Scratch address used by the alternate memory test */
	60	#undef CONFIG_SYS_MEMTEST_SCRATCH
	61
	62	/* Enable temporary baudrate change while serial download */
	63	#undef CONFIG_SYS_LOADS_BAUD_CHANGE
	64
	65	/* FLASH */
	66	#define CONFIG_FLASH_CFI_DRIVER 1
	67	#define CONFIG_SYS_FLASH_CFI
	68	#undef CONFIG_SYS_FLASH_QUIET_TEST
	69	#define CONFIG_SYS_FLASH_EMPTY_INFO
	70	#define CONFIG_SYS_FLASH_BASE (0xA0000000)
	71	#define CONFIG_SYS_MAX_FLASH_SECT 512
	72
	73	/* if you use all NOR Flash , you change dip-switch. Please see Manual. */
	74	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	75	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
	76
	77	/* Timeout for Flash erase operations (in ms) */
	78	#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
	79	/* Timeout for Flash write operations (in ms) */
	80	#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
	81	/* Timeout for Flash set sector lock bit operations (in ms) */
	82	#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
	83	/* Timeout for Flash clear lock bit operations (in ms) */
	84	#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
	85
	86	/*
	87	* Use hardware flash sectors protection instead
	88	* of U-Boot software protection
	89	*/
	90	#undef CONFIG_SYS_FLASH_PROTECTION
	91	#undef CONFIG_SYS_DIRECT_FLASH_TFTP
	92
	93	/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
	94	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
	95	/* Monitor size */
	96	#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
	97	/* Size of DRAM reserved for malloc() use */
	98	#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
8ca805e1 NI	99	#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
	100
	101	/* ENV setting */
8ca805e1 NI	102	#define CONFIG_ENV_OVERWRITE 1
	103	#define CONFIG_ENV_SECT_SIZE (128 * 1024)
	104	#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
	105	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
	106	/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
	107	#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
	108	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
	109
	110	/* Board Clock */
	111	#if defined(CONFIG_400MHZ_MODE)
	112	#define CONFIG_SYS_CLK_FREQ 50000000
	113	#else
	114	#define CONFIG_SYS_CLK_FREQ 44444444
	115	#endif
684a501e NI	116	#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
684a501e NI	117	#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
8ca805e1	118	#define CONFIG_SYS_TMU_CLK_DIV 4
8ca805e1 NI	119
8ca805e1 NI	120	#endif /* __R0P7734_H */