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a381bcf5 KY |
1 | /* |
2 | * (C) Copyright 2016 Rockchip Electronics Co., Ltd | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #ifndef __CONFIG_RK3399_COMMON_H | |
8 | #define __CONFIG_RK3399_COMMON_H | |
9 | ||
7f35bbb9 JC |
10 | #include "rockchip-common.h" |
11 | ||
a381bcf5 KY |
12 | #define CONFIG_NR_DRAM_BANKS 1 |
13 | #define CONFIG_ENV_SIZE 0x2000 | |
a381bcf5 KY |
14 | #define CONFIG_SYS_MALLOC_LEN (32 << 20) |
15 | #define CONFIG_SYS_CBSIZE 1024 | |
16 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
66e87cc8 | 17 | #define CONFIG_SPL_FRAMEWORK |
3e75c07d PT |
18 | #if defined(CONFIG_SPL_SPI_SUPPORT) |
19 | #define CONFIG_SPL_SPI_LOAD | |
20 | #endif | |
a381bcf5 | 21 | |
88cb1a9e PT |
22 | #define COUNTER_FREQUENCY 24000000 |
23 | ||
a381bcf5 KY |
24 | #define CONFIG_SYS_NS16550_MEM32 |
25 | ||
26 | #define CONFIG_SYS_TEXT_BASE 0x00200000 | |
27 | #define CONFIG_SYS_INIT_SP_ADDR 0x00300000 | |
28 | #define CONFIG_SYS_LOAD_ADDR 0x00800800 | |
3012a840 | 29 | #define CONFIG_SPL_STACK 0xff8effff |
3d54eabc | 30 | #define CONFIG_SPL_TEXT_BASE 0xff8c2000 |
5302feb6 | 31 | #define CONFIG_SPL_MAX_SIZE 0x30000 - 0x2000 |
3012a840 KY |
32 | /* BSS setup */ |
33 | #define CONFIG_SPL_BSS_START_ADDR 0xff8e0000 | |
34 | #define CONFIG_SPL_BSS_MAX_SIZE 0x10000 | |
a381bcf5 KY |
35 | |
36 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ | |
37 | ||
38 | /* MMC/SD IP block */ | |
a381bcf5 KY |
39 | #define CONFIG_BOUNCE_BUFFER |
40 | #define CONFIG_ROCKCHIP_SDHCI_MAX_FREQ 200000000 | |
41 | ||
583b1bc0 | 42 | #define CONFIG_SUPPORT_VFAT |
583b1bc0 | 43 | #define CONFIG_FS_EXT4 |
a381bcf5 KY |
44 | |
45 | /* RAW SD card / eMMC locations. */ | |
a381bcf5 KY |
46 | #define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10) |
47 | ||
48 | /* FAT sd card locations. */ | |
49 | #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 | |
50 | #define CONFIG_SYS_SDRAM_BASE 0 | |
6d1970fa | 51 | #define SDRAM_MAX_SIZE 0xf8000000 |
a381bcf5 KY |
52 | #define CONFIG_NR_DRAM_BANKS 1 |
53 | ||
a381bcf5 KY |
54 | #define CONFIG_SF_DEFAULT_SPEED 20000000 |
55 | ||
56 | #ifndef CONFIG_SPL_BUILD | |
a381bcf5 KY |
57 | |
58 | #define ENV_MEM_LAYOUT_SETTINGS \ | |
86d01265 KY |
59 | "scriptaddr=0x00500000\0" \ |
60 | "pxefile_addr_r=0x00600000\0" \ | |
a381bcf5 KY |
61 | "fdt_addr_r=0x01f00000\0" \ |
62 | "kernel_addr_r=0x02000000\0" \ | |
63 | "ramdisk_addr_r=0x04000000\0" | |
64 | ||
a381bcf5 KY |
65 | #include <config_distro_bootcmd.h> |
66 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
583b1bc0 KY |
67 | ENV_MEM_LAYOUT_SETTINGS \ |
68 | "partitions=" PARTS_DEFAULT \ | |
a381bcf5 KY |
69 | BOOTENV |
70 | ||
71 | #endif | |
72 | ||
923e7b44 M |
73 | /* enable usb config for usb ether */ |
74 | #define CONFIG_USB_HOST_ETHER | |
75 | ||
76 | #define CONFIG_USB_ETHER_ASIX | |
77 | #define CONFIG_USB_ETHER_ASIX88179 | |
78 | #define CONFIG_USB_ETHER_MCS7830 | |
79 | #define CONFIG_USB_ETHER_SMSC95XX | |
80 | #define CONFIG_USB_ETHER_RTL8152 | |
81 | ||
a381bcf5 | 82 | #endif |