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Commit | Line | Data |
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91e25769 PG |
1 | /* |
2 | * WindRiver SBC8349 U-Boot configuration file. | |
3 | * Copyright (c) 2006, 2007 Wind River Systems, Inc. | |
4 | * | |
5 | * Paul Gortmaker <paul.gortmaker@windriver.com> | |
6 | * Based on the MPC8349EMDS config. | |
7 | * | |
3765b3e7 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
91e25769 PG |
9 | */ |
10 | ||
11 | /* | |
12 | * sbc8349 board configuration file. | |
13 | */ | |
14 | ||
15 | #ifndef __CONFIG_H | |
16 | #define __CONFIG_H | |
17 | ||
fdfaa29e KP |
18 | #define CONFIG_DISPLAY_BOARDINFO |
19 | ||
91e25769 PG |
20 | /* |
21 | * High Level Configuration Options | |
22 | */ | |
23 | #define CONFIG_E300 1 /* E300 Family */ | |
2c7920af | 24 | #define CONFIG_MPC834x 1 /* MPC834x family */ |
91e25769 PG |
25 | #define CONFIG_MPC8349 1 /* MPC8349 specific */ |
26 | #define CONFIG_SBC8349 1 /* WRS SBC8349 board specific */ | |
27 | ||
2ae18241 WD |
28 | #define CONFIG_SYS_TEXT_BASE 0xFF800000 |
29 | ||
91e25769 PG |
30 | /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */ |
31 | #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ | |
32 | ||
c0d660fb PG |
33 | /* |
34 | * The default if PCI isn't enabled, or if no PCI clk setting is given | |
35 | * is 66MHz; this is what the board defaults to when the PCI slot is | |
36 | * physically empty. The board will automatically (i.e w/o jumpers) | |
37 | * clock down to 33MHz if you insert a 33MHz PCI card. | |
38 | */ | |
2ae18241 | 39 | #ifdef CONFIG_PCI_33M |
91e25769 | 40 | #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ |
c0d660fb PG |
41 | #else /* 66M */ |
42 | #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ | |
91e25769 PG |
43 | #endif |
44 | ||
45 | #ifndef CONFIG_SYS_CLK_FREQ | |
2ae18241 | 46 | #ifdef CONFIG_PCI_33M |
91e25769 PG |
47 | #define CONFIG_SYS_CLK_FREQ 33000000 |
48 | #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 | |
c0d660fb PG |
49 | #else /* 66M */ |
50 | #define CONFIG_SYS_CLK_FREQ 66000000 | |
51 | #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 | |
91e25769 PG |
52 | #endif |
53 | #endif | |
54 | ||
91e25769 PG |
55 | #undef CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ |
56 | ||
6d0f6bcf | 57 | #define CONFIG_SYS_IMMR 0xE0000000 |
91e25769 | 58 | |
60e1dc15 | 59 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
6d0f6bcf JCPV |
60 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ |
61 | #define CONFIG_SYS_MEMTEST_END 0x00100000 | |
91e25769 PG |
62 | |
63 | /* | |
64 | * DDR Setup | |
65 | */ | |
66 | #undef CONFIG_DDR_ECC /* only for ECC DDR module */ | |
67 | #undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ | |
68 | #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ | |
60e1dc15 | 69 | #define CONFIG_SYS_83XX_DDR_USES_CS0 /* WRS; Fsl board uses CS2/CS3 */ |
91e25769 PG |
70 | |
71 | /* | |
72 | * 32-bit data path mode. | |
73 | * | |
74 | * Please note that using this mode for devices with the real density of 64-bit | |
75 | * effectively reduces the amount of available memory due to the effect of | |
76 | * wrapping around while translating address to row/columns, for example in the | |
77 | * 256MB module the upper 128MB get aliased with contents of the lower | |
78 | * 128MB); normally this define should be used for devices with real 32-bit | |
79 | * data path. | |
80 | */ | |
81 | #undef CONFIG_DDR_32BIT | |
82 | ||
60e1dc15 | 83 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ |
6d0f6bcf JCPV |
84 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE |
85 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
86 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ | |
91e25769 PG |
87 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) |
88 | #define CONFIG_DDR_2T_TIMING | |
89 | ||
90 | #if defined(CONFIG_SPD_EEPROM) | |
91 | /* | |
92 | * Determine DDR configuration from I2C interface. | |
93 | */ | |
94 | #define SPD_EEPROM_ADDRESS 0x52 /* DDR DIMM */ | |
95 | ||
96 | #else | |
97 | /* | |
98 | * Manually set up DDR parameters | |
99 | * NB: manual DDR setup untested on sbc834x | |
100 | */ | |
6d0f6bcf | 101 | #define CONFIG_SYS_DDR_SIZE 256 /* MB */ |
2e651b24 | 102 | #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \ |
60e1dc15 JH |
103 | | CSCONFIG_ROW_BIT_13 \ |
104 | | CSCONFIG_COL_BIT_10) | |
6d0f6bcf JCPV |
105 | #define CONFIG_SYS_DDR_TIMING_1 0x36332321 |
106 | #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ | |
60e1dc15 | 107 | #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ |
6d0f6bcf | 108 | #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ |
91e25769 PG |
109 | |
110 | #if defined(CONFIG_DDR_32BIT) | |
111 | /* set burst length to 8 for 32-bit data path */ | |
60e1dc15 JH |
112 | /* DLL,normal,seq,4/2.5, 8 burst len */ |
113 | #define CONFIG_SYS_DDR_MODE 0x00000023 | |
91e25769 PG |
114 | #else |
115 | /* the default burst length is 4 - for 64-bit data path */ | |
60e1dc15 JH |
116 | /* DLL,normal,seq,4/2.5, 4 burst len */ |
117 | #define CONFIG_SYS_DDR_MODE 0x00000022 | |
91e25769 PG |
118 | #endif |
119 | #endif | |
120 | ||
121 | /* | |
122 | * SDRAM on the Local Bus | |
123 | */ | |
7d6a0982 JH |
124 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ |
125 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ | |
91e25769 PG |
126 | |
127 | /* | |
128 | * FLASH on the Local Bus | |
129 | */ | |
60e1dc15 JH |
130 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
131 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ | |
6d0f6bcf JCPV |
132 | #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */ |
133 | #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ | |
134 | /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ | |
91e25769 | 135 | |
7d6a0982 JH |
136 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ |
137 | | BR_PS_16 /* 16 bit port */ \ | |
138 | | BR_MS_GPCM /* MSEL = GPCM */ \ | |
139 | | BR_V) /* valid */ | |
140 | ||
141 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | |
142 | | OR_GPCM_XAM \ | |
143 | | OR_GPCM_CSNT \ | |
144 | | OR_GPCM_ACS_DIV2 \ | |
145 | | OR_GPCM_XACS \ | |
146 | | OR_GPCM_SCY_15 \ | |
147 | | OR_GPCM_TRLX_SET \ | |
148 | | OR_GPCM_EHTR_SET \ | |
149 | | OR_GPCM_EAD) | |
150 | /* 0xFF806FF7 */ | |
91e25769 | 151 | |
60e1dc15 JH |
152 | /* window base at flash base */ |
153 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE | |
7d6a0982 | 154 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) |
91e25769 | 155 | |
60e1dc15 JH |
156 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
157 | #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ | |
91e25769 | 158 | |
6d0f6bcf JCPV |
159 | #undef CONFIG_SYS_FLASH_CHECKSUM |
160 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
161 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
91e25769 | 162 | |
14d0a02a | 163 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
91e25769 | 164 | |
6d0f6bcf JCPV |
165 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
166 | #define CONFIG_SYS_RAMBOOT | |
91e25769 | 167 | #else |
6d0f6bcf | 168 | #undef CONFIG_SYS_RAMBOOT |
91e25769 PG |
169 | #endif |
170 | ||
6d0f6bcf | 171 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
60e1dc15 JH |
172 | /* Initial RAM address */ |
173 | #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 | |
174 | /* Size of used area in RAM*/ | |
175 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 | |
91e25769 | 176 | |
60e1dc15 JH |
177 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
178 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
6d0f6bcf | 179 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
91e25769 | 180 | |
60e1dc15 | 181 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
c8a90646 | 182 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ |
91e25769 PG |
183 | |
184 | /* | |
185 | * Local Bus LCRR and LBCR regs | |
186 | * LCRR: DLL bypass, Clock divider is 4 | |
187 | * External Local Bus rate is | |
188 | * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV | |
189 | */ | |
c7190f02 KP |
190 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
191 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 | |
6d0f6bcf | 192 | #define CONFIG_SYS_LBC_LBCR 0x00000000 |
91e25769 | 193 | |
6d0f6bcf | 194 | #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ |
91e25769 | 195 | |
6d0f6bcf | 196 | #ifdef CONFIG_SYS_LB_SDRAM |
91e25769 PG |
197 | /* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/ |
198 | /* | |
199 | * Base Register 2 and Option Register 2 configure SDRAM. | |
6d0f6bcf | 200 | * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. |
91e25769 PG |
201 | * |
202 | * For BR2, need: | |
203 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 | |
204 | * port-size = 32-bits = BR2[19:20] = 11 | |
205 | * no parity checking = BR2[21:22] = 00 | |
206 | * SDRAM for MSEL = BR2[24:26] = 011 | |
207 | * Valid = BR[31] = 1 | |
208 | * | |
209 | * 0 4 8 12 16 20 24 28 | |
210 | * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 | |
91e25769 PG |
211 | */ |
212 | ||
7d6a0982 JH |
213 | #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \ |
214 | | BR_PS_32 \ | |
215 | | BR_MS_SDRAM \ | |
216 | | BR_V) | |
217 | /* 0xF0001861 */ | |
218 | #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE | |
219 | #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) | |
91e25769 PG |
220 | |
221 | /* | |
6d0f6bcf | 222 | * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. |
91e25769 PG |
223 | * |
224 | * For OR2, need: | |
225 | * 64MB mask for AM, OR2[0:7] = 1111 1100 | |
226 | * XAM, OR2[17:18] = 11 | |
227 | * 9 columns OR2[19-21] = 010 | |
228 | * 13 rows OR2[23-25] = 100 | |
229 | * EAD set for extra time OR[31] = 1 | |
230 | * | |
231 | * 0 4 8 12 16 20 24 28 | |
232 | * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 | |
233 | */ | |
234 | ||
7d6a0982 JH |
235 | #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \ |
236 | | OR_SDRAM_XAM \ | |
237 | | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \ | |
238 | | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \ | |
239 | | OR_SDRAM_EAD) | |
240 | /* 0xFC006901 */ | |
91e25769 | 241 | |
60e1dc15 JH |
242 | /* LB sdram refresh timer, about 6us */ |
243 | #define CONFIG_SYS_LBC_LSRT 0x32000000 | |
244 | /* LB refresh timer prescal, 266MHz/32 */ | |
245 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 | |
91e25769 | 246 | |
60e1dc15 JH |
247 | #define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \ |
248 | | LSDMR_BSMA1516 \ | |
249 | | LSDMR_RFCR8 \ | |
250 | | LSDMR_PRETOACT6 \ | |
251 | | LSDMR_ACTTORW3 \ | |
252 | | LSDMR_BL8 \ | |
253 | | LSDMR_WRC3 \ | |
254 | | LSDMR_CL3) | |
91e25769 PG |
255 | |
256 | /* | |
257 | * SDRAM Controller configuration sequence. | |
258 | */ | |
540dcf1c KG |
259 | #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) |
260 | #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) | |
261 | #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) | |
262 | #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) | |
263 | #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) | |
91e25769 PG |
264 | #endif |
265 | ||
266 | /* | |
267 | * Serial Port | |
268 | */ | |
269 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
270 | #define CONFIG_SYS_NS16550_SERIAL |
271 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
272 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
91e25769 | 273 | |
6d0f6bcf | 274 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
60e1dc15 | 275 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
91e25769 | 276 | |
6d0f6bcf JCPV |
277 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
278 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) | |
91e25769 | 279 | |
22d71a71 | 280 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
a059e90e | 281 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
91e25769 | 282 | /* Use the HUSH parser */ |
6d0f6bcf | 283 | #define CONFIG_SYS_HUSH_PARSER |
91e25769 | 284 | |
91e25769 | 285 | /* I2C */ |
00f792e0 HS |
286 | #define CONFIG_SYS_I2C |
287 | #define CONFIG_SYS_I2C_FSL | |
288 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
289 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
290 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
291 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
292 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
293 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
294 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69}, {1, 0x69} } | |
efaf6f1b | 295 | /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ |
91e25769 PG |
296 | |
297 | /* TSEC */ | |
6d0f6bcf | 298 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
60e1dc15 | 299 | #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) |
6d0f6bcf | 300 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 |
60e1dc15 | 301 | #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) |
91e25769 PG |
302 | |
303 | /* | |
304 | * General PCI | |
305 | * Addresses are mapped 1-1. | |
306 | */ | |
6d0f6bcf JCPV |
307 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
308 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
309 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
310 | #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 | |
311 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE | |
312 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
60e1dc15 JH |
313 | #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 |
314 | #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 | |
315 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ | |
6d0f6bcf JCPV |
316 | |
317 | #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 | |
318 | #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE | |
319 | #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ | |
320 | #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 | |
321 | #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE | |
322 | #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ | |
60e1dc15 JH |
323 | #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 |
324 | #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 | |
325 | #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ | |
91e25769 PG |
326 | |
327 | #if defined(CONFIG_PCI) | |
328 | ||
329 | #define PCI_64BIT | |
330 | #define PCI_ONE_PCI1 | |
331 | #if defined(PCI_64BIT) | |
332 | #undef PCI_ALL_PCI1 | |
333 | #undef PCI_TWO_PCI1 | |
334 | #undef PCI_ONE_PCI1 | |
335 | #endif | |
336 | ||
91e25769 PG |
337 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
338 | ||
339 | #undef CONFIG_EEPRO100 | |
340 | #undef CONFIG_TULIP | |
341 | ||
342 | #if !defined(CONFIG_PCI_PNP) | |
343 | #define PCI_ENET0_IOADDR 0xFIXME | |
344 | #define PCI_ENET0_MEMADDR 0xFIXME | |
345 | #define PCI_IDSEL_NUMBER 0xFIXME | |
346 | #endif | |
347 | ||
348 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
6d0f6bcf | 349 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ |
91e25769 PG |
350 | |
351 | #endif /* CONFIG_PCI */ | |
352 | ||
353 | /* | |
354 | * TSEC configuration | |
355 | */ | |
356 | #define CONFIG_TSEC_ENET /* TSEC ethernet support */ | |
357 | ||
358 | #if defined(CONFIG_TSEC_ENET) | |
91e25769 | 359 | |
255a3577 KP |
360 | #define CONFIG_TSEC1 1 |
361 | #define CONFIG_TSEC1_NAME "TSEC0" | |
362 | #define CONFIG_TSEC2 1 | |
363 | #define CONFIG_TSEC2_NAME "TSEC1" | |
91e25769 PG |
364 | #define CONFIG_PHY_BCM5421S 1 |
365 | #define TSEC1_PHY_ADDR 0x19 | |
366 | #define TSEC2_PHY_ADDR 0x1a | |
367 | #define TSEC1_PHYIDX 0 | |
368 | #define TSEC2_PHYIDX 0 | |
3a79013e AF |
369 | #define TSEC1_FLAGS TSEC_GIGABIT |
370 | #define TSEC2_FLAGS TSEC_GIGABIT | |
91e25769 PG |
371 | |
372 | /* Options are: TSEC[0-1] */ | |
373 | #define CONFIG_ETHPRIME "TSEC0" | |
374 | ||
375 | #endif /* CONFIG_TSEC_ENET */ | |
376 | ||
377 | /* | |
378 | * Environment | |
379 | */ | |
6d0f6bcf | 380 | #ifndef CONFIG_SYS_RAMBOOT |
5a1aceb0 | 381 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 382 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) |
0e8d1586 JCPV |
383 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
384 | #define CONFIG_ENV_SIZE 0x2000 | |
91e25769 PG |
385 | |
386 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
387 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
388 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
91e25769 PG |
389 | |
390 | #else | |
60e1dc15 | 391 | #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ |
93f6d725 | 392 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
6d0f6bcf | 393 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 394 | #define CONFIG_ENV_SIZE 0x2000 |
91e25769 PG |
395 | #endif |
396 | ||
397 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 398 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
91e25769 | 399 | |
866e3089 | 400 | |
079a136c JL |
401 | /* |
402 | * BOOTP options | |
403 | */ | |
404 | #define CONFIG_BOOTP_BOOTFILESIZE | |
405 | #define CONFIG_BOOTP_BOOTPATH | |
406 | #define CONFIG_BOOTP_GATEWAY | |
407 | #define CONFIG_BOOTP_HOSTNAME | |
408 | ||
409 | ||
866e3089 JL |
410 | /* |
411 | * Command line configuration. | |
412 | */ | |
866e3089 JL |
413 | #define CONFIG_CMD_I2C |
414 | #define CONFIG_CMD_MII | |
415 | #define CONFIG_CMD_PING | |
416 | ||
91e25769 | 417 | #if defined(CONFIG_PCI) |
e496865e | 418 | #define CONFIG_CMD_PCI |
91e25769 | 419 | #endif |
866e3089 | 420 | |
91e25769 PG |
421 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
422 | ||
423 | /* | |
424 | * Miscellaneous configurable options | |
425 | */ | |
6d0f6bcf JCPV |
426 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
427 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
91e25769 | 428 | |
866e3089 | 429 | #if defined(CONFIG_CMD_KGDB) |
60e1dc15 | 430 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
91e25769 | 431 | #else |
60e1dc15 | 432 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
91e25769 PG |
433 | #endif |
434 | ||
60e1dc15 JH |
435 | /* Print Buffer Size */ |
436 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
437 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
438 | /* Boot Argument Buffer Size */ | |
439 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
91e25769 PG |
440 | |
441 | /* | |
442 | * For booting Linux, the board info and command line data | |
9f530d59 | 443 | * have to be in the first 256 MB of memory, since this is |
91e25769 PG |
444 | * the maximum mapped by the Linux kernel during initialization. |
445 | */ | |
60e1dc15 JH |
446 | /* Initial Memory map for Linux*/ |
447 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) | |
91e25769 | 448 | |
6d0f6bcf | 449 | #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ |
91e25769 PG |
450 | |
451 | #if 1 /*528/264*/ | |
6d0f6bcf | 452 | #define CONFIG_SYS_HRCW_LOW (\ |
91e25769 PG |
453 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
454 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
455 | HRCWL_CSB_TO_CLKIN |\ | |
456 | HRCWL_VCO_1X2 |\ | |
457 | HRCWL_CORE_TO_CSB_2X1) | |
458 | #elif 0 /*396/132*/ | |
6d0f6bcf | 459 | #define CONFIG_SYS_HRCW_LOW (\ |
91e25769 PG |
460 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
461 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
462 | HRCWL_CSB_TO_CLKIN |\ | |
463 | HRCWL_VCO_1X4 |\ | |
464 | HRCWL_CORE_TO_CSB_3X1) | |
465 | #elif 0 /*264/132*/ | |
6d0f6bcf | 466 | #define CONFIG_SYS_HRCW_LOW (\ |
91e25769 PG |
467 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
468 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
469 | HRCWL_CSB_TO_CLKIN |\ | |
470 | HRCWL_VCO_1X4 |\ | |
471 | HRCWL_CORE_TO_CSB_2X1) | |
472 | #elif 0 /*132/132*/ | |
6d0f6bcf | 473 | #define CONFIG_SYS_HRCW_LOW (\ |
91e25769 PG |
474 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
475 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
476 | HRCWL_CSB_TO_CLKIN |\ | |
477 | HRCWL_VCO_1X4 |\ | |
478 | HRCWL_CORE_TO_CSB_1X1) | |
479 | #elif 0 /*264/264 */ | |
6d0f6bcf | 480 | #define CONFIG_SYS_HRCW_LOW (\ |
91e25769 PG |
481 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
482 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
483 | HRCWL_CSB_TO_CLKIN |\ | |
484 | HRCWL_VCO_1X4 |\ | |
485 | HRCWL_CORE_TO_CSB_1X1) | |
486 | #endif | |
487 | ||
488 | #if defined(PCI_64BIT) | |
6d0f6bcf | 489 | #define CONFIG_SYS_HRCW_HIGH (\ |
91e25769 PG |
490 | HRCWH_PCI_HOST |\ |
491 | HRCWH_64_BIT_PCI |\ | |
492 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
493 | HRCWH_PCI2_ARBITER_DISABLE |\ | |
494 | HRCWH_CORE_ENABLE |\ | |
495 | HRCWH_FROM_0X00000100 |\ | |
496 | HRCWH_BOOTSEQ_DISABLE |\ | |
497 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
498 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
499 | HRCWH_TSEC1M_IN_GMII |\ | |
60e1dc15 | 500 | HRCWH_TSEC2M_IN_GMII) |
91e25769 | 501 | #else |
6d0f6bcf | 502 | #define CONFIG_SYS_HRCW_HIGH (\ |
91e25769 PG |
503 | HRCWH_PCI_HOST |\ |
504 | HRCWH_32_BIT_PCI |\ | |
505 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
506 | HRCWH_PCI2_ARBITER_ENABLE |\ | |
507 | HRCWH_CORE_ENABLE |\ | |
508 | HRCWH_FROM_0X00000100 |\ | |
509 | HRCWH_BOOTSEQ_DISABLE |\ | |
510 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
511 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
512 | HRCWH_TSEC1M_IN_GMII |\ | |
60e1dc15 | 513 | HRCWH_TSEC2M_IN_GMII) |
91e25769 PG |
514 | #endif |
515 | ||
516 | /* System IO Config */ | |
3c9b1ee1 | 517 | #define CONFIG_SYS_SICRH 0 |
6d0f6bcf | 518 | #define CONFIG_SYS_SICRL SICRL_LDP_A |
91e25769 | 519 | |
6d0f6bcf | 520 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
60e1dc15 JH |
521 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ |
522 | | HID0_ENABLE_INSTRUCTION_CACHE) | |
91e25769 | 523 | |
60e1dc15 | 524 | /* #define CONFIG_SYS_HID0_FINAL (\ |
91e25769 PG |
525 | HID0_ENABLE_INSTRUCTION_CACHE |\ |
526 | HID0_ENABLE_M_BIT |\ | |
60e1dc15 | 527 | HID0_ENABLE_ADDRESS_BROADCAST) */ |
91e25769 PG |
528 | |
529 | ||
6d0f6bcf | 530 | #define CONFIG_SYS_HID2 HID2_HBE |
91e25769 | 531 | |
31d82672 BB |
532 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
533 | ||
91e25769 | 534 | /* DDR @ 0x00000000 */ |
60e1dc15 | 535 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ |
72cd4087 | 536 | | BATL_PP_RW \ |
60e1dc15 JH |
537 | | BATL_MEMCOHERENCE) |
538 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ | |
539 | | BATU_BL_256M \ | |
540 | | BATU_VS \ | |
541 | | BATU_VP) | |
91e25769 PG |
542 | |
543 | /* PCI @ 0x80000000 */ | |
544 | #ifdef CONFIG_PCI | |
842033e6 | 545 | #define CONFIG_PCI_INDIRECT_BRIDGE |
60e1dc15 | 546 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ |
72cd4087 | 547 | | BATL_PP_RW \ |
60e1dc15 JH |
548 | | BATL_MEMCOHERENCE) |
549 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ | |
550 | | BATU_BL_256M \ | |
551 | | BATU_VS \ | |
552 | | BATU_VP) | |
553 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ | |
72cd4087 | 554 | | BATL_PP_RW \ |
60e1dc15 JH |
555 | | BATL_CACHEINHIBIT \ |
556 | | BATL_GUARDEDSTORAGE) | |
557 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ | |
558 | | BATU_BL_256M \ | |
559 | | BATU_VS \ | |
560 | | BATU_VP) | |
91e25769 | 561 | #else |
6d0f6bcf JCPV |
562 | #define CONFIG_SYS_IBAT1L (0) |
563 | #define CONFIG_SYS_IBAT1U (0) | |
564 | #define CONFIG_SYS_IBAT2L (0) | |
565 | #define CONFIG_SYS_IBAT2U (0) | |
91e25769 PG |
566 | #endif |
567 | ||
568 | #ifdef CONFIG_MPC83XX_PCI2 | |
60e1dc15 | 569 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ |
72cd4087 | 570 | | BATL_PP_RW \ |
60e1dc15 JH |
571 | | BATL_MEMCOHERENCE) |
572 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ | |
573 | | BATU_BL_256M \ | |
574 | | BATU_VS \ | |
575 | | BATU_VP) | |
576 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ | |
72cd4087 | 577 | | BATL_PP_RW \ |
60e1dc15 JH |
578 | | BATL_CACHEINHIBIT \ |
579 | | BATL_GUARDEDSTORAGE) | |
580 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ | |
581 | | BATU_BL_256M \ | |
582 | | BATU_VS \ | |
583 | | BATU_VP) | |
91e25769 | 584 | #else |
6d0f6bcf JCPV |
585 | #define CONFIG_SYS_IBAT3L (0) |
586 | #define CONFIG_SYS_IBAT3U (0) | |
587 | #define CONFIG_SYS_IBAT4L (0) | |
588 | #define CONFIG_SYS_IBAT4U (0) | |
91e25769 PG |
589 | #endif |
590 | ||
591 | /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ | |
60e1dc15 | 592 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ |
72cd4087 | 593 | | BATL_PP_RW \ |
60e1dc15 JH |
594 | | BATL_CACHEINHIBIT \ |
595 | | BATL_GUARDEDSTORAGE) | |
596 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ | |
597 | | BATU_BL_256M \ | |
598 | | BATU_VS \ | |
599 | | BATU_VP) | |
91e25769 | 600 | |
7d6a0982 JH |
601 | /* LBC SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ |
602 | #define CONFIG_SYS_IBAT6L (CONFIG_SYS_LBC_SDRAM_BASE \ | |
72cd4087 | 603 | | BATL_PP_RW \ |
60e1dc15 JH |
604 | | BATL_MEMCOHERENCE \ |
605 | | BATL_GUARDEDSTORAGE) | |
7d6a0982 JH |
606 | #define CONFIG_SYS_IBAT6U (CONFIG_SYS_LBC_SDRAM_BASE \ |
607 | | BATU_BL_256M \ | |
608 | | BATU_VS \ | |
609 | | BATU_VP) | |
6d0f6bcf JCPV |
610 | |
611 | #define CONFIG_SYS_IBAT7L (0) | |
612 | #define CONFIG_SYS_IBAT7U (0) | |
613 | ||
614 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
615 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
616 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
617 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
618 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
619 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
620 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
621 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
622 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L | |
623 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
624 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L | |
625 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
626 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
627 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
628 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
629 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
91e25769 | 630 | |
866e3089 | 631 | #if defined(CONFIG_CMD_KGDB) |
91e25769 | 632 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
91e25769 PG |
633 | #endif |
634 | ||
635 | /* | |
636 | * Environment Configuration | |
637 | */ | |
638 | #define CONFIG_ENV_OVERWRITE | |
639 | ||
640 | #if defined(CONFIG_TSEC_ENET) | |
10327dc5 | 641 | #define CONFIG_HAS_ETH0 |
91e25769 | 642 | #define CONFIG_HAS_ETH1 |
91e25769 PG |
643 | #endif |
644 | ||
91e25769 | 645 | #define CONFIG_HOSTNAME SBC8349 |
8b3637c6 | 646 | #define CONFIG_ROOTPATH "/tftpboot/rootfs" |
b3f44c21 | 647 | #define CONFIG_BOOTFILE "uImage" |
91e25769 | 648 | |
60e1dc15 JH |
649 | /* default location for tftp and bootm */ |
650 | #define CONFIG_LOADADDR 800000 | |
91e25769 PG |
651 | |
652 | #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ | |
60e1dc15 | 653 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
91e25769 PG |
654 | |
655 | #define CONFIG_BAUDRATE 115200 | |
656 | ||
657 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
658 | "netdev=eth0\0" \ | |
a99715b8 | 659 | "hostname=sbc8349\0" \ |
91e25769 PG |
660 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
661 | "nfsroot=${serverip}:${rootpath}\0" \ | |
662 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
663 | "addip=setenv bootargs ${bootargs} " \ | |
664 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
665 | ":${hostname}:${netdev}:off panic=1\0" \ | |
666 | "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ | |
667 | "flash_nfs=run nfsargs addip addtty;" \ | |
668 | "bootm ${kernel_addr}\0" \ | |
669 | "flash_self=run ramargs addip addtty;" \ | |
670 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
671 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ | |
672 | "bootm\0" \ | |
673 | "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \ | |
fe613cdd | 674 | "update=protect off ff800000 ff83ffff; " \ |
60e1dc15 | 675 | "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \ |
d8ab58b2 | 676 | "upd=run load update\0" \ |
79f516bc | 677 | "fdtaddr=780000\0" \ |
a99715b8 | 678 | "fdtfile=sbc8349.dtb\0" \ |
91e25769 PG |
679 | "" |
680 | ||
60e1dc15 JH |
681 | #define CONFIG_NFSBOOTCOMMAND \ |
682 | "setenv bootargs root=/dev/nfs rw " \ | |
683 | "nfsroot=$serverip:$rootpath " \ | |
684 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ | |
685 | "$netdev:off " \ | |
686 | "console=$consoledev,$baudrate $othbootargs;" \ | |
687 | "tftp $loadaddr $bootfile;" \ | |
688 | "tftp $fdtaddr $fdtfile;" \ | |
689 | "bootm $loadaddr - $fdtaddr" | |
91e25769 PG |
690 | |
691 | #define CONFIG_RAMBOOTCOMMAND \ | |
60e1dc15 JH |
692 | "setenv bootargs root=/dev/ram rw " \ |
693 | "console=$consoledev,$baudrate $othbootargs;" \ | |
694 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
695 | "tftp $loadaddr $bootfile;" \ | |
696 | "tftp $fdtaddr $fdtfile;" \ | |
697 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
91e25769 PG |
698 | |
699 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
700 | ||
701 | #endif /* __CONFIG_H */ |