projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| c646bba6 JH |
1 | /* |
| 2 | * Copyright 2007 Wind River Systems <www.windriver.com> | |
| 3 | * Copyright 2007 Embedded Specialties, Inc. | |
| 4 | * Joe Hamman <joe.hamman@embeddedspecialties.com> | |
| 5 | * | |
| 6 | * Copyright 2006 Freescale Semiconductor. | |
| 7 | * | |
| 8 | * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) | |
| 9 | * | |
| 10 | * See file CREDITS for list of people who contributed to this | |
| 11 | * project. | |
| 12 | * | |
| 13 | * This program is free software; you can redistribute it and/or | |
| 14 | * modify it under the terms of the GNU General Public License as | |
| 15 | * published by the Free Software Foundation; either version 2 of | |
| 16 | * the License, or (at your option) any later version. | |
| 17 | * | |
| 18 | * This program is distributed in the hope that it will be useful, | |
| 19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 21 | * GNU General Public License for more details. | |
| 22 | * | |
| 23 | * You should have received a copy of the GNU General Public License | |
| 24 | * along with this program; if not, write to the Free Software | |
| 25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 26 | * MA 02111-1307 USA | |
| 27 | */ | |
| 28 | ||
| 29 | /* | |
| 30 | * SBC8641D board configuration file | |
| 31 | * | |
| 32 | * Make sure you change the MAC address and other network params first, | |
| 33 | * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. | |
| 34 | */ | |
| 35 | ||
| 36 | #ifndef __CONFIG_H | |
| 37 | #define __CONFIG_H | |
| 38 | ||
| 39 | /* High Level Configuration Options */ | |
| 40 | #define CONFIG_MPC86xx 1 /* MPC86xx */ | |
| 41 | #define CONFIG_MPC8641 1 /* MPC8641 specific */ | |
| 42 | #define CONFIG_SBC8641D 1 /* SBC8641D board specific */ | |
| 43 | #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ | |
| 44 | #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ | |
| 45 | ||
| 46 | #ifdef RUN_DIAG | |
| 47 | #define CFG_DIAG_ADDR 0xff800000 | |
| 48 | #endif | |
| 49 | ||
| 50 | #define CFG_RESET_ADDRESS 0xfff00100 | |
| 51 | ||
| cca34967 JH |
52 | #define CONFIG_PCI 1 /* Enable PCIE */ |
| 53 | #define CONFIG_PCI1 1 /* PCIE controler 1 (slot 1) */ | |
| 54 | #define CONFIG_PCI2 1 /* PCIE controler 2 (slot 2) */ | |
| 55 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ | |
| 713d8186 | 56 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
| c646bba6 | 57 | |
| 53677ef1 | 58 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
| c646bba6 JH |
59 | #define CONFIG_ENV_OVERWRITE |
| 60 | ||
| 23f935c0 BB |
61 | #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ |
| 62 | ||
| c646bba6 | 63 | #undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/ |
| 53677ef1 | 64 | #undef CONFIG_DDR_ECC /* only for ECC DDR module */ |
| c646bba6 JH |
65 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
| 66 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
| 67 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
| 68 | #define CACHE_LINE_INTERLEAVING 0x20000000 | |
| 69 | #define PAGE_INTERLEAVING 0x21000000 | |
| 70 | #define BANK_INTERLEAVING 0x22000000 | |
| 71 | #define SUPER_BANK_INTERLEAVING 0x23000000 | |
| 72 | ||
| 73 | ||
| 74 | #define CONFIG_ALTIVEC 1 | |
| 75 | ||
| 76 | /* | |
| 77 | * L2CR setup -- make sure this is right for your board! | |
| 78 | */ | |
| 79 | #define CFG_L2 | |
| 80 | #define L2_INIT 0 | |
| 81 | #define L2_ENABLE (L2CR_L2E) | |
| 82 | ||
| 83 | #ifndef CONFIG_SYS_CLK_FREQ | |
| 84 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) | |
| 85 | #endif | |
| 86 | ||
| 87 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ | |
| 88 | ||
| 89 | #undef CFG_DRAM_TEST /* memory test, takes time */ | |
| 90 | #define CFG_MEMTEST_START 0x00200000 /* memtest region */ | |
| 91 | #define CFG_MEMTEST_END 0x00400000 | |
| 92 | ||
| 93 | /* | |
| 94 | * Base addresses -- Note these are effective addresses where the | |
| 95 | * actual resources get mapped (not physical addresses) | |
| 96 | */ | |
| 53677ef1 | 97 | #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
| c646bba6 JH |
98 | #define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ |
| 99 | #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ | |
| 100 | ||
| cca34967 JH |
101 | #define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) |
| 102 | #define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000) | |
| 103 | ||
| c646bba6 JH |
104 | /* |
| 105 | * DDR Setup | |
| 106 | */ | |
| 107 | #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ | |
| 108 | #define CFG_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */ | |
| 109 | #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE | |
| 110 | #define CFG_SDRAM_BASE2 CFG_DDR_SDRAM_BASE2 | |
| 111 | #define CONFIG_VERY_BIG_RAM | |
| 112 | ||
| 113 | #define MPC86xx_DDR_SDRAM_CLK_CNTL | |
| 114 | ||
| 9bd4e591 KG |
115 | #define CONFIG_NUM_DDR_CONTROLLERS 2 |
| 116 | #define CONFIG_DIMM_SLOTS_PER_CTLR 2 | |
| 117 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
| 118 | ||
| c646bba6 JH |
119 | #if defined(CONFIG_SPD_EEPROM) |
| 120 | /* | |
| 121 | * Determine DDR configuration from I2C interface. | |
| 122 | */ | |
| 123 | #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ | |
| 124 | #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */ | |
| 125 | #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */ | |
| 126 | #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */ | |
| 127 | ||
| 128 | #else | |
| 129 | /* | |
| 130 | * Manually set up DDR1 & DDR2 parameters | |
| 131 | */ | |
| 132 | ||
| 133 | #define CFG_SDRAM_SIZE 512 /* DDR is 512MB */ | |
| 134 | ||
| 135 | #define CFG_DDR_CS0_BNDS 0x0000000F | |
| 136 | #define CFG_DDR_CS1_BNDS 0x00000000 | |
| 137 | #define CFG_DDR_CS2_BNDS 0x00000000 | |
| 138 | #define CFG_DDR_CS3_BNDS 0x00000000 | |
| 139 | #define CFG_DDR_CS0_CONFIG 0x80010102 | |
| 140 | #define CFG_DDR_CS1_CONFIG 0x00000000 | |
| 141 | #define CFG_DDR_CS2_CONFIG 0x00000000 | |
| 142 | #define CFG_DDR_CS3_CONFIG 0x00000000 | |
| 45239cf4 | 143 | #define CFG_DDR_TIMING_3 0x00000000 |
| c646bba6 JH |
144 | #define CFG_DDR_TIMING_0 0x00220802 |
| 145 | #define CFG_DDR_TIMING_1 0x38377322 | |
| 146 | #define CFG_DDR_TIMING_2 0x002040c7 | |
| 147 | #define CFG_DDR_CFG_1A 0x43008008 | |
| 148 | #define CFG_DDR_CFG_2 0x24401000 | |
| 149 | #define CFG_DDR_MODE_1 0x23c00542 | |
| 150 | #define CFG_DDR_MODE_2 0x00000000 | |
| 151 | #define CFG_DDR_MODE_CTL 0x00000000 | |
| 152 | #define CFG_DDR_INTERVAL 0x05080100 | |
| 153 | #define CFG_DDR_DATA_INIT 0x00000000 | |
| 154 | #define CFG_DDR_CLK_CTRL 0x03800000 | |
| 155 | #define CFG_DDR_CFG_1B 0xC3008008 | |
| 156 | ||
| 157 | #define CFG_DDR2_CS0_BNDS 0x0010001F | |
| 158 | #define CFG_DDR2_CS1_BNDS 0x00000000 | |
| 159 | #define CFG_DDR2_CS2_BNDS 0x00000000 | |
| 160 | #define CFG_DDR2_CS3_BNDS 0x00000000 | |
| 161 | #define CFG_DDR2_CS0_CONFIG 0x80010102 | |
| 162 | #define CFG_DDR2_CS1_CONFIG 0x00000000 | |
| 163 | #define CFG_DDR2_CS2_CONFIG 0x00000000 | |
| 164 | #define CFG_DDR2_CS3_CONFIG 0x00000000 | |
| 165 | #define CFG_DDR2_EXT_REFRESH 0x00000000 | |
| 166 | #define CFG_DDR2_TIMING_0 0x00220802 | |
| 167 | #define CFG_DDR2_TIMING_1 0x38377322 | |
| 168 | #define CFG_DDR2_TIMING_2 0x002040c7 | |
| 169 | #define CFG_DDR2_CFG_1A 0x43008008 | |
| 170 | #define CFG_DDR2_CFG_2 0x24401000 | |
| 171 | #define CFG_DDR2_MODE_1 0x23c00542 | |
| 172 | #define CFG_DDR2_MODE_2 0x00000000 | |
| 173 | #define CFG_DDR2_MODE_CTL 0x00000000 | |
| 174 | #define CFG_DDR2_INTERVAL 0x05080100 | |
| 175 | #define CFG_DDR2_DATA_INIT 0x00000000 | |
| 176 | #define CFG_DDR2_CLK_CTRL 0x03800000 | |
| 177 | #define CFG_DDR2_CFG_1B 0xC3008008 | |
| 178 | ||
| 179 | ||
| 180 | #endif | |
| 181 | ||
| 32628c50 | 182 | /* #define CONFIG_ID_EEPROM 1 |
| c646bba6 JH |
183 | #define ID_EEPROM_ADDR 0x57 */ |
| 184 | ||
| 185 | /* | |
| 186 | * The SBC8641D contains 16MB flash space at ff000000. | |
| 187 | */ | |
| 188 | #define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */ | |
| 189 | ||
| 190 | /* Flash */ | |
| 191 | #define CFG_BR0_PRELIM 0xff001001 /* port size 16bit */ | |
| 192 | #define CFG_OR0_PRELIM 0xff006e65 /* 16MB Boot Flash area */ | |
| 193 | ||
| 194 | /* 64KB EEPROM */ | |
| 195 | #define CFG_BR1_PRELIM 0xf0000801 /* port size 16bit */ | |
| 196 | #define CFG_OR1_PRELIM 0xffff6e65 /* 64K EEPROM area */ | |
| 197 | ||
| 198 | /* EPLD - User switches, board id, LEDs */ | |
| 199 | #define CFG_BR2_PRELIM 0xf1000801 /* port size 16bit */ | |
| 200 | #define CFG_OR2_PRELIM 0xfff06e65 /* EPLD (switches, board ID, LEDs) area */ | |
| 201 | ||
| 202 | /* Local bus SDRAM 128MB */ | |
| 203 | #define CFG_BR3_PRELIM 0xe0001861 /* port size ?bit */ | |
| 204 | #define CFG_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */ | |
| 205 | #define CFG_BR4_PRELIM 0xe4001861 /* port size ?bit */ | |
| 206 | #define CFG_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */ | |
| 207 | ||
| 208 | /* Disk on Chip (DOC) 128MB */ | |
| 209 | #define CFG_BR5_PRELIM 0xe8001001 /* port size ?bit */ | |
| 210 | #define CFG_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */ | |
| 211 | ||
| 212 | /* LCD */ | |
| 213 | #define CFG_BR6_PRELIM 0xf4000801 /* port size ?bit */ | |
| 214 | #define CFG_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ | |
| 215 | ||
| 216 | /* Control logic & misc peripherals */ | |
| 217 | #define CFG_BR7_PRELIM 0xf2000801 /* port size ?bit */ | |
| 218 | #define CFG_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ | |
| 219 | ||
| 220 | #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ | |
| 221 | #define CFG_MAX_FLASH_SECT 131 /* sectors per device */ | |
| 222 | ||
| 223 | #undef CFG_FLASH_CHECKSUM | |
| 224 | #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 225 | #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 53677ef1 | 226 | #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ |
| c646bba6 | 227 | |
| 00b1883a | 228 | #define CONFIG_FLASH_CFI_DRIVER |
| c646bba6 JH |
229 | #define CFG_FLASH_CFI |
| 230 | #define CFG_WRITE_SWAPPED_DATA | |
| 231 | #define CFG_FLASH_EMPTY_INFO | |
| 232 | #define CFG_FLASH_PROTECTION | |
| 233 | ||
| 234 | #undef CONFIG_CLOCKS_IN_MHZ | |
| 235 | ||
| 236 | #define CONFIG_L1_INIT_RAM | |
| 237 | #define CFG_INIT_RAM_LOCK 1 | |
| 238 | #ifndef CFG_INIT_RAM_LOCK | |
| 239 | #define CFG_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ | |
| 240 | #else | |
| 241 | #define CFG_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ | |
| 242 | #endif | |
| 53677ef1 | 243 | #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ |
| c646bba6 | 244 | |
| 53677ef1 | 245 | #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ |
| c646bba6 JH |
246 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
| 247 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
| 248 | ||
| 53677ef1 WD |
249 | #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
| 250 | #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ | |
| c646bba6 JH |
251 | |
| 252 | /* Serial Port */ | |
| 253 | #define CONFIG_CONS_INDEX 1 | |
| 254 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
| 255 | #define CFG_NS16550 | |
| 256 | #define CFG_NS16550_SERIAL | |
| 257 | #define CFG_NS16550_REG_SIZE 1 | |
| 258 | #define CFG_NS16550_CLK get_bus_freq(0) | |
| 259 | ||
| 260 | #define CFG_BAUDRATE_TABLE \ | |
| 261 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} | |
| 262 | ||
| 263 | #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) | |
| 264 | #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) | |
| 265 | ||
| 266 | /* Use the HUSH parser */ | |
| 267 | #define CFG_HUSH_PARSER | |
| 268 | #ifdef CFG_HUSH_PARSER | |
| 269 | #define CFG_PROMPT_HUSH_PS2 "> " | |
| 270 | #endif | |
| 271 | ||
| 272 | /* | |
| 273 | * Pass open firmware flat tree to kernel | |
| 274 | */ | |
| 13f5433f JL |
275 | #define CONFIG_OF_LIBFDT 1 |
| 276 | #define CONFIG_OF_BOARD_SETUP 1 | |
| 277 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
| c646bba6 JH |
278 | |
| 279 | #define CFG_64BIT_VSPRINTF 1 | |
| 280 | #define CFG_64BIT_STRTOUL 1 | |
| 281 | ||
| 282 | /* | |
| 283 | * I2C | |
| 284 | */ | |
| 285 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
| 286 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
| 287 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
| 288 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ | |
| 289 | #define CFG_I2C_SLAVE 0x7F | |
| 290 | #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ | |
| 291 | #define CFG_I2C_OFFSET 0x3100 | |
| 292 | ||
| 293 | /* | |
| 294 | * RapidIO MMU | |
| 295 | */ | |
| 296 | #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ | |
| 297 | #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE | |
| 298 | #define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ | |
| 299 | ||
| 300 | /* | |
| 301 | * General PCI | |
| 302 | * Addresses are mapped 1-1. | |
| 303 | */ | |
| 304 | #define CFG_PCI1_MEM_BASE 0x80000000 | |
| 305 | #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE | |
| 306 | #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ | |
| 307 | #define CFG_PCI1_IO_BASE 0xe2000000 | |
| 308 | #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE | |
| 309 | #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ | |
| 310 | ||
| 311 | /* PCI view of System Memory */ | |
| 312 | #define CFG_PCI_MEMORY_BUS 0x00000000 | |
| 313 | #define CFG_PCI_MEMORY_PHYS 0x00000000 | |
| 314 | #define CFG_PCI_MEMORY_SIZE 0x80000000 | |
| 315 | ||
| 316 | #define CFG_PCI2_MEM_BASE 0xa0000000 | |
| 317 | #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE | |
| 318 | #define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ | |
| 319 | #define CFG_PCI2_IO_BASE 0xe3000000 | |
| 320 | #define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE | |
| 321 | #define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ | |
| 322 | ||
| 323 | #if defined(CONFIG_PCI) | |
| 324 | ||
| 325 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
| 326 | ||
| 327 | #undef CFG_SCSI_SCAN_BUS_REVERSE | |
| 328 | ||
| 329 | #define CONFIG_NET_MULTI | |
| 53677ef1 | 330 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
| c646bba6 JH |
331 | |
| 332 | #undef CONFIG_EEPRO100 | |
| 333 | #undef CONFIG_TULIP | |
| 334 | ||
| 335 | #if !defined(CONFIG_PCI_PNP) | |
| 336 | #define PCI_ENET0_IOADDR 0xe0000000 | |
| 337 | #define PCI_ENET0_MEMADDR 0xe0000000 | |
| 53677ef1 | 338 | #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ |
| c646bba6 JH |
339 | #endif |
| 340 | ||
| 341 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
| 342 | ||
| 343 | #define CONFIG_DOS_PARTITION | |
| 344 | #undef CONFIG_SCSI_AHCI | |
| 345 | ||
| 346 | #ifdef CONFIG_SCSI_AHCI | |
| 347 | #define CONFIG_SATA_ULI5288 | |
| 348 | #define CFG_SCSI_MAX_SCSI_ID 4 | |
| 349 | #define CFG_SCSI_MAX_LUN 1 | |
| 53677ef1 | 350 | #define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) |
| c646bba6 JH |
351 | #define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE |
| 352 | #endif | |
| 353 | ||
| 354 | #endif /* CONFIG_PCI */ | |
| 355 | ||
| 356 | #if defined(CONFIG_TSEC_ENET) | |
| 357 | ||
| 358 | #ifndef CONFIG_NET_MULTI | |
| 53677ef1 | 359 | #define CONFIG_NET_MULTI 1 |
| c646bba6 JH |
360 | #endif |
| 361 | ||
| 362 | /* #define CONFIG_MII 1 */ /* MII PHY management */ | |
| 363 | ||
| 364 | #define CONFIG_TSEC1 1 | |
| 365 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
| 366 | #define CONFIG_TSEC2 1 | |
| 367 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
| 368 | #define CONFIG_TSEC3 1 | |
| 369 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
| 370 | #define CONFIG_TSEC4 1 | |
| 371 | #define CONFIG_TSEC4_NAME "eTSEC4" | |
| 372 | ||
| 373 | #define TSEC1_PHY_ADDR 0x1F | |
| 374 | #define TSEC2_PHY_ADDR 0x00 | |
| 375 | #define TSEC3_PHY_ADDR 0x01 | |
| 376 | #define TSEC4_PHY_ADDR 0x02 | |
| 377 | #define TSEC1_PHYIDX 0 | |
| 378 | #define TSEC2_PHYIDX 0 | |
| 379 | #define TSEC3_PHYIDX 0 | |
| 380 | #define TSEC4_PHYIDX 0 | |
| 3a79013e AF |
381 | #define TSEC1_FLAGS TSEC_GIGABIT |
| 382 | #define TSEC2_FLAGS TSEC_GIGABIT | |
| 383 | #define TSEC3_FLAGS TSEC_GIGABIT | |
| 384 | #define TSEC4_FLAGS TSEC_GIGABIT | |
| c646bba6 JH |
385 | |
| 386 | #define CFG_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */ | |
| 387 | ||
| 388 | #define CONFIG_ETHPRIME "eTSEC1" | |
| 389 | ||
| 390 | #endif /* CONFIG_TSEC_ENET */ | |
| 391 | ||
| 392 | /* | |
| 393 | * BAT0 2G Cacheable, non-guarded | |
| 394 | * 0x0000_0000 2G DDR | |
| 395 | */ | |
| 396 | #define CFG_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) | |
| 397 | #define CFG_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) | |
| 398 | #define CFG_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) | |
| 399 | #define CFG_IBAT0U CFG_DBAT0U | |
| 400 | ||
| 401 | /* | |
| 402 | * BAT1 1G Cache-inhibited, guarded | |
| 403 | * 0x8000_0000 512M PCI-Express 1 Memory | |
| 404 | * 0xa000_0000 512M PCI-Express 2 Memory | |
| 405 | * Changed it for operating from 0xd0000000 | |
| 406 | */ | |
| 407 | #define CFG_DBAT1L ( CFG_PCI1_MEM_BASE | BATL_PP_RW \ | |
| 408 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 409 | #define CFG_DBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 410 | #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 411 | #define CFG_IBAT1U CFG_DBAT1U | |
| 412 | ||
| 413 | /* | |
| 414 | * BAT2 512M Cache-inhibited, guarded | |
| 415 | * 0xc000_0000 512M RapidIO Memory | |
| 416 | */ | |
| 417 | #define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW \ | |
| 418 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 419 | #define CFG_DBAT2U (CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) | |
| 420 | #define CFG_IBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 421 | #define CFG_IBAT2U CFG_DBAT2U | |
| 422 | ||
| 423 | /* | |
| 424 | * BAT3 4M Cache-inhibited, guarded | |
| 425 | * 0xf800_0000 4M CCSR | |
| 426 | */ | |
| 427 | #define CFG_DBAT3L ( CFG_CCSRBAR | BATL_PP_RW \ | |
| 428 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 429 | #define CFG_DBAT3U (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) | |
| 430 | #define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 431 | #define CFG_IBAT3U CFG_DBAT3U | |
| 432 | ||
| 433 | /* | |
| 434 | * BAT4 32M Cache-inhibited, guarded | |
| 435 | * 0xe200_0000 16M PCI-Express 1 I/O | |
| 436 | * 0xe300_0000 16M PCI-Express 2 I/0 | |
| 437 | * Note that this is at 0xe0000000 | |
| 438 | */ | |
| 439 | #define CFG_DBAT4L ( CFG_PCI1_IO_BASE | BATL_PP_RW \ | |
| 440 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 441 | #define CFG_DBAT4U (CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP) | |
| 442 | #define CFG_IBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 443 | #define CFG_IBAT4U CFG_DBAT4U | |
| 444 | ||
| 445 | /* | |
| 446 | * BAT5 128K Cacheable, non-guarded | |
| 447 | * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) | |
| 448 | */ | |
| 449 | #define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) | |
| 450 | #define CFG_DBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
| 451 | #define CFG_IBAT5L CFG_DBAT5L | |
| 452 | #define CFG_IBAT5U CFG_DBAT5U | |
| 453 | ||
| 454 | /* | |
| 455 | * BAT6 32M Cache-inhibited, guarded | |
| 456 | * 0xfe00_0000 32M FLASH | |
| 457 | */ | |
| 458 | #define CFG_DBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ | |
| 459 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 460 | #define CFG_DBAT6U ((CFG_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) | |
| 461 | #define CFG_IBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) | |
| 462 | #define CFG_IBAT6U CFG_DBAT6U | |
| 463 | ||
| 464 | #define CFG_DBAT7L 0x00000000 | |
| 465 | #define CFG_DBAT7U 0x00000000 | |
| 466 | #define CFG_IBAT7L 0x00000000 | |
| 467 | #define CFG_IBAT7U 0x00000000 | |
| 468 | ||
| 469 | /* | |
| 470 | * Environment | |
| 471 | */ | |
| 5a1aceb0 | 472 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| 0e8d1586 JCPV |
473 | #define CONFIG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) |
| 474 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ | |
| 475 | #define CONFIG_ENV_SIZE 0x2000 | |
| c646bba6 JH |
476 | |
| 477 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 478 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
| 479 | ||
| 480 | #include <config_cmd_default.h> | |
| 481 | #define CONFIG_CMD_PING | |
| 482 | #define CONFIG_CMD_I2C | |
| 4f93f8b1 | 483 | #define CONFIG_CMD_REGINFO |
| c646bba6 JH |
484 | |
| 485 | #if defined(CONFIG_PCI) | |
| 486 | #define CONFIG_CMD_PCI | |
| 487 | #endif | |
| 488 | ||
| 489 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| 490 | ||
| 491 | /* | |
| 492 | * Miscellaneous configurable options | |
| 493 | */ | |
| 494 | #define CFG_LONGHELP /* undef to save memory */ | |
| 495 | #define CFG_LOAD_ADDR 0x2000000 /* default load address */ | |
| 496 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
| 497 | ||
| 30b52df9 | 498 | #if defined(CONFIG_CMD_KGDB) |
| c646bba6 JH |
499 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 500 | #else | |
| 501 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 502 | #endif | |
| 503 | ||
| 504 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
| 505 | #define CFG_MAXARGS 16 /* max number of command args */ | |
| 506 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
| 507 | #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ | |
| 508 | ||
| 509 | /* | |
| 510 | * For booting Linux, the board info and command line data | |
| 511 | * have to be in the first 8 MB of memory, since this is | |
| 512 | * the maximum mapped by the Linux kernel during initialization. | |
| 513 | */ | |
| 514 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ | |
| 515 | ||
| 516 | /* Cache Configuration */ | |
| 517 | #define CFG_DCACHE_SIZE 32768 | |
| 518 | #define CFG_CACHELINE_SIZE 32 | |
| 30b52df9 | 519 | #if defined(CONFIG_CMD_KGDB) |
| c646bba6 JH |
520 | #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ |
| 521 | #endif | |
| 522 | ||
| 523 | /* | |
| 524 | * Internal Definitions | |
| 525 | * | |
| 526 | * Boot Flags | |
| 527 | */ | |
| 528 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
| 529 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
| 530 | ||
| 30b52df9 | 531 | #if defined(CONFIG_CMD_KGDB) |
| c646bba6 JH |
532 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
| 533 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
| 534 | #endif | |
| 535 | ||
| 536 | /* | |
| 537 | * Environment Configuration | |
| 538 | */ | |
| 539 | ||
| 540 | /* The mac addresses for all ethernet interface */ | |
| 541 | #if defined(CONFIG_TSEC_ENET) | |
| 542 | #define CONFIG_ETHADDR 02:E0:0C:00:00:01 | |
| 543 | #define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD | |
| 544 | #define CONFIG_ETH2ADDR 02:E0:0C:00:02:FD | |
| 545 | #define CONFIG_ETH3ADDR 02:E0:0C:00:03:FD | |
| 546 | #endif | |
| 547 | ||
| 10327dc5 | 548 | #define CONFIG_HAS_ETH0 1 |
| c646bba6 JH |
549 | #define CONFIG_HAS_ETH1 1 |
| 550 | #define CONFIG_HAS_ETH2 1 | |
| 551 | #define CONFIG_HAS_ETH3 1 | |
| 552 | ||
| 553 | #define CONFIG_IPADDR 192.168.0.50 | |
| 554 | ||
| 555 | #define CONFIG_HOSTNAME sbc8641d | |
| 556 | #define CONFIG_ROOTPATH /opt/eldk/ppc_74xx | |
| 557 | #define CONFIG_BOOTFILE uImage | |
| 558 | ||
| 559 | #define CONFIG_SERVERIP 192.168.0.2 | |
| 560 | #define CONFIG_GATEWAYIP 192.168.0.1 | |
| 561 | #define CONFIG_NETMASK 255.255.255.0 | |
| 562 | ||
| 563 | /* default location for tftp and bootm */ | |
| 564 | #define CONFIG_LOADADDR 1000000 | |
| 565 | ||
| 566 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
| 567 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
| 568 | ||
| 569 | #define CONFIG_BAUDRATE 115200 | |
| 570 | ||
| 571 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 572 | "netdev=eth0\0" \ | |
| 573 | "consoledev=ttyS0\0" \ | |
| 574 | "ramdiskaddr=2000000\0" \ | |
| 575 | "ramdiskfile=uRamdisk\0" \ | |
| 576 | "dtbaddr=400000\0" \ | |
| 577 | "dtbfile=sbc8641d.dtb\0" \ | |
| 578 | "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ | |
| 579 | "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ | |
| 580 | "maxcpus=1" | |
| 581 | ||
| 582 | #define CONFIG_NFSBOOTCOMMAND \ | |
| 583 | "setenv bootargs root=/dev/nfs rw " \ | |
| 584 | "nfsroot=$serverip:$rootpath " \ | |
| 585 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 586 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 587 | "tftp $loadaddr $bootfile;" \ | |
| 588 | "tftp $dtbaddr $dtbfile;" \ | |
| 589 | "bootm $loadaddr - $dtbaddr" | |
| 590 | ||
| 591 | #define CONFIG_RAMBOOTCOMMAND \ | |
| 592 | "setenv bootargs root=/dev/ram rw " \ | |
| 593 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 594 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 595 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 596 | "tftp $loadaddr $bootfile;" \ | |
| 597 | "tftp $dtbaddr $dtbfile;" \ | |
| 598 | "bootm $loadaddr $ramdiskaddr $dtbaddr" | |
| 599 | ||
| 600 | #define CONFIG_FLASHBOOTCOMMAND \ | |
| 601 | "setenv bootargs root=/dev/ram rw " \ | |
| 602 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 603 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 604 | "bootm ffd00000 ffb00000 ffa00000" | |
| 605 | ||
| 606 | #define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND | |
| 607 | ||
| 608 | #endif /* __CONFIG_H */ |