[people/ms/u-boot.git] / include / configs / silk.h

/*
 * include/configs/silk.h
 *     This file is silk board configuration.
 *
 * Copyright (C) 2015 Renesas Electronics Corporation
 * Copyright (C) 2015 Cogent Embedded, Inc.
 *
 * SPDX-License-Identifier: GPL-2.0
 */

#ifndef __SILK_H
#define __SILK_H

#undef DEBUG
#define CONFIG_R8A7794
#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Silk"

#include "rcar-gen2-common.h"

#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
#define CONFIG_SYS_TEXT_BASE	0x70000000
#else
#define CONFIG_SYS_TEXT_BASE	0xE6304000
#endif

#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
#define CONFIG_SYS_INIT_SP_ADDR		0x7003FFFC
#else
#define CONFIG_SYS_INIT_SP_ADDR		0xE633FFFC
#endif
#define STACK_AREA_SIZE			0xC000
#define LOW_LEVEL_MERAM_STACK \
		(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)

/* MEMORY */
#define RCAR_GEN2_SDRAM_BASE		0x40000000
#define RCAR_GEN2_SDRAM_SIZE		(1024u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE	(512 * 1024 * 1024)

/* SCIF */

/* FLASH */
#define CONFIG_SPI
#define CONFIG_SH_QSPI
#define CONFIG_SPI_FLASH_QUAD

/* SH Ether */
#define CONFIG_SH_ETHER
#define CONFIG_SH_ETHER_USE_PORT	0
#define CONFIG_SH_ETHER_PHY_ADDR	0x1
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_SH_ETHER_ALIGNE_SIZE	64
#define CONFIG_PHY_MICREL
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI

/* Board Clock */
#define RMOBILE_XTAL_CLK	20000000u
#define CONFIG_SYS_CLK_FREQ	RMOBILE_XTAL_CLK
#define CONFIG_SH_TMU_CLK_FREQ	(CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
#define CONFIG_PLL1_CLK_FREQ	(CONFIG_SYS_CLK_FREQ * 156 / 2)
#define CONFIG_P_CLK_FREQ	(CONFIG_PLL1_CLK_FREQ / 24)

#define CONFIG_SYS_TMU_CLK_DIV  4

/* i2c */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SH
#define CONFIG_SYS_I2C_SLAVE		0x7F
#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS	3
#define CONFIG_SYS_I2C_SH_SPEED0	400000
#define CONFIG_SYS_I2C_SH_SPEED1	400000
#define CONFIG_SYS_I2C_SH_SPEED2	400000
#define CONFIG_SH_I2C_DATA_HIGH		4
#define CONFIG_SH_I2C_DATA_LOW		5
#define CONFIG_SH_I2C_CLOCK		10000000

#define CONFIG_SYS_I2C_POWERIC_ADDR	0x58 /* da9063 */

/* USB */
#define CONFIG_USB_EHCI_RMOBILE
#define CONFIG_USB_MAX_CONTROLLER_COUNT	2

/* MMCIF */
#define CONFIG_SH_MMCIF
#define CONFIG_SH_MMCIF_ADDR	0xee200000
#define CONFIG_SH_MMCIF_CLK	48000000

/* SDHI */
#define CONFIG_SH_SDHI_FREQ	97500000

/* Module stop status bits */
/* INTC-RT */
#define CONFIG_SMSTP0_ENA	0x00400000
/* MSIF */
#define CONFIG_SMSTP2_ENA	0x00002000
/* INTC-SYS, IRQC */
#define CONFIG_SMSTP4_ENA	0x00000180
/* SCIF2 */
#define CONFIG_SMSTP7_ENA	0x00080000

#endif /* __SILK_H */
Commit	Line	Data
3b7f0e10 VB	1	/*
	2	* include/configs/silk.h
	3	* This file is silk board configuration.
	4	*
	5	* Copyright (C) 2015 Renesas Electronics Corporation
	6	* Copyright (C) 2015 Cogent Embedded, Inc.
	7	*
	8	* SPDX-License-Identifier: GPL-2.0
	9	*/
	10
	11	#ifndef __SILK_H
	12	#define __SILK_H
	13
	14	#undef DEBUG
	15	#define CONFIG_R8A7794
1cc95f6e	16	#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Silk"
3b7f0e10 VB	17
	18	#include "rcar-gen2-common.h"
	19
1cc95f6e	20	#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
3b7f0e10 VB	21	#define CONFIG_SYS_TEXT_BASE 0x70000000
	22	#else
	23	#define CONFIG_SYS_TEXT_BASE 0xE6304000
	24	#endif
	25
1cc95f6e	26	#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
3b7f0e10 VB	27	#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC
	28	#else
	29	#define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC
	30	#endif
	31	#define STACK_AREA_SIZE 0xC000
	32	#define LOW_LEVEL_MERAM_STACK \
	33	(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
	34
	35	/* MEMORY */
	36	#define RCAR_GEN2_SDRAM_BASE 0x40000000
	37	#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024)
	38	#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
	39
	40	/* SCIF */
3b7f0e10 VB	41
	42	/* FLASH */
	43	#define CONFIG_SPI
3b7f0e10	44	#define CONFIG_SH_QSPI
3b7f0e10	45	#define CONFIG_SPI_FLASH_QUAD
3b7f0e10 VB	46
3b7f0e10 VB	47	/* SH Ether */
3b7f0e10 VB	48	#define CONFIG_SH_ETHER
	49	#define CONFIG_SH_ETHER_USE_PORT 0
	50	#define CONFIG_SH_ETHER_PHY_ADDR 0x1
	51	#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
	52	#define CONFIG_SH_ETHER_CACHE_WRITEBACK
	53	#define CONFIG_SH_ETHER_CACHE_INVALIDATE
	54	#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
3b7f0e10 VB	55	#define CONFIG_PHY_MICREL
	56	#define CONFIG_BITBANGMII
	57	#define CONFIG_BITBANGMII_MULTI
	58
	59	/* Board Clock */
	60	#define RMOBILE_XTAL_CLK 20000000u
	61	#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
	62	#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
	63	#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2)
	64	#define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24)
3b7f0e10 VB	65
	66	#define CONFIG_SYS_TMU_CLK_DIV 4
	67
	68	/* i2c */
3b7f0e10 VB	69	#define CONFIG_SYS_I2C
	70	#define CONFIG_SYS_I2C_SH
	71	#define CONFIG_SYS_I2C_SLAVE 0x7F
	72	#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3
	73	#define CONFIG_SYS_I2C_SH_SPEED0 400000
	74	#define CONFIG_SYS_I2C_SH_SPEED1 400000
	75	#define CONFIG_SYS_I2C_SH_SPEED2 400000
	76	#define CONFIG_SH_I2C_DATA_HIGH 4
	77	#define CONFIG_SH_I2C_DATA_LOW 5
	78	#define CONFIG_SH_I2C_CLOCK 10000000
	79
	80	#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
	81
	82	/* USB */
3b7f0e10 VB	83	#define CONFIG_USB_EHCI_RMOBILE
	84	#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
	85
	86	/* MMCIF */
3b7f0e10 VB	87	#define CONFIG_SH_MMCIF
	88	#define CONFIG_SH_MMCIF_ADDR 0xee200000
	89	#define CONFIG_SH_MMCIF_CLK 48000000
	90
275ec28e VB	91	/* SDHI */
	92	#define CONFIG_SH_SDHI_FREQ 97500000
	93
3b7f0e10 VB	94	/* Module stop status bits */
	95	/* INTC-RT */
	96	#define CONFIG_SMSTP0_ENA 0x00400000
	97	/* MSIF */
	98	#define CONFIG_SMSTP2_ENA 0x00002000
	99	/* INTC-SYS, IRQC */
	100	#define CONFIG_SMSTP4_ENA 0x00000180
	101	/* SCIF2 */
	102	#define CONFIG_SMSTP7_ENA 0x00080000
	103
	104	#endif /* __SILK_H */