[people/ms/u-boot.git] / include / configs / socfpga_sr1500.h

/*
 * Copyright (C) 2015 Stefan Roese <sr@denx.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#ifndef __CONFIG_SOCFPGA_SR1500_H__
#define __CONFIG_SOCFPGA_SR1500_H__

#include <asm/arch/base_addr_ac5.h>

/* Memory configurations */
#define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on SR1500 */

/* Booting Linux */
#define CONFIG_LOADADDR		0x01000000
#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR

/* Ethernet on SoC (EMAC) */
#define CONFIG_PHY_INTERFACE_MODE	PHY_INTERFACE_MODE_RGMII
/* The PHY is autodetected, so no MII PHY address is needed here */
#define CONFIG_PHY_MARVELL
#define PHY_ANEG_TIMEOUT	8000

/* Environment */

/* Enable SPI NOR flash reset, needed for SPI booting */
#define CONFIG_SPI_N25Q256A_RESET

/*
 * Bootcounter
 */
#define CONFIG_SYS_BOOTCOUNT_BE

/* Environment setting for SPI flash */
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_SECT_SIZE	(64 * 1024)
#define CONFIG_ENV_SIZE		(16 * 1024)
#define CONFIG_ENV_OFFSET	0x000e0000
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SPI_BUS	0
#define CONFIG_ENV_SPI_CS	0
#define CONFIG_ENV_SPI_MODE	SPI_MODE_3
#define CONFIG_ENV_SPI_MAX_HZ	100000000	/* Use max of 100MHz */
#define CONFIG_SF_DEFAULT_SPEED	100000000

/*
 * The QSPI NOR flash layout on SR1500:
 *
 * 0000.0000 - 0003.ffff: SPL (4 times)
 * 0004.0000 - 000d.ffff: U-Boot
 * 000e.0000 - 000e.ffff: env1
 * 000f.0000 - 000f.ffff: env2
 */

/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>

#endif	/* __CONFIG_SOCFPGA_SR1500_H__ */
Commit	Line	Data
ae9996c8 SR	1	/*
	2	* Copyright (C) 2015 Stefan Roese <sr@denx.de>
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6	#ifndef __CONFIG_SOCFPGA_SR1500_H__
	7	#define __CONFIG_SOCFPGA_SR1500_H__
	8
	9	#include <asm/arch/base_addr_ac5.h>
	10
ae9996c8 SR	11	/* Memory configurations */
	12	#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */
	13
	14	/* Booting Linux */
ae9996c8 SR	15	#define CONFIG_LOADADDR 0x01000000
ae9996c8 SR	16	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
ae9996c8 SR	17
	18	/* Ethernet on SoC (EMAC) */
	19	#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
	20	/* The PHY is autodetected, so no MII PHY address is needed here */
	21	#define CONFIG_PHY_MARVELL
	22	#define PHY_ANEG_TIMEOUT 8000
	23
ae9996c8	24	/* Environment */
ae9996c8 SR	25
	26	/* Enable SPI NOR flash reset, needed for SPI booting */
	27	#define CONFIG_SPI_N25Q256A_RESET
	28
	29	/*
	30	* Bootcounter
	31	*/
ae9996c8 SR	32	#define CONFIG_SYS_BOOTCOUNT_BE
ae9996c8 SR	33
ae9996c8	34	/* Environment setting for SPI flash */
ae9996c8 SR	35	#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
	36	#define CONFIG_ENV_SECT_SIZE (64 * 1024)
	37	#define CONFIG_ENV_SIZE (16 * 1024)
93d9fc26	38	#define CONFIG_ENV_OFFSET 0x000e0000
ae9996c8 SR	39	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
	40	#define CONFIG_ENV_SPI_BUS 0
	41	#define CONFIG_ENV_SPI_CS 0
	42	#define CONFIG_ENV_SPI_MODE SPI_MODE_3
93d9fc26 SR	43	#define CONFIG_ENV_SPI_MAX_HZ 100000000 /* Use max of 100MHz */
	44	#define CONFIG_SF_DEFAULT_SPEED 100000000
	45
	46	/*
	47	* The QSPI NOR flash layout on SR1500:
	48	*
	49	* 0000.0000 - 0003.ffff: SPL (4 times)
	50	* 0004.0000 - 000d.ffff: U-Boot
	51	* 000e.0000 - 000e.ffff: env1
	52	* 000f.0000 - 000f.ffff: env2
	53	*/
ae9996c8	54
b72041cc MV	55	/* The rest of the configuration is shared */
	56	#include <configs/socfpga_common.h>
	57
ae9996c8	58	#endif /* __CONFIG_SOCFPGA_SR1500_H__ */