[people/ms/u-boot.git] / include / configs / socrates.h

/*
 * (C) Copyright 2008
 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
 *
 * Wolfgang Denk <wd@denx.de>
 * Copyright 2004 Freescale Semiconductor.
 * (C) Copyright 2002,2003 Motorola,Inc.
 * Xianghua Xiao <X.Xiao@motorola.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * Socrates
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* High Level Configuration Options */
#define CONFIG_SOCRATES		1

#define CONFIG_PCI_INDIRECT_BRIDGE

#define CONFIG_TSEC_ENET		/* tsec ethernet support	*/

#define CONFIG_MISC_INIT_R	1	/* Call misc_init_r		*/
#define CONFIG_BOARD_EARLY_INIT_R 1	/* Call board_early_init_r	*/

/*
 * Only possible on E500 Version 2 or newer cores.
 */
#define CONFIG_ENABLE_36BIT_PHYS	1

/*
 * sysclk for MPC85xx
 *
 * Two valid values are:
 *    33000000
 *    66000000
 *
 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
 * is likely the desired value here, so that is now the default.
 * The board, however, can run at 66MHz.  In any event, this value
 * must match the settings of some switches.  Details can be found
 * in the README.mpc85xxads.
 */

#ifndef CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_CLK_FREQ	66666666
#endif

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			/* toggle L2 cache		*/
#define CONFIG_BTB			/* toggle branch predition	*/

#define CONFIG_SYS_INIT_DBCR DBCR_IDM		/* Enable Debug Exceptions	*/

#undef	CONFIG_SYS_DRAM_TEST			/* memory test, takes time	*/
#define CONFIG_SYS_MEMTEST_START	0x00400000
#define CONFIG_SYS_MEMTEST_END		0x00C00000

#define CONFIG_SYS_CCSRBAR		0xE0000000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR

/* DDR Setup */
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD

#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE	0xDeadBeef

#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_VERY_BIG_RAM

#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	2

/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS	0x50	/* CTLR 0 DIMM 0 */

#define CONFIG_DDR_DEFAULT_CL	30		/* CAS latency 3	*/

/* Hardcoded values, to use instead of SPD */
#define CONFIG_SYS_DDR_CS0_BNDS		0x0000000f
#define CONFIG_SYS_DDR_CS0_CONFIG		0x80010102
#define CONFIG_SYS_DDR_TIMING_0		0x00260802
#define CONFIG_SYS_DDR_TIMING_1		0x3935D322
#define CONFIG_SYS_DDR_TIMING_2		0x14904CC8
#define CONFIG_SYS_DDR_MODE			0x00480432
#define CONFIG_SYS_DDR_INTERVAL		0x030C0100
#define CONFIG_SYS_DDR_CONFIG_2		0x04400000
#define CONFIG_SYS_DDR_CONFIG			0xC3008000
#define CONFIG_SYS_DDR_CLK_CONTROL		0x03800000
#define CONFIG_SYS_SDRAM_SIZE			256 /* in Megs */

/*
 * Flash on the LocalBus
 */
#define CONFIG_SYS_LBC_CACHE_BASE	0xf0000000	/* Localbus cacheable	 */

#define CONFIG_SYS_FLASH0		0xFE000000
#define CONFIG_SYS_FLASH1		0xFC000000
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }

#define CONFIG_SYS_LBC_FLASH_BASE	CONFIG_SYS_FLASH1	/* Localbus flash start	*/
#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH	*/

#define CONFIG_SYS_BR0_PRELIM		0xfe001001	/* port size 16bit	*/
#define CONFIG_SYS_OR0_PRELIM		0xfe000030	/* 32MB Flash		*/
#define CONFIG_SYS_BR1_PRELIM		0xfc001001	/* port size 16bit	*/
#define CONFIG_SYS_OR1_PRELIM		0xfe000030	/* 32MB Flash		*/

#define CONFIG_SYS_FLASH_CFI				/* flash is CFI compat.	*/
#define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver*/

#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks	*/
#define CONFIG_SYS_MAX_FLASH_SECT	256		/* sectors per device	*/
#undef	CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms)	*/

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor	*/

#define CONFIG_SYS_LBC_LCRR		0x00030004    /* LB clock ratio reg	*/
#define CONFIG_SYS_LBC_LBCR		0x00000000    /* LB config reg		*/
#define CONFIG_SYS_LBC_LSRT		0x20000000    /* LB sdram refresh timer	*/
#define CONFIG_SYS_LBC_MRTPR		0x20000000    /* LB refresh timer presc.*/

#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address	*/
#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size used area in RAM*/

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(384 * 1024)	/* Reserve 384KiB for Mon */
#define CONFIG_SYS_MALLOC_LEN		(4 << 20)	/* Reserve 4 MB for malloc */

/* FPGA and NAND */
#define CONFIG_SYS_FPGA_BASE		0xc0000000
#define CONFIG_SYS_FPGA_SIZE		0x00100000	/* 1 MB		*/
#define CONFIG_SYS_HMI_BASE		0xc0010000
#define CONFIG_SYS_BR3_PRELIM		0xc0001881	/* UPMA, 32-bit */
#define CONFIG_SYS_OR3_PRELIM		0xfff00000	/* 1 MB 	*/

#define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_FPGA_BASE + 0x70)
#define CONFIG_SYS_MAX_NAND_DEVICE	1

/* LIME GDC */
#define CONFIG_SYS_LIME_BASE		0xc8000000
#define CONFIG_SYS_LIME_SIZE		0x04000000	/* 64 MB	*/
#define CONFIG_SYS_BR2_PRELIM		0xc80018a1	/* UPMB, 32-bit	*/
#define CONFIG_SYS_OR2_PRELIM		0xfc000000	/* 64 MB	*/

#define CONFIG_VIDEO_MB862xx
#define CONFIG_VIDEO_MB862xx_ACCEL
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#define VIDEO_FB_16BPP_PIXEL_SWAP
#define VIDEO_FB_16BPP_WORD_SWAP
#define CONFIG_SPLASH_SCREEN
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(2 << 20)	/* decompressed img */

/* SDRAM Clock frequency, 100MHz (0x0000) or 133MHz (0x10000) */
#define CONFIG_SYS_MB862xx_CCF		0x10000
/* SDRAM parameter */
#define CONFIG_SYS_MB862xx_MMR		0x4157BA63

/* Serial Port */

#define CONFIG_CONS_INDEX     1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)

#define CONFIG_SYS_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

/*
 * I2C
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	102124
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_FSL_I2C2_SPEED	102124
#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100

/* I2C RTC */
#define CONFIG_RTC_RX8025		/* Use Epson rx8025 rtc via i2c	*/
#define CONFIG_SYS_I2C_RTC_ADDR	0x32	/* at address 0x32		*/

/* I2C W83782G HW-Monitoring IC */
#define CONFIG_SYS_I2C_W83782G_ADDR	0x28	/* W83782G address 		*/

#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4

/*
 * General PCI
 * Memory space is mapped 1-1.
 */
#define CONFIG_SYS_PCI_PHYS		0x80000000	/* 1G PCI TLB */

/* PCI is clocked by the external source at 33 MHz */
#define CONFIG_PCI_CLK_FREQ	33000000
#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M			*/
#define CONFIG_SYS_PCI1_IO_BASE	0xE2000000
#define CONFIG_SYS_PCI1_IO_PHYS	CONFIG_SYS_PCI1_IO_BASE
#define CONFIG_SYS_PCI1_IO_SIZE	0x01000000	/* 16M			*/

#if defined(CONFIG_PCI)
#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
#endif	/* CONFIG_PCI */

#define CONFIG_MII		1	/* MII PHY management */
#define CONFIG_TSEC1	1
#define CONFIG_TSEC1_NAME	"TSEC0"
#define CONFIG_TSEC3	1
#define CONFIG_TSEC3_NAME	"TSEC1"
#undef CONFIG_MPC85XX_FEC

#define TSEC1_PHY_ADDR		0
#define TSEC3_PHY_ADDR		1

#define TSEC1_PHYIDX		0
#define TSEC3_PHYIDX		0
#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC3_FLAGS		TSEC_GIGABIT

/* Options are: TSEC[0,1] */
#define CONFIG_ETHPRIME		"TSEC0"

#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1

/*
 * Environment
 */
#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env	*/
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE		0x4000
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define	CONFIG_TIMESTAMP		/* Print image info with ts	*/

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE

#undef CONFIG_WATCHDOG			/* watchdog disabled		*/

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address		*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux	*/

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port*/
#endif

#define CONFIG_LOADADDR	 200000		/* default addr for tftp & bootm*/


#define CONFIG_PREBOOT	"echo;"	\
	"echo Welcome on the ABB Socrates Board;" \
	"echo"

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"consdev=ttyS0\0"						\
	"uboot_file=/home/tftp/syscon3/u-boot.bin\0"			\
	"bootfile=/home/tftp/syscon3/uImage\0"				\
	"fdt_file=/home/tftp/syscon3/socrates.dtb\0"			\
	"initrd_file=/home/tftp/syscon3/uinitrd.gz\0"			\
	"uboot_addr=FFFA0000\0"						\
	"kernel_addr=FE000000\0"					\
	"fdt_addr=FE1E0000\0"						\
	"ramdisk_addr=FE200000\0"					\
	"fdt_addr_r=B00000\0"						\
	"kernel_addr_r=200000\0"					\
	"ramdisk_addr_r=400000\0"					\
	"rootpath=/opt/eldk/ppc_85xxDP\0"				\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=$serverip:$rootpath\0"				\
	"addcons=setenv bootargs $bootargs "				\
		"console=$consdev,$baudrate\0"				\
	"addip=setenv bootargs $bootargs "				\
		"ip=$ipaddr:$serverip:$gatewayip:$netmask"		\
		":$hostname:$netdev:off panic=1\0"			\
	"boot_nor=run ramargs addcons;"					\
		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
		"tftp ${fdt_addr_r} ${fdt_file}; "			\
		"run nfsargs addip addcons;"				\
		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
	"update_uboot=tftp 100000 ${uboot_file};"			\
		"protect off fffa0000 ffffffff;"			\
		"era fffa0000 ffffffff;"				\
		"cp.b 100000 fffa0000 ${filesize};"			\
		"setenv filesize;saveenv\0"				\
	"update_kernel=tftp 100000 ${bootfile};"			\
		"era fe000000 fe1dffff;"				\
		"cp.b 100000 fe000000 ${filesize};"			\
		"setenv filesize;saveenv\0"				\
	"update_fdt=tftp 100000 ${fdt_file};" 				\
		"era fe1e0000 fe1fffff;"				\
		"cp.b 100000 fe1e0000 ${filesize};"			\
		"setenv filesize;saveenv\0"				\
	"update_initrd=tftp 100000 ${initrd_file};" 			\
		"era fe200000 fe9fffff;"				\
		"cp.b 100000 fe200000 ${filesize};"			\
		"setenv filesize;saveenv\0"				\
	"clean_data=era fea00000 fff5ffff\0"				\
	"usbargs=setenv bootargs root=/dev/sda1 rw\0" 			\
	"load_usb=usb start;" 						\
		"ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0"	\
	"boot_usb=run load_usb usbargs addcons;"			\
		"bootm ${kernel_addr_r} - ${fdt_addr};"			\
		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
	""
#define CONFIG_BOOTCOMMAND	"run boot_nor"

/* pass open firmware flat tree */

/* USB support */
#define CONFIG_USB_OHCI_NEW		1
#define CONFIG_PCI_OHCI			1
#define CONFIG_PCI_OHCI_DEVNO		3 /* Number in PCI list */
#define CONFIG_PCI_EHCI_DEVNO		(CONFIG_PCI_OHCI_DEVNO / 2)
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"ohci_pci"
#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS	1

#endif	/* __CONFIG_H */
Commit	Line	Data
5d108ac8 SP	1	/*
	2	* (C) Copyright 2008
	3	* Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
	4	*
	5	* Wolfgang Denk <wd@denx.de>
	6	* Copyright 2004 Freescale Semiconductor.
	7	* (C) Copyright 2002,2003 Motorola,Inc.
	8	* Xianghua Xiao <X.Xiao@motorola.com>
	9	*
3765b3e7	10	* SPDX-License-Identifier: GPL-2.0+
5d108ac8 SP	11	*/
	12
	13	/*
	14	* Socrates
	15	*/
	16
	17	#ifndef __CONFIG_H
	18	#define __CONFIG_H
	19
	20	/* High Level Configuration Options */
5d108ac8 SP	21	#define CONFIG_SOCRATES 1
5d108ac8 SP	22
842033e6	23	#define CONFIG_PCI_INDIRECT_BRIDGE
5d108ac8 SP	24
	25	#define CONFIG_TSEC_ENET /* tsec ethernet support */
	26
	27	#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
3e79b588	28	#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */
5d108ac8	29
5d108ac8 SP	30	/*
	31	* Only possible on E500 Version 2 or newer cores.
	32	*/
	33	#define CONFIG_ENABLE_36BIT_PHYS 1
	34
	35	/*
	36	* sysclk for MPC85xx
	37	*
	38	* Two valid values are:
	39	* 33000000
	40	* 66000000
	41	*
	42	* Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
	43	* is likely the desired value here, so that is now the default.
	44	* The board, however, can run at 66MHz. In any event, this value
	45	* must match the settings of some switches. Details can be found
	46	* in the README.mpc85xxads.
	47	*/
	48
	49	#ifndef CONFIG_SYS_CLK_FREQ
	50	#define CONFIG_SYS_CLK_FREQ 66666666
	51	#endif
	52
	53	/*
	54	* These can be toggled for performance analysis, otherwise use default.
	55	*/
	56	#define CONFIG_L2_CACHE /* toggle L2 cache */
	57	#define CONFIG_BTB /* toggle branch predition */
5d108ac8	58
6d0f6bcf	59	#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
5d108ac8	60
6d0f6bcf JCPV	61	#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
	62	#define CONFIG_SYS_MEMTEST_START 0x00400000
	63	#define CONFIG_SYS_MEMTEST_END 0x00C00000
5d108ac8	64
e46fedfe TT	65	#define CONFIG_SYS_CCSRBAR 0xE0000000
e46fedfe TT	66	#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
5d108ac8	67
be0bd823	68	/* DDR Setup */
be0bd823 KG	69	#undef CONFIG_FSL_DDR_INTERACTIVE
	70	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
	71	#define CONFIG_DDR_SPD
	72
	73	#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
	74	#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
	75
6d0f6bcf JCPV	76	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	77	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
be0bd823 KG	78	#define CONFIG_VERY_BIG_RAM
be0bd823 KG	79
be0bd823 KG	80	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	81	#define CONFIG_CHIP_SELECTS_PER_CTRL 2
	82
	83	/* I2C addresses of SPD EEPROMs */
562788b0	84	#define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */
5d108ac8 SP	85
	86	#define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */
	87
	88	/* Hardcoded values, to use instead of SPD */
6d0f6bcf JCPV	89	#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
	90	#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102
	91	#define CONFIG_SYS_DDR_TIMING_0 0x00260802
	92	#define CONFIG_SYS_DDR_TIMING_1 0x3935D322
	93	#define CONFIG_SYS_DDR_TIMING_2 0x14904CC8
	94	#define CONFIG_SYS_DDR_MODE 0x00480432
	95	#define CONFIG_SYS_DDR_INTERVAL 0x030C0100
	96	#define CONFIG_SYS_DDR_CONFIG_2 0x04400000
	97	#define CONFIG_SYS_DDR_CONFIG 0xC3008000
	98	#define CONFIG_SYS_DDR_CLK_CONTROL 0x03800000
	99	#define CONFIG_SYS_SDRAM_SIZE 256 /* in Megs */
5d108ac8	100
5d108ac8 SP	101	/*
	102	* Flash on the LocalBus
	103	*/
6d0f6bcf	104	#define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
5d108ac8	105
6d0f6bcf JCPV	106	#define CONFIG_SYS_FLASH0 0xFE000000
	107	#define CONFIG_SYS_FLASH1 0xFC000000
	108	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
5d108ac8	109
6d0f6bcf JCPV	110	#define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */
6d0f6bcf JCPV	111	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */
5d108ac8	112
6d0f6bcf JCPV	113	#define CONFIG_SYS_BR0_PRELIM 0xfe001001 /* port size 16bit */
	114	#define CONFIG_SYS_OR0_PRELIM 0xfe000030 /* 32MB Flash */
	115	#define CONFIG_SYS_BR1_PRELIM 0xfc001001 /* port size 16bit */
	116	#define CONFIG_SYS_OR1_PRELIM 0xfe000030 /* 32MB Flash */
5d108ac8	117
6d0f6bcf	118	#define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */
00b1883a	119	#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/
5d108ac8	120
6d0f6bcf JCPV	121	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
	122	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
	123	#undef CONFIG_SYS_FLASH_CHECKSUM
	124	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	125	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
5d108ac8	126
14d0a02a	127	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
5d108ac8	128
6d0f6bcf JCPV	129	#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
	130	#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
	131	#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
	132	#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
5d108ac8	133
6d0f6bcf JCPV	134	#define CONFIG_SYS_INIT_RAM_LOCK 1
6d0f6bcf JCPV	135	#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
553f0982	136	#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM*/
5d108ac8	137
25ddd1fb	138	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	139	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
5d108ac8	140
47106ce1	141	#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384KiB for Mon */
6d0f6bcf	142	#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc */
3e79b588 DZ	143
3e79b588 DZ	144	/* FPGA and NAND */
6d0f6bcf JCPV	145	#define CONFIG_SYS_FPGA_BASE 0xc0000000
	146	#define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */
	147	#define CONFIG_SYS_HMI_BASE 0xc0010000
	148	#define CONFIG_SYS_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */
	149	#define CONFIG_SYS_OR3_PRELIM 0xfff00000 /* 1 MB */
	150
	151	#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70)
	152	#define CONFIG_SYS_MAX_NAND_DEVICE 1
5d108ac8	153
e64987a8	154	/* LIME GDC */
6d0f6bcf JCPV	155	#define CONFIG_SYS_LIME_BASE 0xc8000000
	156	#define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */
	157	#define CONFIG_SYS_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */
	158	#define CONFIG_SYS_OR2_PRELIM 0xfc000000 /* 64 MB */
e64987a8	159
e64987a8	160	#define CONFIG_VIDEO_MB862xx
5d16ca87	161	#define CONFIG_VIDEO_MB862xx_ACCEL
e64987a8 AG	162	#define CONFIG_VIDEO_LOGO
e64987a8 AG	163	#define CONFIG_VIDEO_BMP_LOGO
e64987a8	164	#define VIDEO_FB_16BPP_PIXEL_SWAP
229b6dce	165	#define VIDEO_FB_16BPP_WORD_SWAP
e64987a8 AG	166	#define CONFIG_SPLASH_SCREEN
e64987a8 AG	167	#define CONFIG_VIDEO_BMP_GZIP
6d0f6bcf	168	#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */
e64987a8	169
c28d3bbe WG	170	/* SDRAM Clock frequency, 100MHz (0x0000) or 133MHz (0x10000) */
	171	#define CONFIG_SYS_MB862xx_CCF 0x10000
	172	/* SDRAM parameter */
	173	#define CONFIG_SYS_MB862xx_MMR 0x4157BA63
	174
5d108ac8 SP	175	/* Serial Port */
	176
	177	#define CONFIG_CONS_INDEX 1
6d0f6bcf JCPV	178	#define CONFIG_SYS_NS16550_SERIAL
	179	#define CONFIG_SYS_NS16550_REG_SIZE 1
	180	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
5d108ac8	181
6d0f6bcf JCPV	182	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
6d0f6bcf JCPV	183	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
5d108ac8	184
6d0f6bcf	185	#define CONFIG_SYS_BAUDRATE_TABLE \
5d108ac8 SP	186	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
5d108ac8 SP	187
5d108ac8 SP	188	/*
	189	* I2C
	190	*/
00f792e0 HS	191	#define CONFIG_SYS_I2C
	192	#define CONFIG_SYS_I2C_FSL
	193	#define CONFIG_SYS_FSL_I2C_SPEED 102124
	194	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	195	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	196	#define CONFIG_SYS_FSL_I2C2_SPEED 102124
	197	#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
	198	#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
3e79b588	199
5d108ac8	200	/* I2C RTC */
e18575d5	201	#define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */
6d0f6bcf	202	#define CONFIG_SYS_I2C_RTC_ADDR 0x32 /* at address 0x32 */
5d108ac8	203
e64987a8	204	/* I2C W83782G HW-Monitoring IC */
6d0f6bcf	205	#define CONFIG_SYS_I2C_W83782G_ADDR 0x28 /* W83782G address */
e64987a8	206
6d0f6bcf	207	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
2f7468ae	208
5d108ac8 SP	209	/*
	210	* General PCI
	211	* Memory space is mapped 1-1.
	212	*/
6d0f6bcf	213	#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
5d108ac8	214
5e1882df SP	215	/* PCI is clocked by the external source at 33 MHz */
5e1882df SP	216	#define CONFIG_PCI_CLK_FREQ 33000000
6d0f6bcf JCPV	217	#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
	218	#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
	219	#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
	220	#define CONFIG_SYS_PCI1_IO_BASE 0xE2000000
	221	#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
	222	#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
5d108ac8 SP	223
5d108ac8 SP	224	#if defined(CONFIG_PCI)
d39e6851	225	#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
5d108ac8 SP	226	#endif /* CONFIG_PCI */
5d108ac8 SP	227
5d108ac8 SP	228	#define CONFIG_MII 1 /* MII PHY management */
	229	#define CONFIG_TSEC1 1
	230	#define CONFIG_TSEC1_NAME "TSEC0"
2f845dc2 SP	231	#define CONFIG_TSEC3 1
2f845dc2 SP	232	#define CONFIG_TSEC3_NAME "TSEC1"
5d108ac8 SP	233	#undef CONFIG_MPC85XX_FEC
	234
	235	#define TSEC1_PHY_ADDR 0
2f845dc2	236	#define TSEC3_PHY_ADDR 1
5d108ac8 SP	237
5d108ac8 SP	238	#define TSEC1_PHYIDX 0
2f845dc2	239	#define TSEC3_PHYIDX 0
5d108ac8	240	#define TSEC1_FLAGS TSEC_GIGABIT
2f845dc2	241	#define TSEC3_FLAGS TSEC_GIGABIT
5d108ac8	242
2f845dc2	243	/* Options are: TSEC[0,1] */
5d108ac8	244	#define CONFIG_ETHPRIME "TSEC0"
5d108ac8	245
e18575d5 SP	246	#define CONFIG_HAS_ETH0
	247	#define CONFIG_HAS_ETH1
	248
5d108ac8 SP	249	/*
	250	* Environment
	251	*/
0e8d1586	252	#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
6d0f6bcf	253	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
0e8d1586 JCPV	254	#define CONFIG_ENV_SIZE 0x4000
	255	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
	256	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
5d108ac8 SP	257
5d108ac8 SP	258	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	259	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
5d108ac8 SP	260
	261	#define CONFIG_TIMESTAMP /* Print image info with ts */
	262
5d108ac8 SP	263	/*
	264	* BOOTP options
	265	*/
	266	#define CONFIG_BOOTP_BOOTFILESIZE
5d108ac8	267
5d108ac8 SP	268	#undef CONFIG_WATCHDOG /* watchdog disabled */
	269
	270	/*
	271	* Miscellaneous configurable options
	272	*/
6d0f6bcf	273	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
5d108ac8	274
5d108ac8 SP	275	/*
	276	* For booting Linux, the board info and command line data
	277	* have to be in the first 8 MB of memory, since this is
	278	* the maximum mapped by the Linux kernel during initialization.
	279	*/
6d0f6bcf	280	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
5d108ac8	281
5d108ac8 SP	282	#if defined(CONFIG_CMD_KGDB)
5d108ac8 SP	283	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
5d108ac8 SP	284	#endif
5d108ac8 SP	285
5d108ac8 SP	286	#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/
5d108ac8 SP	287
5d108ac8 SP	288
5d108ac8 SP	289	#define CONFIG_PREBOOT "echo;" \
3e79b588	290	"echo Welcome on the ABB Socrates Board;" \
5d108ac8 SP	291	"echo"
5d108ac8 SP	292
5d108ac8	293	#define CONFIG_EXTRA_ENV_SETTINGS \
5d108ac8 SP	294	"netdev=eth0\0" \
5d108ac8 SP	295	"consdev=ttyS0\0" \
3e79b588 DZ	296	"uboot_file=/home/tftp/syscon3/u-boot.bin\0" \
	297	"bootfile=/home/tftp/syscon3/uImage\0" \
	298	"fdt_file=/home/tftp/syscon3/socrates.dtb\0" \
	299	"initrd_file=/home/tftp/syscon3/uinitrd.gz\0" \
	300	"uboot_addr=FFFA0000\0" \
	301	"kernel_addr=FE000000\0" \
	302	"fdt_addr=FE1E0000\0" \
	303	"ramdisk_addr=FE200000\0" \
	304	"fdt_addr_r=B00000\0" \
	305	"kernel_addr_r=200000\0" \
	306	"ramdisk_addr_r=400000\0" \
	307	"rootpath=/opt/eldk/ppc_85xxDP\0" \
	308	"ramargs=setenv bootargs root=/dev/ram rw\0" \
5d108ac8 SP	309	"nfsargs=setenv bootargs root=/dev/nfs rw " \
5d108ac8 SP	310	"nfsroot=$serverip:$rootpath\0" \
3e79b588 DZ	311	"addcons=setenv bootargs $bootargs " \
3e79b588 DZ	312	"console=$consdev,$baudrate\0" \
5d108ac8 SP	313	"addip=setenv bootargs $bootargs " \
	314	"ip=$ipaddr:$serverip:$gatewayip:$netmask" \
	315	":$hostname:$netdev:off panic=1\0" \
3e79b588	316	"boot_nor=run ramargs addcons;" \
e18575d5	317	"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
e18575d5 SP	318	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
	319	"tftp ${fdt_addr_r} ${fdt_file}; " \
	320	"run nfsargs addip addcons;" \
	321	"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
3e79b588 DZ	322	"update_uboot=tftp 100000 ${uboot_file};" \
	323	"protect off fffa0000 ffffffff;" \
	324	"era fffa0000 ffffffff;" \
	325	"cp.b 100000 fffa0000 ${filesize};" \
	326	"setenv filesize;saveenv\0" \
	327	"update_kernel=tftp 100000 ${bootfile};" \
	328	"era fe000000 fe1dffff;" \
	329	"cp.b 100000 fe000000 ${filesize};" \
5d108ac8	330	"setenv filesize;saveenv\0" \
3e79b588 DZ	331	"update_fdt=tftp 100000 ${fdt_file};" \
	332	"era fe1e0000 fe1fffff;" \
	333	"cp.b 100000 fe1e0000 ${filesize};" \
	334	"setenv filesize;saveenv\0" \
	335	"update_initrd=tftp 100000 ${initrd_file};" \
	336	"era fe200000 fe9fffff;" \
	337	"cp.b 100000 fe200000 ${filesize};" \
	338	"setenv filesize;saveenv\0" \
	339	"clean_data=era fea00000 fff5ffff\0" \
	340	"usbargs=setenv bootargs root=/dev/sda1 rw\0" \
	341	"load_usb=usb start;" \
	342	"ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0" \
	343	"boot_usb=run load_usb usbargs addcons;" \
	344	"bootm ${kernel_addr_r} - ${fdt_addr};" \
	345	"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
5d108ac8	346	""
3e79b588	347	#define CONFIG_BOOTCOMMAND "run boot_nor"
5d108ac8	348
e18575d5	349	/* pass open firmware flat tree */
e18575d5	350
791e1dba SP	351	/* USB support */
	352	#define CONFIG_USB_OHCI_NEW 1
	353	#define CONFIG_PCI_OHCI 1
	354	#define CONFIG_PCI_OHCI_DEVNO 3 /* Number in PCI list */
e90fb6af	355	#define CONFIG_PCI_EHCI_DEVNO (CONFIG_PCI_OHCI_DEVNO / 2)
6d0f6bcf JCPV	356	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
	357	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
	358	#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
791e1dba	359
5d108ac8	360	#endif /* __CONFIG_H */