]>
Commit | Line | Data |
---|---|---|
cba69eee IC |
1 | /* |
2 | * (C) Copyright 2012-2012 Henrik Nordstrom <henrik@henriknordstrom.net> | |
3 | * | |
4 | * (C) Copyright 2007-2011 | |
5 | * Allwinner Technology Co., Ltd. <www.allwinnertech.com> | |
6 | * Tom Cubie <tangliang@allwinnertech.com> | |
7 | * | |
8 | * Configuration settings for the Allwinner sunxi series of boards. | |
9 | * | |
10 | * SPDX-License-Identifier: GPL-2.0+ | |
11 | */ | |
12 | ||
13 | #ifndef _SUNXI_COMMON_CONFIG_H | |
14 | #define _SUNXI_COMMON_CONFIG_H | |
15 | ||
daf6d399 | 16 | #include <asm/arch/cpu.h> |
e049fe28 HG |
17 | #include <linux/stringify.h> |
18 | ||
77ef1369 SS |
19 | #ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT |
20 | /* | |
21 | * The U-Boot workarounds bugs in the outdated buggy sunxi-3.4 kernels at the | |
22 | * expense of restricting some features, so the regular machine id values can | |
23 | * be used. | |
24 | */ | |
25 | # define CONFIG_MACH_TYPE_COMPAT_REV 0 | |
26 | #else | |
27 | /* | |
28 | * A compatibility guard to prevent loading outdated buggy sunxi-3.4 kernels. | |
29 | * Only sunxi-3.4 kernels with appropriate fixes applied are able to pass | |
30 | * beyond the machine id check. | |
31 | */ | |
32 | # define CONFIG_MACH_TYPE_COMPAT_REV 1 | |
33 | #endif | |
34 | ||
d29adf8e AP |
35 | #ifdef CONFIG_ARM64 |
36 | #define CONFIG_BUILD_TARGET "u-boot.itb" | |
37 | #endif | |
38 | ||
cba69eee | 39 | /* Serial & console */ |
cba69eee IC |
40 | #define CONFIG_SYS_NS16550_SERIAL |
41 | /* ns16550 reg in the low bits of cpu reg */ | |
cba69eee | 42 | #define CONFIG_SYS_NS16550_CLK 24000000 |
4fb60552 | 43 | #ifndef CONFIG_DM_SERIAL |
1a81cf83 SG |
44 | # define CONFIG_SYS_NS16550_REG_SIZE -4 |
45 | # define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE | |
46 | # define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE | |
47 | # define CONFIG_SYS_NS16550_COM3 SUNXI_UART2_BASE | |
48 | # define CONFIG_SYS_NS16550_COM4 SUNXI_UART3_BASE | |
49 | # define CONFIG_SYS_NS16550_COM5 SUNXI_R_UART_BASE | |
50 | #endif | |
cba69eee | 51 | |
8a65f69c | 52 | /* CPU */ |
e4916e85 | 53 | #define COUNTER_FREQUENCY 24000000 |
8a65f69c | 54 | |
e049fe28 HG |
55 | /* |
56 | * The DRAM Base differs between some models. We cannot use macros for the | |
57 | * CONFIG_FOO defines which contain the DRAM base address since they end | |
58 | * up unexpanded in include/autoconf.mk . | |
59 | * | |
60 | * So we have to have this #ifdef #else #endif block for these. | |
61 | */ | |
62 | #ifdef CONFIG_MACH_SUN9I | |
63 | #define SDRAM_OFFSET(x) 0x2##x | |
64 | #define CONFIG_SYS_SDRAM_BASE 0x20000000 | |
65 | #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* default load address */ | |
66 | #define CONFIG_SYS_TEXT_BASE 0x2a000000 | |
ff42d107 HG |
67 | /* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here |
68 | * since it needs to fit in with the other values. By also #defining it | |
69 | * we get warnings if the Kconfig value mismatches. */ | |
70 | #define CONFIG_SPL_STACK_R_ADDR 0x2fe00000 | |
e049fe28 HG |
71 | #define CONFIG_SPL_BSS_START_ADDR 0x2ff80000 |
72 | #else | |
73 | #define SDRAM_OFFSET(x) 0x4##x | |
cba69eee | 74 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 |
e049fe28 | 75 | #define CONFIG_SYS_LOAD_ADDR 0x42000000 /* default load address */ |
c199489f IZ |
76 | /* V3s do not have enough memory to place code at 0x4a000000 */ |
77 | #ifndef CONFIG_MACH_SUN8I_V3S | |
e049fe28 | 78 | #define CONFIG_SYS_TEXT_BASE 0x4a000000 |
c199489f IZ |
79 | #else |
80 | #define CONFIG_SYS_TEXT_BASE 0x42e00000 | |
81 | #endif | |
ff42d107 HG |
82 | /* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here |
83 | * since it needs to fit in with the other values. By also #defining it | |
84 | * we get warnings if the Kconfig value mismatches. */ | |
85 | #define CONFIG_SPL_STACK_R_ADDR 0x4fe00000 | |
e049fe28 HG |
86 | #define CONFIG_SPL_BSS_START_ADDR 0x4ff80000 |
87 | #endif | |
88 | ||
89 | #define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 /* 512 KiB */ | |
e049fe28 | 90 | |
bc613d85 | 91 | #ifdef CONFIG_SUNXI_HIGH_SRAM |
77fe9887 HG |
92 | /* |
93 | * The A80's A1 sram starts at 0x00010000 rather then at 0x00000000 and is | |
94 | * slightly bigger. Note that it is possible to map the first 32 KiB of the | |
95 | * A1 at 0x00000000 like with older SoCs by writing 0x16aa0001 to the | |
96 | * undocumented 0x008000e0 SYS_CTRL register. Where the 16aa is a key and | |
97 | * the 1 actually activates the mapping of the first 32 KiB to 0x00000000. | |
98 | */ | |
99 | #define CONFIG_SYS_INIT_RAM_ADDR 0x10000 | |
eb504fa1 | 100 | #define CONFIG_SYS_INIT_RAM_SIZE 0x08000 /* FIXME: 40 KiB ? */ |
77fe9887 | 101 | #else |
cba69eee IC |
102 | #define CONFIG_SYS_INIT_RAM_ADDR 0x0 |
103 | #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */ | |
77fe9887 | 104 | #endif |
cba69eee IC |
105 | |
106 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
107 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
108 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
109 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
110 | ||
111 | #define CONFIG_NR_DRAM_BANKS 1 | |
112 | #define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE | |
113 | #define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */ | |
114 | ||
a6e50a88 IC |
115 | #ifdef CONFIG_AHCI |
116 | #define CONFIG_LIBATA | |
117 | #define CONFIG_SCSI_AHCI | |
118 | #define CONFIG_SCSI_AHCI_PLAT | |
119 | #define CONFIG_SUNXI_AHCI | |
0751b138 | 120 | #define CONFIG_SYS_64BIT_LBA |
a6e50a88 IC |
121 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 |
122 | #define CONFIG_SYS_SCSI_MAX_LUN 1 | |
123 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ | |
124 | CONFIG_SYS_SCSI_MAX_LUN) | |
a6e50a88 IC |
125 | #endif |
126 | ||
cba69eee IC |
127 | #define CONFIG_SETUP_MEMORY_TAGS |
128 | #define CONFIG_CMDLINE_TAG | |
129 | #define CONFIG_INITRD_TAG | |
9f852211 | 130 | #define CONFIG_SERIAL_TAG |
cba69eee | 131 | |
e5268616 | 132 | #ifdef CONFIG_NAND_SUNXI |
a0dfa88b | 133 | #define CONFIG_SYS_NAND_MAX_ECCPOS 1664 |
4ccae81c BB |
134 | #define CONFIG_SYS_NAND_ONFI_DETECTION |
135 | #define CONFIG_SYS_MAX_NAND_DEVICE 8 | |
d482a8df HG |
136 | |
137 | #define CONFIG_MTD_DEVICE | |
138 | #define CONFIG_MTD_PARTITIONS | |
960caeba PZ |
139 | #endif |
140 | ||
19e99fb4 | 141 | #ifdef CONFIG_SPL_SPI_SUNXI |
19e99fb4 SS |
142 | #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 |
143 | #endif | |
144 | ||
e24ea55c | 145 | /* mmc config */ |
44c79879 | 146 | #ifdef CONFIG_MMC |
e24ea55c | 147 | #define CONFIG_MMC_SUNXI_SLOT 0 |
fb1c43cc MR |
148 | #endif |
149 | ||
150 | #if defined(CONFIG_ENV_IS_IN_MMC) | |
de86fc38 MR |
151 | #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 |
152 | /* If we have two devices (most likely eMMC + MMC), favour the eMMC */ | |
153 | #define CONFIG_SYS_MMC_ENV_DEV 1 | |
154 | #else | |
155 | /* Otherwise, use the only device we have */ | |
156 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
157 | #endif | |
ae042beb | 158 | #define CONFIG_SYS_MMC_MAX_DEVICE 4 |
d6a7e0cb MR |
159 | #elif defined(CONFIG_ENV_IS_NOWHERE) |
160 | #define CONFIG_ENV_SIZE (128 << 10) | |
ff2b47f6 | 161 | #endif |
e24ea55c | 162 | |
c199489f | 163 | #ifndef CONFIG_MACH_SUN8I_V3S |
5c965ed9 HG |
164 | /* 64MB of malloc() pool */ |
165 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (64 << 20)) | |
c199489f IZ |
166 | #else |
167 | /* 2MB of malloc() pool */ | |
168 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (2 << 20)) | |
169 | #endif | |
cba69eee IC |
170 | |
171 | /* | |
172 | * Miscellaneous configurable options | |
173 | */ | |
06beadb0 IC |
174 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
175 | #define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */ | |
cba69eee | 176 | |
cba69eee | 177 | /* standalone support */ |
e049fe28 | 178 | #define CONFIG_STANDALONE_LOAD_ADDR CONFIG_SYS_LOAD_ADDR |
cba69eee | 179 | |
cba69eee IC |
180 | /* FLASH and environment organization */ |
181 | ||
fa5e1020 | 182 | #define CONFIG_SYS_MONITOR_LEN (768 << 10) /* 768 KiB */ |
cba69eee | 183 | |
cba69eee | 184 | #define CONFIG_SPL_FRAMEWORK |
cba69eee | 185 | |
eb77f5c9 | 186 | #ifndef CONFIG_ARM64 /* AArch64 FEL support is not ready yet */ |
942cb0b6 | 187 | #define CONFIG_SPL_BOARD_LOAD_IMAGE |
eb77f5c9 | 188 | #endif |
942cb0b6 | 189 | |
bc613d85 | 190 | #ifdef CONFIG_SUNXI_HIGH_SRAM |
7f0ef5a9 SS |
191 | #define CONFIG_SPL_TEXT_BASE 0x10060 /* sram start+header */ |
192 | #define CONFIG_SPL_MAX_SIZE 0x7fa0 /* 32 KiB */ | |
54522c92 AP |
193 | #ifdef CONFIG_ARM64 |
194 | /* end of SRAM A2 for now, as SRAM A1 is pretty tight for an ARM64 build */ | |
195 | #define LOW_LEVEL_SRAM_STACK 0x00054000 | |
196 | #else | |
bc613d85 | 197 | #define LOW_LEVEL_SRAM_STACK 0x00018000 |
54522c92 | 198 | #endif /* !CONFIG_ARM64 */ |
d96ebc46 | 199 | #else |
7f0ef5a9 SS |
200 | #define CONFIG_SPL_TEXT_BASE 0x60 /* sram start+header */ |
201 | #define CONFIG_SPL_MAX_SIZE 0x5fa0 /* 24KB on sun4i/sun7i */ | |
bc613d85 | 202 | #define LOW_LEVEL_SRAM_STACK 0x00008000 /* End of sram */ |
d96ebc46 | 203 | #endif |
50827a59 | 204 | |
bc613d85 AP |
205 | #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK |
206 | ||
50827a59 IC |
207 | #define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */ |
208 | ||
cba69eee | 209 | |
6620377e | 210 | /* I2C */ |
0d8382ae JW |
211 | #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \ |
212 | defined CONFIG_SY8106A_POWER | |
ad40610b HG |
213 | #endif |
214 | ||
6c739c5d PK |
215 | #if defined CONFIG_I2C0_ENABLE || defined CONFIG_I2C1_ENABLE || \ |
216 | defined CONFIG_I2C2_ENABLE || defined CONFIG_I2C3_ENABLE || \ | |
9d082687 | 217 | defined CONFIG_I2C4_ENABLE || defined CONFIG_R_I2C_ENABLE |
6620377e | 218 | #define CONFIG_SYS_I2C_MVTWSI |
a8f01ccf JS |
219 | #ifndef CONFIG_DM_I2C |
220 | #define CONFIG_SYS_I2C | |
6620377e HG |
221 | #define CONFIG_SYS_I2C_SPEED 400000 |
222 | #define CONFIG_SYS_I2C_SLAVE 0x7f | |
8b2db32a | 223 | #endif |
a8f01ccf | 224 | #endif |
55410089 HG |
225 | |
226 | #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) | |
227 | #define CONFIG_SYS_I2C_SOFT | |
228 | #define CONFIG_SYS_I2C_SOFT_SPEED 50000 | |
229 | #define CONFIG_SYS_I2C_SOFT_SLAVE 0x00 | |
55410089 HG |
230 | /* We use pin names in Kconfig and sunxi_name_to_gpio() */ |
231 | #define CONFIG_SOFT_I2C_GPIO_SDA soft_i2c_gpio_sda | |
232 | #define CONFIG_SOFT_I2C_GPIO_SCL soft_i2c_gpio_scl | |
233 | #ifndef __ASSEMBLY__ | |
234 | extern int soft_i2c_gpio_sda; | |
235 | extern int soft_i2c_gpio_scl; | |
236 | #endif | |
1fc42018 HG |
237 | #define CONFIG_VIDEO_LCD_I2C_BUS 0 /* The lcd panel soft i2c is bus 0 */ |
238 | #define CONFIG_SYS_SPD_BUS_NUM 1 /* And the axp209 i2c bus is bus 1 */ | |
239 | #else | |
240 | #define CONFIG_SYS_SPD_BUS_NUM 0 /* The axp209 i2c bus is bus 0 */ | |
241 | #define CONFIG_VIDEO_LCD_I2C_BUS -1 /* NA, but necessary to compile */ | |
55410089 HG |
242 | #endif |
243 | ||
14bc66bd | 244 | /* PMU */ |
95ab8fee | 245 | #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \ |
0d8382ae JW |
246 | defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER || \ |
247 | defined CONFIG_SY8106A_POWER | |
14bc66bd HN |
248 | #endif |
249 | ||
a5da3c83 | 250 | #ifdef CONFIG_REQUIRE_SERIAL_CONSOLE |
f3133962 HG |
251 | #if CONFIG_CONS_INDEX == 1 |
252 | #ifdef CONFIG_MACH_SUN9I | |
253 | #define OF_STDOUT_PATH "/soc/serial@07000000:115200" | |
254 | #else | |
255 | #define OF_STDOUT_PATH "/soc@01c00000/serial@01c28000:115200" | |
256 | #endif | |
257 | #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I) | |
258 | #define OF_STDOUT_PATH "/soc@01c00000/serial@01c28400:115200" | |
5cd83b11 LI |
259 | #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I) |
260 | #define OF_STDOUT_PATH "/soc@01c00000/serial@01c28800:115200" | |
f3133962 HG |
261 | #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I) |
262 | #define OF_STDOUT_PATH "/soc@01c00000/serial@01f02800:115200" | |
263 | #else | |
264 | #error Unsupported console port nr. Please fix stdout-path in sunxi-common.h. | |
265 | #endif | |
a5da3c83 | 266 | #endif /* ifdef CONFIG_REQUIRE_SERIAL_CONSOLE */ |
f3133962 | 267 | |
abce2c62 IC |
268 | /* GPIO */ |
269 | #define CONFIG_SUNXI_GPIO | |
abce2c62 | 270 | |
401a3ca0 | 271 | #ifdef CONFIG_VIDEO_SUNXI |
7f2c521f | 272 | /* |
5633a296 HG |
273 | * The amount of RAM to keep free at the top of RAM when relocating u-boot, |
274 | * to use as framebuffer. This must be a multiple of 4096. | |
7f2c521f | 275 | */ |
5c965ed9 | 276 | #define CONFIG_SUNXI_MAX_FB_SIZE (16 << 20) |
7f2c521f | 277 | |
7f2c521f | 278 | #define CONFIG_VIDEO_LOGO |
be8ec633 | 279 | #define CONFIG_VIDEO_STD_TIMINGS |
75481607 | 280 | #define CONFIG_I2C_EDID |
58332f89 | 281 | #define VIDEO_LINE_LEN (pGD->plnSizeX) |
7f2c521f LV |
282 | |
283 | /* allow both serial and cfb console. */ | |
7f2c521f | 284 | /* stop x86 thinking in cfbconsole from trying to init a pc keyboard */ |
7f2c521f | 285 | |
401a3ca0 | 286 | #endif /* CONFIG_VIDEO_SUNXI */ |
7f2c521f | 287 | |
c26fb9db HG |
288 | /* Ethernet support */ |
289 | #ifdef CONFIG_SUNXI_EMAC | |
8145dea4 | 290 | #define CONFIG_PHY_ADDR 1 |
c26fb9db HG |
291 | #define CONFIG_MII /* MII PHY management */ |
292 | #endif | |
293 | ||
6ff005cf | 294 | #ifdef CONFIG_SUN7I_GMAC |
5835823d IC |
295 | #define CONFIG_PHY_ADDR 1 |
296 | #define CONFIG_MII /* MII PHY management */ | |
1eae8f66 | 297 | #define CONFIG_PHY_REALTEK |
5835823d IC |
298 | #endif |
299 | ||
2582ca0d | 300 | #ifdef CONFIG_USB_EHCI_HCD |
6a72e804 HG |
301 | #define CONFIG_USB_OHCI_NEW |
302 | #define CONFIG_USB_OHCI_SUNXI | |
303 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 | |
1a800f7a HG |
304 | #endif |
305 | ||
306 | #ifdef CONFIG_USB_MUSB_SUNXI | |
95de1e2f | 307 | #define CONFIG_USB_MUSB_PIO_ONLY |
1a800f7a HG |
308 | #endif |
309 | ||
b21144eb | 310 | #ifdef CONFIG_USB_MUSB_GADGET |
aaa4a9e3 | 311 | #define CONFIG_USB_FUNCTION_MASS_STORAGE |
b21144eb PK |
312 | #endif |
313 | ||
b21144eb | 314 | #ifdef CONFIG_USB_FUNCTION_MASS_STORAGE |
b21144eb PK |
315 | #endif |
316 | ||
86b49093 | 317 | #ifdef CONFIG_USB_KEYBOARD |
86b49093 | 318 | #define CONFIG_PREBOOT |
86b49093 HG |
319 | #endif |
320 | ||
b41d7d05 JL |
321 | #define CONFIG_MISC_INIT_R |
322 | ||
cba69eee IC |
323 | #ifndef CONFIG_SPL_BUILD |
324 | #include <config_distro_defaults.h> | |
2ec3a612 | 325 | |
671f9ad8 AP |
326 | #ifdef CONFIG_ARM64 |
327 | /* | |
328 | * Boards seem to come with at least 512MB of DRAM. | |
329 | * The kernel should go at 512K, which is the default text offset (that will | |
330 | * be adjusted at runtime if needed). | |
331 | * There is no compression for arm64 kernels (yet), so leave some space | |
332 | * for really big kernels, say 256MB for now. | |
333 | * Scripts, PXE and DTBs should go afterwards, leaving the rest for the initrd. | |
334 | * Align the initrd to a 2MB page. | |
335 | */ | |
c199489f | 336 | #define BOOTM_SIZE __stringify(0xa000000) |
671f9ad8 AP |
337 | #define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(0080000)) |
338 | #define FDT_ADDR_R __stringify(SDRAM_OFFSET(FA00000)) | |
339 | #define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(FC00000)) | |
340 | #define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(FD00000)) | |
341 | #define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(FE00000)) | |
342 | ||
343 | #else | |
8c95c556 | 344 | /* |
5c965ed9 | 345 | * 160M RAM (256M minimum minus 64MB heap + 32MB for u-boot, stack, fb, etc. |
8c95c556 HG |
346 | * 32M uncompressed kernel, 16M compressed kernel, 1M fdt, |
347 | * 1M script, 1M pxe and the ramdisk at the end. | |
348 | */ | |
c199489f IZ |
349 | #ifndef CONFIG_MACH_SUN8I_V3S |
350 | #define BOOTM_SIZE __stringify(0xa000000) | |
2a909c5f SS |
351 | #define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(2000000)) |
352 | #define FDT_ADDR_R __stringify(SDRAM_OFFSET(3000000)) | |
353 | #define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(3100000)) | |
354 | #define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(3200000)) | |
355 | #define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(3300000)) | |
c199489f IZ |
356 | #else |
357 | /* | |
358 | * 64M RAM minus 2MB heap + 16MB for u-boot, stack, fb, etc. | |
359 | * 16M uncompressed kernel, 8M compressed kernel, 1M fdt, | |
360 | * 1M script, 1M pxe and the ramdisk at the end. | |
361 | */ | |
362 | #define BOOTM_SIZE __stringify(0x2e00000) | |
363 | #define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(1000000)) | |
364 | #define FDT_ADDR_R __stringify(SDRAM_OFFSET(1800000)) | |
365 | #define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(1900000)) | |
366 | #define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(1A00000)) | |
367 | #define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(1B00000)) | |
368 | #endif | |
671f9ad8 | 369 | #endif |
2a909c5f | 370 | |
846e3254 | 371 | #define MEM_LAYOUT_ENV_SETTINGS \ |
c199489f | 372 | "bootm_size=" BOOTM_SIZE "\0" \ |
2a909c5f SS |
373 | "kernel_addr_r=" KERNEL_ADDR_R "\0" \ |
374 | "fdt_addr_r=" FDT_ADDR_R "\0" \ | |
375 | "scriptaddr=" SCRIPT_ADDR_R "\0" \ | |
376 | "pxefile_addr_r=" PXEFILE_ADDR_R "\0" \ | |
377 | "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" | |
378 | ||
379 | #define DFU_ALT_INFO_RAM \ | |
380 | "dfu_alt_info_ram=" \ | |
381 | "kernel ram " KERNEL_ADDR_R " 0x1000000;" \ | |
382 | "fdt ram " FDT_ADDR_R " 0x100000;" \ | |
383 | "ramdisk ram " RAMDISK_ADDR_R " 0x4000000\0" | |
846e3254 | 384 | |
41f8e9f5 | 385 | #ifdef CONFIG_MMC |
5a37a400 | 386 | #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 |
de86fc38 MR |
387 | #define BOOTENV_DEV_MMC_AUTO(devtypeu, devtypel, instance) \ |
388 | BOOTENV_DEV_MMC(MMC, mmc, 0) \ | |
389 | BOOTENV_DEV_MMC(MMC, mmc, 1) \ | |
390 | "bootcmd_mmc_auto=" \ | |
391 | "if test ${mmc_bootdev} -eq 1; then " \ | |
392 | "run bootcmd_mmc1; " \ | |
393 | "run bootcmd_mmc0; " \ | |
394 | "elif test ${mmc_bootdev} -eq 0; then " \ | |
395 | "run bootcmd_mmc0; " \ | |
396 | "run bootcmd_mmc1; " \ | |
397 | "fi\0" | |
398 | ||
399 | #define BOOTENV_DEV_NAME_MMC_AUTO(devtypeu, devtypel, instance) \ | |
400 | "mmc_auto " | |
401 | ||
402 | #define BOOT_TARGET_DEVICES_MMC(func) func(MMC_AUTO, mmc_auto, na) | |
5a37a400 | 403 | #else |
de86fc38 | 404 | #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) |
5a37a400 | 405 | #endif |
41f8e9f5 CYT |
406 | #else |
407 | #define BOOT_TARGET_DEVICES_MMC(func) | |
408 | #endif | |
409 | ||
2ec3a612 HG |
410 | #ifdef CONFIG_AHCI |
411 | #define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0) | |
412 | #else | |
413 | #define BOOT_TARGET_DEVICES_SCSI(func) | |
414 | #endif | |
415 | ||
2582ca0d | 416 | #ifdef CONFIG_USB_STORAGE |
859b3f14 CYT |
417 | #define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) |
418 | #else | |
419 | #define BOOT_TARGET_DEVICES_USB(func) | |
420 | #endif | |
421 | ||
f3b589c0 BN |
422 | /* FEL boot support, auto-execute boot.scr if a script address was provided */ |
423 | #define BOOTENV_DEV_FEL(devtypeu, devtypel, instance) \ | |
424 | "bootcmd_fel=" \ | |
425 | "if test -n ${fel_booted} && test -n ${fel_scriptaddr}; then " \ | |
426 | "echo '(FEL boot)'; " \ | |
427 | "source ${fel_scriptaddr}; " \ | |
428 | "fi\0" | |
429 | #define BOOTENV_DEV_NAME_FEL(devtypeu, devtypel, instance) \ | |
430 | "fel " | |
431 | ||
2ec3a612 | 432 | #define BOOT_TARGET_DEVICES(func) \ |
f3b589c0 | 433 | func(FEL, fel, na) \ |
41f8e9f5 | 434 | BOOT_TARGET_DEVICES_MMC(func) \ |
2ec3a612 | 435 | BOOT_TARGET_DEVICES_SCSI(func) \ |
859b3f14 | 436 | BOOT_TARGET_DEVICES_USB(func) \ |
2ec3a612 HG |
437 | func(PXE, pxe, na) \ |
438 | func(DHCP, dhcp, na) | |
439 | ||
3b824025 HG |
440 | #ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT |
441 | #define BOOTCMD_SUNXI_COMPAT \ | |
442 | "bootcmd_sunxi_compat=" \ | |
443 | "setenv root /dev/mmcblk0p3 rootwait; " \ | |
444 | "if ext2load mmc 0 0x44000000 uEnv.txt; then " \ | |
445 | "echo Loaded environment from uEnv.txt; " \ | |
446 | "env import -t 0x44000000 ${filesize}; " \ | |
447 | "fi; " \ | |
448 | "setenv bootargs console=${console} root=${root} ${extraargs}; " \ | |
449 | "ext2load mmc 0 0x43000000 script.bin && " \ | |
450 | "ext2load mmc 0 0x48000000 uImage && " \ | |
451 | "bootm 0x48000000\0" | |
452 | #else | |
453 | #define BOOTCMD_SUNXI_COMPAT | |
454 | #endif | |
455 | ||
2ec3a612 HG |
456 | #include <config_distro_bootcmd.h> |
457 | ||
86b49093 HG |
458 | #ifdef CONFIG_USB_KEYBOARD |
459 | #define CONSOLE_STDIN_SETTINGS \ | |
460 | "preboot=usb start\0" \ | |
461 | "stdin=serial,usbkbd\0" | |
462 | #else | |
7f2c521f LV |
463 | #define CONSOLE_STDIN_SETTINGS \ |
464 | "stdin=serial\0" | |
86b49093 | 465 | #endif |
7f2c521f LV |
466 | |
467 | #ifdef CONFIG_VIDEO | |
468 | #define CONSOLE_STDOUT_SETTINGS \ | |
469 | "stdout=serial,vga\0" \ | |
470 | "stderr=serial,vga\0" | |
56009451 JS |
471 | #elif CONFIG_DM_VIDEO |
472 | #define CONFIG_SYS_WHITE_ON_BLACK | |
473 | #define CONSOLE_STDOUT_SETTINGS \ | |
474 | "stdout=serial,vidconsole\0" \ | |
475 | "stderr=serial,vidconsole\0" | |
7f2c521f LV |
476 | #else |
477 | #define CONSOLE_STDOUT_SETTINGS \ | |
478 | "stdout=serial\0" \ | |
479 | "stderr=serial\0" | |
480 | #endif | |
481 | ||
c8564b24 MR |
482 | #ifdef CONFIG_MTDIDS_DEFAULT |
483 | #define SUNXI_MTDIDS_DEFAULT \ | |
484 | "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" | |
485 | #else | |
486 | #define SUNXI_MTDIDS_DEFAULT | |
487 | #endif | |
488 | ||
489 | #ifdef CONFIG_MTDPARTS_DEFAULT | |
490 | #define SUNXI_MTDPARTS_DEFAULT \ | |
491 | "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" | |
492 | #else | |
493 | #define SUNXI_MTDPARTS_DEFAULT | |
494 | #endif | |
495 | ||
7f2c521f LV |
496 | #define CONSOLE_ENV_SETTINGS \ |
497 | CONSOLE_STDIN_SETTINGS \ | |
498 | CONSOLE_STDOUT_SETTINGS | |
499 | ||
2eff3b71 AF |
500 | #ifdef CONFIG_ARM64 |
501 | #define FDTFILE "allwinner/" CONFIG_DEFAULT_DEVICE_TREE ".dtb" | |
502 | #else | |
503 | #define FDTFILE CONFIG_DEFAULT_DEVICE_TREE ".dtb" | |
504 | #endif | |
505 | ||
2ec3a612 | 506 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
7f2c521f | 507 | CONSOLE_ENV_SETTINGS \ |
846e3254 | 508 | MEM_LAYOUT_ENV_SETTINGS \ |
2a909c5f | 509 | DFU_ALT_INFO_RAM \ |
2eff3b71 | 510 | "fdtfile=" FDTFILE "\0" \ |
846e3254 | 511 | "console=ttyS0,115200\0" \ |
c8564b24 MR |
512 | SUNXI_MTDIDS_DEFAULT \ |
513 | SUNXI_MTDPARTS_DEFAULT \ | |
3b824025 | 514 | BOOTCMD_SUNXI_COMPAT \ |
2ec3a612 HG |
515 | BOOTENV |
516 | ||
517 | #else /* ifndef CONFIG_SPL_BUILD */ | |
518 | #define CONFIG_EXTRA_ENV_SETTINGS | |
cba69eee IC |
519 | #endif |
520 | ||
521 | #endif /* _SUNXI_COMMON_CONFIG_H */ |