[people/ms/u-boot.git] / include / configs / tam3517-common.h

/*
 * Copyright (C) 2011
 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
 *
 * Copyright (C) 2009 TechNexion Ltd.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __TAM3517_H
#define __TAM3517_H

/*
 * High Level Configuration Options
 */
#define CONFIG_OMAP		/* in a TI OMAP core */
#define CONFIG_OMAP_GPIO

#define CONFIG_SYS_TEXT_BASE 0x80008000

#define CONFIG_EMIF4	/* The chip has EMIF4 controller */

#include <asm/arch/cpu.h>		/* get chip and board defs */
#include <asm/arch/omap.h>

/* Clock Defines */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

#define CONFIG_MISC_INIT_R

#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG

/*
 * Size of malloc() pool
 */
#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10) + \
					2 * 1024 * 1024)
/*
 * DDR related
 */
#define CONFIG_OMAP3_MICRON_DDR		/* Micron DDR */
#define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)

/*
 * Hardware drivers
 */

/*
 * NS16550 Configuration
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		48000000	/* 48MHz (APLL96/2) */

/*
 * select serial console configuration
 */
#define CONFIG_CONS_INDEX		1
#define CONFIG_SYS_NS16550_COM1		OMAP34XX_UART1
#define CONFIG_SERIAL1			/* UART1 */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
					115200}
/* EHCI */
#define CONFIG_OMAP3_GPIO_5
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_OMAP
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	25
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3

/* commands to include */
#define CONFIG_CMD_NAND		/* NAND support			*/
#define CONFIG_CMD_EEPROM

#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED	400000
#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
#define CONFIG_SYS_I2C_OMAP34XX
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50		/* base address */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1		/* bytes of address */
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07

/*
 * Board NAND Info.
 */
#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
							/* to access */
							/* nand at CS0 */

#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
							/* NAND devices */

#define CONFIG_AUTO_COMPLETE

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */

/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		32	/* max number of command */
						/* args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
					0x01F00000) /* 31MB */

#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
								/* address */

/*
 * AM3517 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */

/*
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

/*
 * FLASH and environment organization
 */

/* **** PISMO SUPPORT *** */
#define CONFIG_NAND
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_ENV_IS_IN_NAND
#define SMNAND_ENV_OFFSET		0x180000 /* environment starts here */

/* Redundant Environment */
#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
						2 * CONFIG_SYS_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE	0x800
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - \
					 GENERATED_GBL_DATA_SIZE)

/*
 * ethernet support, EMAC
 *
 */
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_DRIVER_TI_EMAC_USE_RMII
#define CONFIG_MII
#define CONFIG_EMAC_MDIO_PHY_NUM	0
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10

/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_CONSOLE
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_NAND_SOFTECC
#define CONFIG_SPL_NAND_WORKSPACE	0x8f07f000 /* below BSS */

#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_LDSCRIPT		"arch/arm/mach-omap2/u-boot-spl.lds"

#define CONFIG_SPL_TEXT_BASE		0x40200000 /*CONFIG_SYS_SRAM_START*/
#define CONFIG_SPL_MAX_SIZE		(SRAM_SCRATCH_SPACE_ADDR - \
					 CONFIG_SPL_TEXT_BASE)
#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK

#define CONFIG_SYS_SPL_MALLOC_START	0x8f000000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
#define CONFIG_SPL_BSS_START_ADDR	0x8f080000 /* end of RAM */
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000

#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"

/* FAT */
#define CONFIG_SPL_FS_LOAD_KERNEL_NAME		"uImage"
#define CONFIG_SPL_FS_LOAD_ARGS_NAME		"args"

/* RAW SD card / eMMC */
#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0x900	/* address 0x120000 */
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x80	/* address 0x10000 */
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	0x80	/* 64KiB */

/* NAND boot config */
#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_PAGE_SIZE	2048
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
#define CONFIG_SYS_NAND_ECCPOS		{40, 41, 42, 43, 44, 45, 46, 47,\
					 48, 49, 50, 51, 52, 53, 54, 55,\
					 56, 57, 58, 59, 60, 61, 62, 63}
#define CONFIG_SYS_NAND_ECCSIZE		256
#define CONFIG_SYS_NAND_ECCBYTES	3
#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_SW
#define CONFIG_NAND_OMAP_GPMC_PREFETCH

#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE

#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x80000

#define CONFIG_CMD_UBIFS
#define CONFIG_RBTREE
#define CONFIG_LZO
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
#define CONFIG_CMD_MTDPARTS

/* Setup MTD for NAND on the SOM */
#define MTDIDS_DEFAULT		"nand0=omap2-nand.0"
#define MTDPARTS_DEFAULT	"mtdparts=omap2-nand.0:512k(MLO)," \
				"1m(u-boot),256k(env1)," \
				"256k(env2),6m(kernel),-(rootfs)"

#define	CONFIG_TAM3517_SETTINGS						\
	"netdev=eth0\0"							\
	"nandargs=setenv bootargs root=${nandroot} "			\
		"rootfstype=${nandrootfstype}\0"			\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip_sta=setenv bootargs ${bootargs} "			\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"		\
	"addip=if test -n ${ipdyn};then run addip_dyn;"			\
		"else run addip_sta;fi\0"				\
	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
	"addtty=setenv bootargs ${bootargs}"				\
		" console=ttyO0,${baudrate}\0"				\
	"addmisc=setenv bootargs ${bootargs} ${misc}\0"			\
	"loadaddr=82000000\0"						\
	"kernel_addr_r=82000000\0"					\
	"hostname=" __stringify(CONFIG_HOSTNAME) "\0"			\
	"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0"		\
	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr}\0"				\
	"nandboot=run nandargs addip addtty addmtd addmisc;"		\
		"nand read ${kernel_addr_r} kernel\0"			\
		"bootm ${kernel_addr_r}\0"				\
	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
		"run nfsargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr_r}\0"				\
	"net_self=if run net_self_load;then "				\
		"run ramargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr_r} ${ramdisk_addr_r};"		\
		"else echo Images not loades;fi\0"			\
	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0"		\
	"load=tftp ${loadaddr} ${u-boot}\0"				\
	"loadmlo=tftp ${loadaddr} ${mlo}\0"				\
	"mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0"			\
	"uboot_addr=0x80000\0"						\
	"update=nandecc sw;nand erase ${uboot_addr} 100000;"		\
		"nand write ${loadaddr} ${uboot_addr} 80000\0"		\
	"updatemlo=nandecc hw;nand erase 0 20000;"			\
		"nand write ${loadaddr} 0 20000\0"			\
	"upd=if run load;then echo Updating u-boot;if run update;"	\
		"then echo U-Boot updated;"				\
			"else echo Error updating u-boot !;"		\
			"echo Board without bootloader !!;"		\
		"fi;"							\
		"else echo U-Boot not downloaded..exiting;fi\0"		\

/*
 * this is common code for all TAM3517 boards.
 * MAC address is stored from manufacturer in
 * I2C EEPROM
 */
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
/*
 * The I2C EEPROM on the TAM3517 contains
 * mac address and production data
 */
struct tam3517_module_info {
	char customer[48];
	char product[48];

	/*
	 * bit 0~47  : sequence number
	 * bit 48~55 : week of year, from 0.
	 * bit 56~63 : year
	 */
	unsigned long long sequence_number;

	/*
	 * bit 0~7   : revision fixed
	 * bit 8~15  : revision major
	 * bit 16~31 : TNxxx
	 */
	unsigned int revision;
	unsigned char eth_addr[4][8];
	unsigned char _rev[100];
};

#define TAM3517_READ_EEPROM(info, ret) \
do {								\
	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \
	if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,		\
		(void *)info, sizeof(*info)))			\
		ret = 1;					\
	else							\
		ret = 0;					\
} while (0)

#define TAM3517_READ_MAC_FROM_EEPROM(info)			\
do {								\
	char buf[80], ethname[20];				\
	int i;							\
	memset(buf, 0, sizeof(buf));				\
	for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) {	\
		sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X",	\
			(info)->eth_addr[i][5],			\
			(info)->eth_addr[i][4],			\
			(info)->eth_addr[i][3],			\
			(info)->eth_addr[i][2],			\
			(info)->eth_addr[i][1],			\
			(info)->eth_addr[i][0]);			\
								\
		if (i)						\
			sprintf(ethname, "eth%daddr", i);	\
		else						\
			strcpy(ethname, "ethaddr");		\
		printf("Setting %s from EEPROM with %s\n", ethname, buf);\
		setenv(ethname, buf);				\
	}							\
} while (0)

/* The following macros are taken from Technexion's documentation */
#define TAM3517_sequence_number(info) \
	((info)->sequence_number % 0x1000000000000LL)
#define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100)
#define TAM3517_year(info) ((info)->sequence_number >> 56)
#define TAM3517_revision_fixed(info) ((info)->revision % 0x100)
#define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100)
#define TAM3517_revision_tn(info) ((info)->revision >> 16)

#define TAM3517_PRINT_SOM_INFO(info)				\
do {								\
	printf("Vendor:%s\n", (info)->customer);		\
	printf("SOM:   %s\n", (info)->product);			\
	printf("SeqNr: %02llu%02llu%012llu\n",			\
		TAM3517_year(info),				\
		TAM3517_week_of_year(info),			\
		TAM3517_sequence_number(info));			\
	printf("Rev:   TN%u %u.%u\n",				\
		TAM3517_revision_tn(info),			\
		TAM3517_revision_major(info),			\
		TAM3517_revision_fixed(info));			\
} while (0)

#endif

#endif /* __TAM3517_H */
Commit	Line	Data
f9c6fac4 SB	1	/*
	2	* Copyright (C) 2011
	3	* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
	4	*
	5	* Copyright (C) 2009 TechNexion Ltd.
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
f9c6fac4 SB	8	*/
	9
	10	#ifndef __TAM3517_H
	11	#define __TAM3517_H
	12
	13	/*
	14	* High Level Configuration Options
	15	*/
	16	#define CONFIG_OMAP /* in a TI OMAP core */
308252ad	17	#define CONFIG_OMAP_GPIO
f9c6fac4 SB	18
	19	#define CONFIG_SYS_TEXT_BASE 0x80008000
	20
f9c6fac4 SB	21	#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
	22
	23	#include <asm/arch/cpu.h> /* get chip and board defs */
987ec585	24	#include <asm/arch/omap.h>
f9c6fac4	25
f9c6fac4 SB	26	/* Clock Defines */
	27	#define V_OSCK 26000000 /* Clock output from T2 */
	28	#define V_SCLK (V_OSCK >> 1)
	29
f9c6fac4 SB	30	#define CONFIG_MISC_INIT_R
	31
	32	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	33	#define CONFIG_SETUP_MEMORY_TAGS
	34	#define CONFIG_INITRD_TAG
	35	#define CONFIG_REVISION_TAG
	36
	37	/*
	38	* Size of malloc() pool
	39	*/
	40	#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
	41	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \
	42	2 * 1024 * 1024)
	43	/*
	44	* DDR related
	45	*/
	46	#define CONFIG_OMAP3_MICRON_DDR /* Micron DDR */
	47	#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
	48
	49	/*
	50	* Hardware drivers
	51	*/
	52
	53	/*
	54	* NS16550 Configuration
	55	*/
f9c6fac4 SB	56	#define CONFIG_SYS_NS16550_SERIAL
	57	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	58	#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	59
	60	/*
	61	* select serial console configuration
	62	*/
	63	#define CONFIG_CONS_INDEX 1
	64	#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
	65	#define CONFIG_SERIAL1 /* UART1 */
	66
	67	/* allow to overwrite serial and ethaddr */
	68	#define CONFIG_ENV_OVERWRITE
f9c6fac4 SB	69	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
f9c6fac4 SB	70	115200}
f9c6fac4 SB	71	/* EHCI */
	72	#define CONFIG_OMAP3_GPIO_5
	73	#define CONFIG_USB_EHCI
	74	#define CONFIG_USB_EHCI_OMAP
	75	#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25
	76	#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
f9c6fac4	77
f9c6fac4	78	/* commands to include */
f9c6fac4	79	#define CONFIG_CMD_NAND /* NAND support */
8103c6f0	80	#define CONFIG_CMD_EEPROM
f9c6fac4	81
6789e84e HS	82	#define CONFIG_SYS_I2C
	83	#define CONFIG_SYS_OMAP24_I2C_SPEED 400000
	84	#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
	85	#define CONFIG_SYS_I2C_OMAP34XX
8103c6f0 SB	86	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
	87	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
	88	#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
f9c6fac4 SB	89
	90	/*
	91	* Board NAND Info.
	92	*/
	93	#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
	94	/* to access */
	95	/* nand at CS0 */
	96
	97	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
	98	/* NAND devices */
f9c6fac4 SB	99
	100	#define CONFIG_AUTO_COMPLETE
	101
	102	/*
	103	* Miscellaneous configurable options
	104	*/
	105	#define CONFIG_SYS_LONGHELP /* undef to save memory */
f9c6fac4 SB	106	#define CONFIG_CMDLINE_EDITING
	107	#define CONFIG_AUTO_COMPLETE
	108	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
	109
	110	/* Print Buffer Size */
	111	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	112	sizeof(CONFIG_SYS_PROMPT) + 16)
	113	#define CONFIG_SYS_MAXARGS 32 /* max number of command */
	114	/* args */
	115	/* Boot Argument Buffer Size */
	116	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	117	/* memtest works on */
	118	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
	119	#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
	120	0x01F00000) /* 31MB */
	121
	122	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
	123	/* address */
	124
	125	/*
	126	* AM3517 has 12 GP timers, they can be driven by the system clock
	127	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	128	* This rate is divided by a local divisor.
	129	*/
	130	#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
	131	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
f9c6fac4	132
f9c6fac4 SB	133	/*
	134	* Physical Memory Map
	135	*/
	136	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
	137	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
f9c6fac4 SB	138	#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
	139
	140	/*
	141	* FLASH and environment organization
	142	*/
	143
	144	/* ** PISMO SUPPORT * */
0970051d	145	#define CONFIG_NAND
f9c6fac4	146	#define CONFIG_NAND_OMAP_GPMC
f9c6fac4 SB	147	#define CONFIG_ENV_IS_IN_NAND
	148	#define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */
	149
	150	/* Redundant Environment */
	151	#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
	152	#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
	153	#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
	154	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
	155	2 * CONFIG_SYS_ENV_SECT_SIZE)
	156	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
	157
	158	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	159	#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
	160	#define CONFIG_SYS_INIT_RAM_SIZE 0x800
	161	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	162	CONFIG_SYS_INIT_RAM_SIZE - \
	163	GENERATED_GBL_DATA_SIZE)
	164
	165	/*
	166	* ethernet support, EMAC
	167	*
	168	*/
	169	#define CONFIG_DRIVER_TI_EMAC
	170	#define CONFIG_DRIVER_TI_EMAC_USE_RMII
	171	#define CONFIG_MII
	172	#define CONFIG_EMAC_MDIO_PHY_NUM 0
f9c6fac4 SB	173	#define CONFIG_BOOTP_DNS
	174	#define CONFIG_BOOTP_DNS2
	175	#define CONFIG_BOOTP_SEND_HOSTNAME
	176	#define CONFIG_NET_RETRY_COUNT 10
f9c6fac4 SB	177
f9c6fac4 SB	178	/* Defines for SPL */
47f7bcae	179	#define CONFIG_SPL_FRAMEWORK
d7cb93b2	180	#define CONFIG_SPL_BOARD_INIT
f9c6fac4 SB	181	#define CONFIG_SPL_CONSOLE
f9c6fac4 SB	182	#define CONFIG_SPL_NAND_SIMPLE
8ad59c9a	183	#define CONFIG_SPL_NAND_SOFTECC
f9c6fac4 SB	184	#define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */
f9c6fac4 SB	185
6f2f01b9 SW	186	#define CONFIG_SPL_NAND_BASE
	187	#define CONFIG_SPL_NAND_DRIVERS
	188	#define CONFIG_SPL_NAND_ECC
983e3700	189	#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
f9c6fac4 SB	190
f9c6fac4 SB	191	#define CONFIG_SPL_TEXT_BASE 0x40200000 /CONFIG_SYS_SRAM_START/
fa2f81b0 TR	192	#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
fa2f81b0 TR	193	CONFIG_SPL_TEXT_BASE)
f51c8a99	194	#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
f9c6fac4 SB	195
	196	#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000
	197	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
	198	#define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */
	199	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
	200
f51c8a99 SB	201	#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
	202	#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
	203
	204	/* FAT */
	205	#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
	206	#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
	207
	208	/* RAW SD card / eMMC */
	209	#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */
	210	#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */
	211	#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */
	212
f9c6fac4	213	/* NAND boot config */
55f1b39f	214	#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
f9c6fac4 SB	215	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	216	#define CONFIG_SYS_NAND_PAGE_SIZE 2048
	217	#define CONFIG_SYS_NAND_OOBSIZE 64
	218	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
	219	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	220	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
	221	#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\
	222	48, 49, 50, 51, 52, 53, 54, 55,\
	223	56, 57, 58, 59, 60, 61, 62, 63}
	224	#define CONFIG_SYS_NAND_ECCSIZE 256
	225	#define CONFIG_SYS_NAND_ECCBYTES 3
3f719069	226	#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW
817aa32b	227	#define CONFIG_NAND_OMAP_GPMC_PREFETCH
f9c6fac4	228
f9c6fac4 SB	229	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	230
	231	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
	232	#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
	233
f9c6fac4 SB	234	#define CONFIG_CMD_UBIFS
	235	#define CONFIG_RBTREE
	236	#define CONFIG_LZO
	237	#define CONFIG_MTD_PARTITIONS
	238	#define CONFIG_MTD_DEVICE
	239	#define CONFIG_CMD_MTDPARTS
	240
	241	/* Setup MTD for NAND on the SOM */
	242	#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
	243	#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \
1fdabedd SB	244	"1m(u-boot),256k(env1)," \
1fdabedd SB	245	"256k(env2),6m(kernel),-(rootfs)"
f9c6fac4	246
f9c6fac4 SB	247	#define CONFIG_TAM3517_SETTINGS \
	248	"netdev=eth0\0" \
	249	"nandargs=setenv bootargs root=${nandroot} " \
	250	"rootfstype=${nandrootfstype}\0" \
	251	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	252	"nfsroot=${serverip}:${rootpath}\0" \
	253	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	254	"addip_sta=setenv bootargs ${bootargs} " \
	255	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	256	":${hostname}:${netdev}:off panic=1\0" \
	257	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
	258	"addip=if test -n ${ipdyn};then run addip_dyn;" \
	259	"else run addip_sta;fi\0" \
	260	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
	261	"addtty=setenv bootargs ${bootargs}" \
	262	" console=ttyO0,${baudrate}\0" \
	263	"addmisc=setenv bootargs ${bootargs} ${misc}\0" \
	264	"loadaddr=82000000\0" \
	265	"kernel_addr_r=82000000\0" \
93ea89f0 MV	266	"hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
93ea89f0 MV	267	"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
f9c6fac4 SB	268	"flash_self=run ramargs addip addtty addmtd addmisc;" \
	269	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
	270	"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
	271	"bootm ${kernel_addr}\0" \
	272	"nandboot=run nandargs addip addtty addmtd addmisc;" \
	273	"nand read ${kernel_addr_r} kernel\0" \
	274	"bootm ${kernel_addr_r}\0" \
	275	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
	276	"run nfsargs addip addtty addmtd addmisc;" \
	277	"bootm ${kernel_addr_r}\0" \
	278	"net_self=if run net_self_load;then " \
	279	"run ramargs addip addtty addmtd addmisc;" \
	280	"bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
	281	"else echo Images not loades;fi\0" \
93ea89f0	282	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \
f9c6fac4 SB	283	"load=tftp ${loadaddr} ${u-boot}\0" \
f9c6fac4 SB	284	"loadmlo=tftp ${loadaddr} ${mlo}\0" \
93ea89f0	285	"mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \
f9c6fac4 SB	286	"uboot_addr=0x80000\0" \
	287	"update=nandecc sw;nand erase ${uboot_addr} 100000;" \
	288	"nand write ${loadaddr} ${uboot_addr} 80000\0" \
	289	"updatemlo=nandecc hw;nand erase 0 20000;" \
	290	"nand write ${loadaddr} 0 20000\0" \
	291	"upd=if run load;then echo Updating u-boot;if run update;" \
	292	"then echo U-Boot updated;" \
	293	"else echo Error updating u-boot !;" \
	294	"echo Board without bootloader !!;" \
	295	"fi;" \
	296	"else echo U-Boot not downloaded..exiting;fi\0" \
	297
8103c6f0 SB	298	/*
	299	* this is common code for all TAM3517 boards.
	300	* MAC address is stored from manufacturer in
	301	* I2C EEPROM
	302	*/
	303	#if !(defined(__KERNEL_STRICT_NAMES) \|\| defined(__ASSEMBLY__))
8103c6f0 SB	304	/*
	305	* The I2C EEPROM on the TAM3517 contains
	306	* mac address and production data
	307	*/
	308	struct tam3517_module_info {
	309	char customer[48];
	310	char product[48];
	311
	312	/*
	313	* bit 0~47 : sequence number
	314	* bit 48~55 : week of year, from 0.
	315	* bit 56~63 : year
	316	*/
	317	unsigned long long sequence_number;
	318
	319	/*
	320	* bit 0~7 : revision fixed
	321	* bit 8~15 : revision major
	322	* bit 16~31 : TNxxx
	323	*/
	324	unsigned int revision;
	325	unsigned char eth_addr[4][8];
	326	unsigned char _rev[100];
	327	};
	328
31f5b651 SB	329	#define TAM3517_READ_EEPROM(info, ret) \
31f5b651 SB	330	do { \
6789e84e	331	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \
8103c6f0	332	if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \
31f5b651 SB	333	(void )info, sizeof(info))) \
	334	ret = 1; \
	335	else \
	336	ret = 0; \
	337	} while (0)
	338
	339	#define TAM3517_READ_MAC_FROM_EEPROM(info) \
	340	do { \
	341	char buf[80], ethname[20]; \
	342	int i; \
8103c6f0	343	memset(buf, 0, sizeof(buf)); \
31f5b651	344	for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) { \
8103c6f0	345	sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X", \
31f5b651 SB	346	(info)->eth_addr[i][5], \
	347	(info)->eth_addr[i][4], \
	348	(info)->eth_addr[i][3], \
	349	(info)->eth_addr[i][2], \
	350	(info)->eth_addr[i][1], \
	351	(info)->eth_addr[i][0]); \
8103c6f0 SB	352	\
	353	if (i) \
	354	sprintf(ethname, "eth%daddr", i); \
	355	else \
192bc694	356	strcpy(ethname, "ethaddr"); \
8103c6f0 SB	357	printf("Setting %s from EEPROM with %s\n", ethname, buf);\
	358	setenv(ethname, buf); \
	359	} \
	360	} while (0)
31f5b651 SB	361
	362	/* The following macros are taken from Technexion's documentation */
	363	#define TAM3517_sequence_number(info) \
	364	((info)->sequence_number % 0x1000000000000LL)
	365	#define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100)
	366	#define TAM3517_year(info) ((info)->sequence_number >> 56)
	367	#define TAM3517_revision_fixed(info) ((info)->revision % 0x100)
	368	#define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100)
	369	#define TAM3517_revision_tn(info) ((info)->revision >> 16)
	370
	371	#define TAM3517_PRINT_SOM_INFO(info) \
	372	do { \
	373	printf("Vendor:%s\n", (info)->customer); \
	374	printf("SOM: %s\n", (info)->product); \
	375	printf("SeqNr: %02llu%02llu%012llu\n", \
	376	TAM3517_year(info), \
	377	TAM3517_week_of_year(info), \
	378	TAM3517_sequence_number(info)); \
	379	printf("Rev: TN%u %u.%u\n", \
	380	TAM3517_revision_tn(info), \
	381	TAM3517_revision_major(info), \
	382	TAM3517_revision_fixed(info)); \
	383	} while (0)
	384
8103c6f0 SB	385	#endif
8103c6f0 SB	386
f9c6fac4	387	#endif /* __TAM3517_H */