]>
Commit | Line | Data |
---|---|---|
550e3756 TU |
1 | /* |
2 | * Configuration settings for the TechNexion TAO-3530 SOM | |
3 | * equipped on Thunder baseboard. | |
4 | * | |
5 | * Edward Lin <linuxfae@technexion.com> | |
6 | * Tapani Utriainen <linuxfae@technexion.com> | |
7 | * | |
a9f52490 SR |
8 | * Copyright (C) 2013 Stefan Roese <sr@denx.de> |
9 | * | |
550e3756 TU |
10 | * SPDX-License-Identifier: GPL-2.0+ |
11 | */ | |
12 | ||
13 | #ifndef __CONFIG_H | |
14 | #define __CONFIG_H | |
15 | ||
16 | /* | |
17 | * High Level Configuration Options | |
18 | */ | |
550e3756 | 19 | |
550e3756 TU |
20 | #define CONFIG_SDRC /* Has an SDRC controller */ |
21 | ||
22 | #include <asm/arch/cpu.h> /* get chip and board defs */ | |
987ec585 | 23 | #include <asm/arch/omap.h> |
550e3756 | 24 | |
550e3756 TU |
25 | /* Clock Defines */ |
26 | #define V_OSCK 26000000 /* Clock output from T2 */ | |
27 | #define V_SCLK (V_OSCK >> 1) | |
28 | ||
29 | #define CONFIG_MISC_INIT_R | |
30 | ||
550e3756 TU |
31 | #define CONFIG_CMDLINE_TAG |
32 | #define CONFIG_SETUP_MEMORY_TAGS | |
33 | #define CONFIG_INITRD_TAG | |
34 | #define CONFIG_REVISION_TAG | |
35 | ||
36 | /* | |
37 | * Size of malloc() pool | |
38 | */ | |
39 | #define CONFIG_SYS_MALLOC_LEN (4 << 20) | |
40 | #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ | |
41 | ||
42 | /* | |
43 | * Hardware drivers | |
44 | */ | |
45 | ||
46 | /* | |
47 | * NS16550 Configuration | |
48 | */ | |
49 | #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ | |
50 | ||
550e3756 TU |
51 | #define CONFIG_SYS_NS16550_SERIAL |
52 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
53 | #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK | |
54 | ||
55 | /* | |
56 | * select serial console configuration | |
57 | */ | |
58 | #define CONFIG_CONS_INDEX 3 | |
59 | #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 | |
60 | ||
61 | /* allow to overwrite serial and ethaddr */ | |
62 | #define CONFIG_ENV_OVERWRITE | |
550e3756 TU |
63 | |
64 | /* commands to include */ | |
550e3756 TU |
65 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
66 | #define MTDIDS_DEFAULT "nand0=nand" | |
67 | #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ | |
68 | "1920k(u-boot),128k(u-boot-env),"\ | |
69 | "4m(kernel),-(fs)" | |
70 | ||
550e3756 | 71 | #define CONFIG_SYS_I2C |
550e3756 TU |
72 | #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 |
73 | #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 | |
74 | #define CONFIG_I2C_MULTI_BUS | |
75 | ||
76 | /* | |
77 | * TWL4030 | |
78 | */ | |
550e3756 TU |
79 | #define CONFIG_TWL4030_LED |
80 | ||
81 | /* | |
82 | * Board NAND Info. | |
83 | */ | |
550e3756 TU |
84 | #define CONFIG_NAND_OMAP_GPMC |
85 | #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ | |
86 | /* to access nand */ | |
87 | #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ | |
88 | /* to access nand at */ | |
89 | /* CS0 */ | |
550e3756 TU |
90 | |
91 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ | |
92 | /* devices */ | |
55f1b39f | 93 | #define CONFIG_SYS_NAND_BUSWIDTH_16BIT |
550e3756 | 94 | /* Environment information */ |
550e3756 TU |
95 | |
96 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
97 | "loadaddr=0x82000000\0" \ | |
98 | "console=ttyO2,115200n8\0" \ | |
99 | "mpurate=600\0" \ | |
100 | "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \ | |
101 | "tv_mode=omapfb.mode=tv:ntsc\0" \ | |
102 | "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \ | |
103 | "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \ | |
104 | "extra_options= \0" \ | |
550e3756 TU |
105 | "mmcdev=0\0" \ |
106 | "mmcroot=/dev/mmcblk0p2 rw\0" \ | |
107 | "mmcrootfstype=ext3 rootwait\0" \ | |
108 | "nandroot=ubi0:rootfs ubi.mtd=4\0" \ | |
109 | "nandrootfstype=ubifs\0" \ | |
110 | "mmcargs=setenv bootargs console=${console} " \ | |
550e3756 TU |
111 | "mpurate=${mpurate} " \ |
112 | "${video_mode} " \ | |
113 | "root=${mmcroot} " \ | |
114 | "rootfstype=${mmcrootfstype} " \ | |
115 | "${extra_options}\0" \ | |
116 | "nandargs=setenv bootargs console=${console} " \ | |
550e3756 TU |
117 | "mpurate=${mpurate} " \ |
118 | "${video_mode} " \ | |
119 | "${network_setting} " \ | |
120 | "root=${nandroot} " \ | |
121 | "rootfstype=${nandrootfstype} "\ | |
122 | "${extra_options}\0" \ | |
123 | "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ | |
124 | "bootscript=echo Running bootscript from mmc ...; " \ | |
125 | "source ${loadaddr}\0" \ | |
126 | "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ | |
127 | "mmcboot=echo Booting from mmc ...; " \ | |
128 | "run mmcargs; " \ | |
129 | "bootm ${loadaddr}\0" \ | |
130 | "nandboot=echo Booting from nand ...; " \ | |
131 | "run nandargs; " \ | |
132 | "nand read ${loadaddr} 280000 400000; " \ | |
133 | "bootm ${loadaddr}\0" \ | |
134 | ||
135 | #define CONFIG_BOOTCOMMAND \ | |
136 | "if mmc rescan ${mmcdev}; then " \ | |
137 | "if run loadbootscript; then " \ | |
138 | "run bootscript; " \ | |
139 | "else " \ | |
140 | "if run loaduimage; then " \ | |
141 | "run mmcboot; " \ | |
142 | "else run nandboot; " \ | |
143 | "fi; " \ | |
144 | "fi; " \ | |
145 | "else run nandboot; fi" | |
146 | ||
147 | /* | |
148 | * Miscellaneous configurable options | |
149 | */ | |
150 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
550e3756 TU |
151 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
152 | ||
153 | /* turn on command-line edit/hist/auto */ | |
154 | #define CONFIG_CMDLINE_EDITING | |
550e3756 TU |
155 | #define CONFIG_AUTO_COMPLETE |
156 | ||
157 | /* Print Buffer Size */ | |
158 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
159 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
160 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
161 | /* Boot Argument Buffer Size */ | |
162 | #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) | |
163 | ||
164 | #define CONFIG_SYS_ALT_MEMTEST 1 | |
165 | #define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */ | |
166 | /* defaults */ | |
167 | #define CONFIG_SYS_MEMTEST_END (0x83FFFFFF) /* 64MB */ | |
168 | #define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */ | |
169 | ||
170 | #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ | |
171 | /* load address */ | |
172 | #define CONFIG_SYS_TEXT_BASE 0x80008000 | |
173 | ||
174 | /* | |
175 | * OMAP3 has 12 GP timers, they can be driven by the system clock | |
176 | * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). | |
177 | * This rate is divided by a local divisor. | |
178 | */ | |
179 | #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) | |
180 | #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ | |
181 | ||
550e3756 TU |
182 | /* |
183 | * Physical Memory Map | |
184 | */ | |
185 | #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ | |
186 | #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 | |
187 | #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ | |
188 | #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 | |
189 | ||
190 | /* | |
191 | * FLASH and environment organization | |
192 | */ | |
193 | ||
194 | /* **** PISMO SUPPORT *** */ | |
550e3756 | 195 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ |
222a3113 | 196 | #define CONFIG_SYS_FLASH_BASE NAND_BASE |
550e3756 TU |
197 | |
198 | /* Monitor at start of flash */ | |
199 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
200 | #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP | |
201 | ||
550e3756 TU |
202 | #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ |
203 | #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ | |
204 | ||
205 | #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) | |
206 | #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET | |
207 | #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET | |
208 | ||
209 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
210 | #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 | |
211 | #define CONFIG_SYS_INIT_RAM_SIZE 0x800 | |
212 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | |
213 | CONFIG_SYS_INIT_RAM_SIZE - \ | |
214 | GENERATED_GBL_DATA_SIZE) | |
215 | ||
550e3756 TU |
216 | /* |
217 | * USB | |
218 | * | |
219 | * Currently only EHCI is enabled, the MUSB OTG controller | |
220 | * is not enabled. | |
221 | */ | |
222 | ||
223 | /* USB EHCI */ | |
550e3756 TU |
224 | #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162 |
225 | ||
550e3756 TU |
226 | #define CONFIG_USB_HOST_ETHER |
227 | #define CONFIG_USB_ETHER_SMSC95XX | |
228 | ||
229 | #define CONFIG_USB_ETHER | |
230 | #define CONFIG_USB_ETHER_RNDIS | |
550e3756 | 231 | |
a9f52490 | 232 | /* Defines for SPL */ |
a9f52490 SR |
233 | #define CONFIG_SPL_FRAMEWORK |
234 | #define CONFIG_SPL_NAND_SIMPLE | |
235 | ||
e2ccdf89 | 236 | #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 |
205b4f33 | 237 | #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" |
a9f52490 | 238 | |
a9f52490 SR |
239 | #define CONFIG_SPL_NAND_BASE |
240 | #define CONFIG_SPL_NAND_DRIVERS | |
241 | #define CONFIG_SPL_NAND_ECC | |
a9f52490 | 242 | #define CONFIG_SPL_OMAP3_ID_NAND |
983e3700 | 243 | #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" |
a9f52490 SR |
244 | |
245 | /* NAND boot config */ | |
246 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE | |
247 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 | |
248 | #define CONFIG_SYS_NAND_PAGE_SIZE 2048 | |
249 | #define CONFIG_SYS_NAND_OOBSIZE 64 | |
250 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
251 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS | |
252 | /* | |
253 | * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: | |
254 | * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT | |
255 | */ | |
256 | #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ | |
257 | 10, 11, 12, 13 } | |
258 | #define CONFIG_SYS_NAND_ECCSIZE 512 | |
259 | #define CONFIG_SYS_NAND_ECCBYTES 3 | |
260 | #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW | |
261 | ||
262 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE | |
263 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 | |
264 | ||
265 | #define CONFIG_SPL_TEXT_BASE 0x40200800 | |
fa2f81b0 TR |
266 | #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ |
267 | CONFIG_SPL_TEXT_BASE) | |
a9f52490 SR |
268 | |
269 | /* | |
270 | * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the | |
271 | * older x-loader implementations. And move the BSS area so that it | |
272 | * doesn't overlap with TEXT_BASE. | |
273 | */ | |
274 | #define CONFIG_SYS_TEXT_BASE 0x80008000 | |
275 | #define CONFIG_SPL_BSS_START_ADDR 0x80100000 | |
276 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ | |
277 | ||
278 | #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 | |
279 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 | |
280 | ||
550e3756 | 281 | #endif /* __CONFIG_H */ |