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3ef5ebeb LV |
1 | /* |
2 | * (C) Copyright 2013 | |
3 | * Texas Instruments Incorporated. | |
4 | * Sricharan R <r.sricharan@ti.com> | |
5 | * | |
6 | * Derived from OMAP4 done by: | |
7 | * Aneesh V <aneesh@ti.com> | |
8 | * | |
9 | * TI OMAP5 AND DRA7XX common configuration settings | |
10 | * | |
3765b3e7 | 11 | * SPDX-License-Identifier: GPL-2.0+ |
a8017574 TR |
12 | * |
13 | * For more details, please see the technical documents listed at | |
14 | * http://www.ti.com/product/omap5432 | |
3ef5ebeb LV |
15 | */ |
16 | ||
3d657a05 EBS |
17 | #ifndef __CONFIG_TI_OMAP5_COMMON_H |
18 | #define __CONFIG_TI_OMAP5_COMMON_H | |
3ef5ebeb | 19 | |
3ef5ebeb LV |
20 | #define CONFIG_DISPLAY_CPUINFO |
21 | #define CONFIG_DISPLAY_BOARDINFO | |
3ef5ebeb | 22 | |
5f603761 PR |
23 | /* Common ARM Erratas */ |
24 | #define CONFIG_ARM_ERRATA_798870 | |
25 | ||
a8017574 TR |
26 | /* Use General purpose timer 1 */ |
27 | #define CONFIG_SYS_TIMERBASE GPT2_BASE | |
28 | ||
078aa4f1 TR |
29 | /* |
30 | * For the DDR timing information we can either dynamically determine | |
31 | * the timings to use or use pre-determined timings (based on using the | |
32 | * dynamic method. Default to the static timing infomation. | |
33 | */ | |
a8017574 | 34 | #define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS |
a8017574 TR |
35 | #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS |
36 | #define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION | |
37 | #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS | |
38 | #endif | |
39 | ||
a8017574 | 40 | #define CONFIG_PALMAS_POWER |
a8017574 TR |
41 | |
42 | #include <asm/arch/cpu.h> | |
43 | #include <asm/arch/omap.h> | |
3ef5ebeb | 44 | |
9a0f4004 | 45 | #include <configs/ti_armv7_omap.h> |
3ef5ebeb LV |
46 | |
47 | /* | |
a8017574 | 48 | * Hardware drivers |
3ef5ebeb | 49 | */ |
c7b9686d | 50 | #define CONFIG_SYS_NS16550_CLK 48000000 |
01e870b7 | 51 | #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL) |
3ef5ebeb LV |
52 | #define CONFIG_SYS_NS16550_SERIAL |
53 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
01e870b7 | 54 | #endif |
3ef5ebeb | 55 | |
3ef5ebeb LV |
56 | /* |
57 | * Environment setup | |
58 | */ | |
9552ee3e TR |
59 | #ifndef PARTS_DEFAULT |
60 | #define PARTS_DEFAULT | |
61 | #endif | |
62 | ||
7a5a3e37 KVA |
63 | #ifndef DFUARGS |
64 | #define DFUARGS | |
65 | #endif | |
66 | ||
08520bf5 | 67 | #ifndef CONFIG_SPL_BUILD |
4ec3f6e5 | 68 | #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
3ef5ebeb | 69 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
fb3ad9bd | 70 | DEFAULT_LINUX_BOOT_ENV \ |
85d17be3 | 71 | DEFAULT_MMC_TI_ARGS \ |
f6723794 | 72 | "console=" CONSOLEDEV ",115200n8\0" \ |
a7143215 | 73 | "fdtfile=undefined\0" \ |
143070df S |
74 | "bootpart=0:2\0" \ |
75 | "bootdir=/boot\0" \ | |
aaed0a23 | 76 | "bootfile=zImage\0" \ |
3ef5ebeb LV |
77 | "usbtty=cdc_acm\0" \ |
78 | "vram=16M\0" \ | |
9552ee3e | 79 | "partitions=" PARTS_DEFAULT "\0" \ |
85b7ac45 | 80 | "optargs=\0" \ |
16862604 | 81 | "dofastboot=0\0" \ |
3ef5ebeb LV |
82 | "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ |
83 | "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ | |
84 | "source ${loadaddr}\0" \ | |
143070df | 85 | "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ |
7406d321 TR |
86 | "mmcboot=mmc dev ${mmcdev}; " \ |
87 | "if mmc rescan; then " \ | |
88 | "echo SD/MMC found on device ${mmcdev};" \ | |
7406d321 TR |
89 | "if run loadimage; then " \ |
90 | "run loadfdt; " \ | |
91 | "echo Booting from mmc${mmcdev} ...; " \ | |
85d17be3 | 92 | "run args_mmc; " \ |
7406d321 TR |
93 | "bootz ${loadaddr} - ${fdtaddr}; " \ |
94 | "fi;" \ | |
95 | "fi;\0" \ | |
143070df S |
96 | "findfdt="\ |
97 | "if test $board_name = omap5_uevm; then " \ | |
a7143215 | 98 | "setenv fdtfile omap5-uevm.dtb; fi; " \ |
45dbbf29 DM |
99 | "if test $board_name = dra7xx; then " \ |
100 | "setenv fdtfile dra7-evm.dtb; fi;" \ | |
df6b506f LV |
101 | "if test $board_name = dra72x-revc; then " \ |
102 | "setenv fdtfile dra72-evm-revc.dtb; fi;" \ | |
4ec3f6e5 LV |
103 | "if test $board_name = dra72x; then " \ |
104 | "setenv fdtfile dra72-evm.dtb; fi;" \ | |
1e4ad74b FB |
105 | "if test $board_name = beagle_x15; then " \ |
106 | "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \ | |
cc5cdaad LV |
107 | "if test $board_name = am572x_idk; then " \ |
108 | "setenv fdtfile am572x-idk.dtb; fi;" \ | |
212f96f6 KS |
109 | "if test $board_name = am57xx_evm; then " \ |
110 | "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \ | |
a7143215 DM |
111 | "if test $fdtfile = undefined; then " \ |
112 | "echo WARNING: Could not determine device tree to use; fi; \0" \ | |
143070df | 113 | "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile};\0" \ |
7a5a3e37 | 114 | DFUARGS \ |
2320866b | 115 | NETARGS \ |
3ef5ebeb LV |
116 | |
117 | #define CONFIG_BOOTCOMMAND \ | |
ecd85579 DK |
118 | "if test ${dofastboot} -eq 1; then " \ |
119 | "echo Boot fastboot requested, resetting dofastboot ...;" \ | |
120 | "setenv dofastboot 0; saveenv;" \ | |
8d2f0039 | 121 | "echo Booting into fastboot ...; fastboot 0;" \ |
ecd85579 | 122 | "fi;" \ |
143070df | 123 | "run findfdt; " \ |
18c534bb | 124 | "run envboot; " \ |
7406d321 TR |
125 | "run mmcboot;" \ |
126 | "setenv mmcdev 1; " \ | |
127 | "setenv bootpart 1:2; " \ | |
128 | "setenv mmcroot /dev/mmcblk0p2 rw; " \ | |
129 | "run mmcboot;" \ | |
ecd85579 | 130 | "" |
08520bf5 | 131 | #endif |
3ef5ebeb | 132 | |
078aa4f1 TR |
133 | /* |
134 | * SPL related defines. The Public RAM memory map the ROM defines the | |
b9b8403f DA |
135 | * area between 0x40300000 and 0x4031E000 as a download area for OMAP5. |
136 | * On DRA7xx/AM57XX the download area is between 0x40300000 and 0x4037E000. | |
137 | * We set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and | |
078aa4f1 TR |
138 | * print some information. |
139 | */ | |
b9b8403f DA |
140 | #ifdef CONFIG_TI_SECURE_DEVICE |
141 | /* | |
142 | * For memory booting on HS parts, the first 4KB of the internal RAM is | |
143 | * reserved for secure world use and the flash loader image is | |
144 | * preceded by a secure certificate. The SPL will therefore run in internal | |
145 | * RAM from address 0x40301350 (0x40300000+0x1000(reserved)+0x350(cert)). | |
146 | */ | |
147 | #define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ 0x1000 | |
148 | #define CONFIG_SPL_TEXT_BASE 0x40301350 | |
149 | #else | |
150 | /* | |
151 | * For all booting on GP parts, the flash loader image is | |
152 | * downloaded into internal RAM at address 0x40300000. | |
153 | */ | |
154 | #define CONFIG_SPL_TEXT_BASE 0x40300000 | |
155 | #endif | |
156 | ||
157 | /* DRA7xx/AM57xx have 512K of SRAM, OMAP5 only 128K */ | |
158 | #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) | |
159 | #define TI_ROM_BOOT_LOAD_END 0x4037E000 | |
160 | #else | |
161 | #define TI_ROM_BOOT_LOAD_END 0x4031E000 | |
162 | #endif | |
163 | #define CONFIG_SPL_MAX_SIZE (TI_ROM_BOOT_LOAD_END - CONFIG_SPL_TEXT_BASE) | |
3ef5ebeb | 164 | #define CONFIG_SPL_DISPLAY_PRINT |
3ef5ebeb | 165 | #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" |
d3289aac TR |
166 | #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ |
167 | (128 << 20)) | |
3ef5ebeb | 168 | |
70e71b61 EBS |
169 | #ifdef CONFIG_NAND |
170 | #define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */ | |
171 | #endif | |
172 | ||
136b1013 M |
173 | /* |
174 | * Disable MMC DM for SPL build and can be re-enabled after adding | |
175 | * DM support in SPL | |
176 | */ | |
177 | #ifdef CONFIG_SPL_BUILD | |
178 | #undef CONFIG_DM_MMC | |
30a0cdb6 | 179 | #undef CONFIG_TIMER |
3d12e804 | 180 | #undef CONFIG_DM_ETH |
136b1013 M |
181 | #endif |
182 | ||
3d657a05 | 183 | #endif /* __CONFIG_TI_OMAP5_COMMON_H */ |