]>
Commit | Line | Data |
---|---|---|
1f03cbfa PT |
1 | /* |
2 | * Copyright 2008 Extreme Engineering Solutions, Inc. | |
3 | * Copyright 2004-2008 Freescale Semiconductor, Inc. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
1f03cbfa PT |
6 | */ |
7 | ||
8 | /* | |
c00ac259 | 9 | * xpedite520x board configuration file |
1f03cbfa PT |
10 | */ |
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
14 | /* | |
15 | * High Level Configuration Options | |
16 | */ | |
1f03cbfa | 17 | #define CONFIG_SYS_BOARD_NAME "XPedite5200" |
92af6549 | 18 | #define CONFIG_SYS_FORM_PMC_XMC 1 |
1f03cbfa | 19 | #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ |
1f03cbfa | 20 | |
2ae18241 WD |
21 | #ifndef CONFIG_SYS_TEXT_BASE |
22 | #define CONFIG_SYS_TEXT_BASE 0xfff80000 | |
23 | #endif | |
24 | ||
1f03cbfa PT |
25 | #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ |
26 | #define CONFIG_PCI1 1 /* PCI controller 1 */ | |
27 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ | |
842033e6 | 28 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ |
1f03cbfa | 29 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
1f03cbfa PT |
30 | |
31 | /* | |
32 | * DDR config | |
33 | */ | |
1f03cbfa PT |
34 | #undef CONFIG_FSL_DDR_INTERACTIVE |
35 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
36 | #define CONFIG_DDR_SPD | |
37 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
38 | #define SPD_EEPROM_ADDRESS 0x54 | |
1f03cbfa PT |
39 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
40 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 | |
41 | #define CONFIG_DDR_ECC | |
42 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
43 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
44 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
45 | #define CONFIG_VERY_BIG_RAM | |
46 | ||
47 | #define CONFIG_SYS_CLK_FREQ 66666666 | |
48 | ||
49 | /* | |
50 | * These can be toggled for performance analysis, otherwise use default. | |
51 | */ | |
52 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
53 | #define CONFIG_BTB /* toggle branch predition */ | |
54 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
55 | ||
e46fedfe TT |
56 | #define CONFIG_SYS_CCSRBAR 0xef000000 |
57 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
1f03cbfa PT |
58 | |
59 | /* | |
60 | * Diagnostics | |
61 | */ | |
62 | #define CONFIG_SYS_ALT_MEMTEST | |
63 | #define CONFIG_SYS_MEMTEST_START 0x10000000 | |
64 | #define CONFIG_SYS_MEMTEST_END 0x20000000 | |
66a8b440 PT |
65 | #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ |
66 | CONFIG_SYS_POST_I2C) | |
67 | #define I2C_ADDR_LIST {CONFIG_SYS_I2C_MAX1237_ADDR, \ | |
68 | CONFIG_SYS_I2C_EEPROM_ADDR, \ | |
69 | CONFIG_SYS_I2C_PCA953X_ADDR0, \ | |
70 | CONFIG_SYS_I2C_PCA953X_ADDR1, \ | |
71 | CONFIG_SYS_I2C_RTC_ADDR} | |
1f03cbfa PT |
72 | |
73 | /* | |
74 | * Memory map | |
75 | * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable | |
76 | * 0x8000_0000 0xbfff_ffff PCI1 Mem 1G non-cacheable | |
77 | * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable | |
78 | * 0xe800_0000 0xe87f_ffff PCI1 IO 8M non-cacheable | |
79 | * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable | |
80 | * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable | |
81 | * 0xf800_0000 0xfbff_ffff NOR Flash 2 64M non-cacheable | |
82 | * 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable | |
83 | */ | |
84 | ||
202d9487 | 85 | #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) |
1f03cbfa PT |
86 | |
87 | /* | |
88 | * NAND flash configuration | |
89 | */ | |
90 | #define CONFIG_SYS_NAND_BASE 0xef800000 | |
91 | #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ | |
92 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
93 | #define CONFIG_NAND_ACTL | |
94 | #define CONFIG_SYS_NAND_ACTL_CLE (1 << 3) /* ADDR3 is CLE */ | |
95 | #define CONFIG_SYS_NAND_ACTL_ALE (1 << 4) /* ADDR4 is ALE */ | |
96 | #define CONFIG_SYS_NAND_ACTL_NCE (0) /* NCE not controlled by ADDR */ | |
97 | #define CONFIG_SYS_NAND_ACTL_DELAY 25 | |
98 | ||
99 | /* | |
100 | * NOR flash configuration | |
101 | */ | |
102 | #define CONFIG_SYS_FLASH_BASE 0xfc000000 | |
103 | #define CONFIG_SYS_FLASH_BASE2 0xf8000000 | |
104 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} | |
105 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
106 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
107 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
108 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
109 | #define CONFIG_FLASH_CFI_DRIVER | |
110 | #define CONFIG_SYS_FLASH_CFI | |
5ff82100 | 111 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
1f03cbfa PT |
112 | #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \ |
113 | {0xfbf40000, 0xc0000} } | |
14d0a02a | 114 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
1f03cbfa PT |
115 | |
116 | /* | |
117 | * Chip select configuration | |
118 | */ | |
119 | /* NOR Flash 0 on CS0 */ | |
120 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ | |
121 | BR_PS_16 | \ | |
122 | BR_V) | |
123 | #define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB | \ | |
124 | OR_GPCM_ACS_DIV4 | \ | |
125 | OR_GPCM_SCY_8) | |
126 | ||
127 | /* NOR Flash 1 on CS1 */ | |
128 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \ | |
129 | BR_PS_16 | \ | |
130 | BR_V) | |
131 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM | |
132 | ||
133 | /* NAND flash on CS2 */ | |
134 | #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \ | |
135 | BR_PS_8 | \ | |
136 | BR_V) | |
137 | ||
138 | /* NAND flash on CS2 */ | |
139 | #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \ | |
140 | OR_GPCM_BCTLD | \ | |
141 | OR_GPCM_CSNT | \ | |
142 | OR_GPCM_ACS_DIV4 | \ | |
143 | OR_GPCM_SCY_4 | \ | |
144 | OR_GPCM_TRLX | \ | |
145 | OR_GPCM_EHTR) | |
146 | ||
147 | /* NAND flash on CS3 */ | |
148 | #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \ | |
149 | BR_PS_8 | \ | |
150 | BR_V) | |
151 | #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM | |
152 | ||
153 | /* | |
154 | * Use L1 as initial stack | |
155 | */ | |
156 | #define CONFIG_SYS_INIT_RAM_LOCK 1 | |
157 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 | |
553f0982 | 158 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 |
1f03cbfa | 159 | |
25ddd1fb | 160 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
1f03cbfa PT |
161 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
162 | ||
163 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ | |
164 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ | |
165 | ||
166 | /* | |
167 | * Serial Port | |
168 | */ | |
169 | #define CONFIG_CONS_INDEX 1 | |
1f03cbfa PT |
170 | #define CONFIG_SYS_NS16550_SERIAL |
171 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
172 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
173 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) | |
174 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
175 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
176 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} | |
1f03cbfa PT |
177 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
178 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
179 | ||
1f03cbfa PT |
180 | /* |
181 | * I2C | |
182 | */ | |
00f792e0 HS |
183 | #define CONFIG_SYS_I2C |
184 | #define CONFIG_SYS_I2C_FSL | |
185 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
186 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
187 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
188 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
189 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
190 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
1f03cbfa PT |
191 | |
192 | /* I2C EEPROM */ | |
193 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 | |
194 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
195 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ | |
196 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ | |
197 | ||
198 | /* I2C RTC */ | |
199 | #define CONFIG_RTC_M41T11 1 | |
200 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
201 | #define CONFIG_SYS_M41T11_BASE_YEAR 2000 | |
202 | ||
203 | /* GPIO */ | |
204 | #define CONFIG_PCA953X | |
205 | #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 | |
206 | #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x19 | |
207 | #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 | |
208 | ||
209 | /* PCA957 @ 0x18 */ | |
210 | #define CONFIG_SYS_PCA953X_BRD_CFG0 0x01 | |
211 | #define CONFIG_SYS_PCA953X_BRD_CFG1 0x02 | |
212 | #define CONFIG_SYS_PCA953X_BRD_CFG2 0x04 | |
213 | #define CONFIG_SYS_PCA953X_XMC_ROOT0 0x08 | |
214 | #define CONFIG_SYS_PCA953X_FLASH_PASS_CS 0x10 | |
72fb68d5 | 215 | #define CONFIG_SYS_PCA953X_NVM_WP 0x20 |
1f03cbfa PT |
216 | #define CONFIG_SYS_PCA953X_MONARCH 0x40 |
217 | #define CONFIG_SYS_PCA953X_EREADY 0x80 | |
218 | ||
219 | /* PCA957 @ 0x19 */ | |
220 | #define CONFIG_SYS_PCA953X_P14_IO0 0x01 | |
221 | #define CONFIG_SYS_PCA953X_P14_IO1 0x02 | |
222 | #define CONFIG_SYS_PCA953X_P14_IO2 0x04 | |
223 | #define CONFIG_SYS_PCA953X_P14_IO3 0x08 | |
224 | #define CONFIG_SYS_PCA953X_P14_IO4 0x10 | |
225 | #define CONFIG_SYS_PCA953X_P14_IO5 0x20 | |
226 | #define CONFIG_SYS_PCA953X_P14_IO6 0x40 | |
227 | #define CONFIG_SYS_PCA953X_P14_IO7 0x80 | |
228 | ||
66a8b440 PT |
229 | /* 12-bit ADC used to measure CPU diode */ |
230 | #define CONFIG_SYS_I2C_MAX1237_ADDR 0x34 | |
231 | ||
1f03cbfa PT |
232 | /* |
233 | * General PCI | |
234 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
235 | */ | |
9660c5de PT |
236 | #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 |
237 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS | |
1f03cbfa | 238 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x40000000 /* 1G */ |
9660c5de | 239 | #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 |
1f03cbfa PT |
240 | #define CONFIG_SYS_PCI1_IO_PHYS 0xe8000000 |
241 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 1M */ | |
242 | ||
243 | /* | |
244 | * Networking options | |
245 | */ | |
246 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
1f03cbfa PT |
247 | #define CONFIG_MII 1 /* MII PHY management */ |
248 | #define CONFIG_ETHPRIME "eTSEC1" | |
249 | ||
250 | #define CONFIG_TSEC1 1 | |
251 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
252 | #define TSEC1_FLAGS TSEC_GIGABIT | |
253 | #define TSEC1_PHY_ADDR 1 | |
254 | #define TSEC1_PHYIDX 0 | |
255 | #define CONFIG_HAS_ETH0 | |
256 | ||
257 | #define CONFIG_TSEC2 1 | |
258 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
259 | #define TSEC2_FLAGS TSEC_GIGABIT | |
260 | #define TSEC2_PHY_ADDR 2 | |
261 | #define TSEC2_PHYIDX 0 | |
262 | #define CONFIG_HAS_ETH1 | |
263 | ||
264 | #define CONFIG_TSEC3 1 | |
265 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
266 | #define TSEC3_FLAGS TSEC_GIGABIT | |
267 | #define TSEC3_PHY_ADDR 3 | |
268 | #define TSEC3_PHYIDX 0 | |
269 | #define CONFIG_HAS_ETH2 | |
270 | ||
271 | #define CONFIG_TSEC4 1 | |
272 | #define CONFIG_TSEC4_NAME "eTSEC4" | |
273 | #define TSEC4_FLAGS TSEC_GIGABIT | |
274 | #define TSEC4_PHY_ADDR 4 | |
275 | #define TSEC4_PHYIDX 0 | |
276 | #define CONFIG_HAS_ETH3 | |
277 | ||
278 | /* | |
279 | * BOOTP options | |
280 | */ | |
281 | #define CONFIG_BOOTP_BOOTFILESIZE | |
282 | #define CONFIG_BOOTP_BOOTPATH | |
283 | #define CONFIG_BOOTP_GATEWAY | |
284 | ||
1f03cbfa PT |
285 | /* |
286 | * Miscellaneous configurable options | |
287 | */ | |
288 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
289 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
1f03cbfa | 290 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
5be58f5f | 291 | #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ |
1f03cbfa | 292 | #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ |
1f03cbfa | 293 | #define CONFIG_PREBOOT /* enable preboot variable */ |
1f03cbfa PT |
294 | #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ |
295 | #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ | |
296 | ||
297 | /* | |
298 | * For booting Linux, the board info and command line data | |
299 | * have to be in the first 16 MB of memory, since this is | |
300 | * the maximum mapped by the Linux kernel during initialization. | |
301 | */ | |
302 | #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ | |
39121c08 | 303 | #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ |
1f03cbfa | 304 | |
1f03cbfa PT |
305 | /* |
306 | * Environment Configuration | |
307 | */ | |
1f03cbfa PT |
308 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ |
309 | #define CONFIG_ENV_SIZE 0x8000 | |
310 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024)) | |
311 | ||
312 | /* | |
313 | * Flash memory map: | |
314 | * fff80000 - ffffffff Pri U-Boot (512 KB) | |
315 | * fff40000 - fff7ffff Pri U-Boot Environment (256 KB) | |
316 | * fff00000 - fff3ffff Pri FDT (256KB) | |
317 | * fef00000 - ffefffff Pri OS image (16MB) | |
318 | * fc000000 - feefffff Pri OS Use/Filesystem (47MB) | |
319 | * | |
320 | * fbf80000 - fbffffff Sec U-Boot (512 KB) | |
321 | * fbf40000 - fbf7ffff Sec U-Boot Environment (256 KB) | |
322 | * fbf00000 - fbf3ffff Sec FDT (256KB) | |
323 | * faf00000 - fbefffff Sec OS image (16MB) | |
324 | * f8000000 - faefffff Sec OS Use/Filesystem (47MB) | |
325 | */ | |
5368c55d MV |
326 | #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000) |
327 | #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xfbf80000) | |
328 | #define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000) | |
329 | #define CONFIG_FDT2_ENV_ADDR __stringify(0xfbf00000) | |
330 | #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000) | |
331 | #define CONFIG_OS2_ENV_ADDR __stringify(0xfaf00000) | |
1f03cbfa PT |
332 | |
333 | #define CONFIG_PROG_UBOOT1 \ | |
334 | "$download_cmd $loadaddr $ubootfile; " \ | |
335 | "if test $? -eq 0; then " \ | |
336 | "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ | |
337 | "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ | |
338 | "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ | |
339 | "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ | |
340 | "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ | |
341 | "if test $? -ne 0; then " \ | |
342 | "echo PROGRAM FAILED; " \ | |
343 | "else; " \ | |
344 | "echo PROGRAM SUCCEEDED; " \ | |
345 | "fi; " \ | |
346 | "else; " \ | |
347 | "echo DOWNLOAD FAILED; " \ | |
348 | "fi;" | |
349 | ||
350 | #define CONFIG_PROG_UBOOT2 \ | |
351 | "$download_cmd $loadaddr $ubootfile; " \ | |
352 | "if test $? -eq 0; then " \ | |
353 | "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ | |
354 | "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ | |
355 | "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ | |
356 | "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ | |
357 | "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ | |
358 | "if test $? -ne 0; then " \ | |
359 | "echo PROGRAM FAILED; " \ | |
360 | "else; " \ | |
361 | "echo PROGRAM SUCCEEDED; " \ | |
362 | "fi; " \ | |
363 | "else; " \ | |
364 | "echo DOWNLOAD FAILED; " \ | |
365 | "fi;" | |
366 | ||
367 | #define CONFIG_BOOT_OS_NET \ | |
368 | "$download_cmd $osaddr $osfile; " \ | |
369 | "if test $? -eq 0; then " \ | |
370 | "if test -n $fdtaddr; then " \ | |
371 | "$download_cmd $fdtaddr $fdtfile; " \ | |
372 | "if test $? -eq 0; then " \ | |
373 | "bootm $osaddr - $fdtaddr; " \ | |
374 | "else; " \ | |
375 | "echo FDT DOWNLOAD FAILED; " \ | |
376 | "fi; " \ | |
377 | "else; " \ | |
378 | "bootm $osaddr; " \ | |
379 | "fi; " \ | |
380 | "else; " \ | |
381 | "echo OS DOWNLOAD FAILED; " \ | |
382 | "fi;" | |
383 | ||
384 | #define CONFIG_PROG_OS1 \ | |
385 | "$download_cmd $osaddr $osfile; " \ | |
386 | "if test $? -eq 0; then " \ | |
387 | "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ | |
388 | "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ | |
389 | "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ | |
390 | "if test $? -ne 0; then " \ | |
391 | "echo OS PROGRAM FAILED; " \ | |
392 | "else; " \ | |
393 | "echo OS PROGRAM SUCCEEDED; " \ | |
394 | "fi; " \ | |
395 | "else; " \ | |
396 | "echo OS DOWNLOAD FAILED; " \ | |
397 | "fi;" | |
398 | ||
399 | #define CONFIG_PROG_OS2 \ | |
400 | "$download_cmd $osaddr $osfile; " \ | |
401 | "if test $? -eq 0; then " \ | |
402 | "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ | |
403 | "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ | |
404 | "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ | |
405 | "if test $? -ne 0; then " \ | |
406 | "echo OS PROGRAM FAILED; " \ | |
407 | "else; " \ | |
408 | "echo OS PROGRAM SUCCEEDED; " \ | |
409 | "fi; " \ | |
410 | "else; " \ | |
411 | "echo OS DOWNLOAD FAILED; " \ | |
412 | "fi;" | |
413 | ||
414 | #define CONFIG_PROG_FDT1 \ | |
415 | "$download_cmd $fdtaddr $fdtfile; " \ | |
416 | "if test $? -eq 0; then " \ | |
417 | "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ | |
418 | "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ | |
419 | "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ | |
420 | "if test $? -ne 0; then " \ | |
421 | "echo FDT PROGRAM FAILED; " \ | |
422 | "else; " \ | |
423 | "echo FDT PROGRAM SUCCEEDED; " \ | |
424 | "fi; " \ | |
425 | "else; " \ | |
426 | "echo FDT DOWNLOAD FAILED; " \ | |
427 | "fi;" | |
428 | ||
429 | #define CONFIG_PROG_FDT2 \ | |
430 | "$download_cmd $fdtaddr $fdtfile; " \ | |
431 | "if test $? -eq 0; then " \ | |
432 | "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ | |
433 | "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ | |
434 | "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ | |
435 | "if test $? -ne 0; then " \ | |
436 | "echo FDT PROGRAM FAILED; " \ | |
437 | "else; " \ | |
438 | "echo FDT PROGRAM SUCCEEDED; " \ | |
439 | "fi; " \ | |
440 | "else; " \ | |
441 | "echo FDT DOWNLOAD FAILED; " \ | |
442 | "fi;" | |
443 | ||
444 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
445 | "autoload=yes\0" \ | |
446 | "download_cmd=tftp\0" \ | |
447 | "console_args=console=ttyS0,115200\0" \ | |
448 | "root_args=root=/dev/nfs rw\0" \ | |
449 | "misc_args=ip=on\0" \ | |
450 | "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ | |
451 | "bootfile=/home/user/file\0" \ | |
c00ac259 PT |
452 | "osfile=/home/user/board.uImage\0" \ |
453 | "fdtfile=/home/user/board.dtb\0" \ | |
1f03cbfa | 454 | "ubootfile=/home/user/u-boot.bin\0" \ |
b24a4f62 | 455 | "fdtaddr=0x1e00000\0" \ |
1f03cbfa PT |
456 | "osaddr=0x1000000\0" \ |
457 | "loadaddr=0x1000000\0" \ | |
458 | "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ | |
459 | "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ | |
460 | "prog_os1="CONFIG_PROG_OS1"\0" \ | |
461 | "prog_os2="CONFIG_PROG_OS2"\0" \ | |
462 | "prog_fdt1="CONFIG_PROG_FDT1"\0" \ | |
463 | "prog_fdt2="CONFIG_PROG_FDT2"\0" \ | |
464 | "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ | |
465 | "bootcmd_flash1=run set_bootargs; " \ | |
466 | "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ | |
467 | "bootcmd_flash2=run set_bootargs; " \ | |
468 | "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ | |
469 | "bootcmd=run bootcmd_flash1\0" | |
470 | #endif /* __CONFIG_H */ |