projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| ccf0fdd0 PT |
1 | /* |
| 2 | * Copyright 2008 Extreme Engineering Solutions, Inc. | |
| 3 | * Copyright 2007-2008 Freescale Semiconductor, Inc. | |
| 4 | * | |
| 1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| ccf0fdd0 PT |
6 | */ |
| 7 | ||
| 8 | /* | |
| c00ac259 | 9 | * xpedite537x board configuration file |
| ccf0fdd0 PT |
10 | */ |
| 11 | #ifndef __CONFIG_H | |
| 12 | #define __CONFIG_H | |
| 13 | ||
| 14 | /* | |
| 15 | * High Level Configuration Options | |
| 16 | */ | |
| ccf0fdd0 | 17 | #define CONFIG_SYS_BOARD_NAME "XPedite5370" |
| 92af6549 | 18 | #define CONFIG_SYS_FORM_3U_VPX 1 |
| ccf0fdd0 | 19 | #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ |
| ccf0fdd0 | 20 | |
| 2ae18241 WD |
21 | #ifndef CONFIG_SYS_TEXT_BASE |
| 22 | #define CONFIG_SYS_TEXT_BASE 0xfff80000 | |
| 23 | #endif | |
| 24 | ||
| ccf0fdd0 | 25 | #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ |
| b38eaec5 RD |
26 | #define CONFIG_PCIE1 1 /* PCIE controller 1 */ |
| 27 | #define CONFIG_PCIE2 1 /* PCIE controller 2 */ | |
| ccf0fdd0 | 28 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ |
| 842033e6 | 29 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ |
| ccf0fdd0 PT |
30 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
| 31 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ | |
| 0914f483 | 32 | #define CONFIG_FSL_ELBC 1 |
| ccf0fdd0 | 33 | |
| 48618126 PT |
34 | /* |
| 35 | * Multicore config | |
| 36 | */ | |
| 37 | #define CONFIG_MP | |
| 38 | #define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */ | |
| 39 | #define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */ | |
| 40 | ||
| ccf0fdd0 PT |
41 | /* |
| 42 | * DDR config | |
| 43 | */ | |
| 5614e71b | 44 | #define CONFIG_SYS_FSL_DDR2 |
| ccf0fdd0 PT |
45 | #undef CONFIG_FSL_DDR_INTERACTIVE |
| 46 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
| 47 | #define CONFIG_DDR_SPD | |
| 48 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
| 49 | #define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */ | |
| 50 | #define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */ | |
| 51 | #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */ | |
| 52 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
| 53 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
| 54 | #define CONFIG_CHIP_SELECTS_PER_CTRL 1 | |
| 55 | #define CONFIG_DDR_ECC | |
| 56 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
| 57 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ | |
| 58 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
| 59 | #define CONFIG_VERY_BIG_RAM | |
| 60 | ||
| 61 | #ifndef __ASSEMBLY__ | |
| 62 | extern unsigned long get_board_sys_clk(unsigned long dummy); | |
| 63 | extern unsigned long get_board_ddr_clk(unsigned long dummy); | |
| 64 | #endif | |
| 65 | ||
| 66 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ | |
| 67 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */ | |
| 68 | ||
| 69 | /* | |
| 70 | * These can be toggled for performance analysis, otherwise use default. | |
| 71 | */ | |
| 72 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
| 73 | #define CONFIG_BTB /* toggle branch predition */ | |
| 74 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
| 75 | ||
| e46fedfe TT |
76 | #define CONFIG_SYS_CCSRBAR 0xef000000 |
| 77 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
| ccf0fdd0 PT |
78 | |
| 79 | /* | |
| 80 | * Diagnostics | |
| 81 | */ | |
| 82 | #define CONFIG_SYS_ALT_MEMTEST | |
| 83 | #define CONFIG_SYS_MEMTEST_START 0x10000000 | |
| 84 | #define CONFIG_SYS_MEMTEST_END 0x20000000 | |
| 66a8b440 PT |
85 | #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ |
| 86 | CONFIG_SYS_POST_I2C) | |
| 87 | #define I2C_ADDR_LIST {CONFIG_SYS_I2C_DS1621_ADDR, \ | |
| 88 | CONFIG_SYS_I2C_DS4510_ADDR, \ | |
| 89 | CONFIG_SYS_I2C_EEPROM_ADDR, \ | |
| 90 | CONFIG_SYS_I2C_LM90_ADDR, \ | |
| 91 | CONFIG_SYS_I2C_PCA953X_ADDR0, \ | |
| 92 | CONFIG_SYS_I2C_PCA953X_ADDR1, \ | |
| 93 | CONFIG_SYS_I2C_PCA953X_ADDR2, \ | |
| 94 | CONFIG_SYS_I2C_PCA953X_ADDR3, \ | |
| 95 | CONFIG_SYS_I2C_PEX8518_ADDR, \ | |
| 96 | CONFIG_SYS_I2C_RTC_ADDR} | |
| 97 | /* The XPedite5370 can host an XMC which has an EEPROM at address 0x50 */ | |
| 98 | #define I2C_ADDR_IGNORE_LIST {0x50} | |
| ccf0fdd0 PT |
99 | |
| 100 | /* | |
| 101 | * Memory map | |
| 102 | * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable | |
| 103 | * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable | |
| 104 | * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable | |
| 105 | * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable | |
| 106 | * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable | |
| 107 | * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable | |
| 48618126 | 108 | * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable |
| ccf0fdd0 PT |
109 | * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable |
| 110 | * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable | |
| 111 | * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable | |
| 112 | * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable | |
| 113 | */ | |
| 114 | ||
| 202d9487 | 115 | #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) |
| ccf0fdd0 PT |
116 | |
| 117 | /* | |
| 118 | * NAND flash configuration | |
| 119 | */ | |
| 120 | #define CONFIG_SYS_NAND_BASE 0xef800000 | |
| 121 | #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ | |
| 0a6d0c63 PT |
122 | #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \ |
| 123 | CONFIG_SYS_NAND_BASE2} | |
| 124 | #define CONFIG_SYS_MAX_NAND_DEVICE 2 | |
| 0a6d0c63 | 125 | #define CONFIG_NAND_FSL_ELBC |
| ccf0fdd0 PT |
126 | |
| 127 | /* | |
| 128 | * NOR flash configuration | |
| 129 | */ | |
| 130 | #define CONFIG_SYS_FLASH_BASE 0xf8000000 | |
| 131 | #define CONFIG_SYS_FLASH_BASE2 0xf0000000 | |
| 132 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} | |
| 133 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
| 134 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
| 135 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 136 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 137 | #define CONFIG_FLASH_CFI_DRIVER | |
| 138 | #define CONFIG_SYS_FLASH_CFI | |
| 5ff82100 | 139 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
| ccf0fdd0 PT |
140 | #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \ |
| 141 | {0xf7f40000, 0xc0000} } | |
| 14d0a02a | 142 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
| ccf0fdd0 PT |
143 | |
| 144 | /* | |
| 145 | * Chip select configuration | |
| 146 | */ | |
| 147 | /* NOR Flash 0 on CS0 */ | |
| 148 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ | |
| 149 | BR_PS_16 | \ | |
| 150 | BR_V) | |
| 151 | #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \ | |
| 152 | OR_GPCM_CSNT | \ | |
| 153 | OR_GPCM_XACS | \ | |
| 154 | OR_GPCM_ACS_DIV2 | \ | |
| 155 | OR_GPCM_SCY_8 | \ | |
| 156 | OR_GPCM_TRLX | \ | |
| 157 | OR_GPCM_EHTR | \ | |
| 158 | OR_GPCM_EAD) | |
| 159 | ||
| 160 | /* NOR Flash 1 on CS1 */ | |
| 161 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \ | |
| 162 | BR_PS_16 | \ | |
| 163 | BR_V) | |
| 164 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM | |
| 165 | ||
| 166 | /* NAND flash on CS2 */ | |
| 167 | #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \ | |
| 168 | (2<<BR_DECC_SHIFT) | \ | |
| 169 | BR_PS_8 | \ | |
| 170 | BR_MS_FCM | \ | |
| 171 | BR_V) | |
| 172 | ||
| 173 | /* NAND flash on CS2 */ | |
| 174 | #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \ | |
| 175 | OR_FCM_PGS | \ | |
| 176 | OR_FCM_CSCT | \ | |
| 177 | OR_FCM_CST | \ | |
| 178 | OR_FCM_CHT | \ | |
| 179 | OR_FCM_SCY_1 | \ | |
| 180 | OR_FCM_TRLX | \ | |
| 181 | OR_FCM_EHTR) | |
| 182 | ||
| 183 | /* NAND flash on CS3 */ | |
| 184 | #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \ | |
| 185 | (2<<BR_DECC_SHIFT) | \ | |
| 186 | BR_PS_8 | \ | |
| 187 | BR_MS_FCM | \ | |
| 188 | BR_V) | |
| 189 | #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM | |
| 190 | ||
| 191 | /* | |
| 192 | * Use L1 as initial stack | |
| 193 | */ | |
| 194 | #define CONFIG_SYS_INIT_RAM_LOCK 1 | |
| 195 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 | |
| 553f0982 | 196 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 |
| ccf0fdd0 | 197 | |
| 25ddd1fb | 198 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
| ccf0fdd0 PT |
199 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| 200 | ||
| 201 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ | |
| 202 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ | |
| 203 | ||
| 204 | /* | |
| 205 | * Serial Port | |
| 206 | */ | |
| 207 | #define CONFIG_CONS_INDEX 1 | |
| ccf0fdd0 PT |
208 | #define CONFIG_SYS_NS16550_SERIAL |
| 209 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 210 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
| 211 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) | |
| 212 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
| 213 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
| 214 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} | |
| 215 | #define CONFIG_BAUDRATE 115200 | |
| 216 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 217 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
| 218 | ||
| ccf0fdd0 PT |
219 | /* |
| 220 | * I2C | |
| 221 | */ | |
| 00f792e0 HS |
222 | #define CONFIG_SYS_I2C |
| 223 | #define CONFIG_SYS_I2C_FSL | |
| 224 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
| 225 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
| 226 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
| 227 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
| 228 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
| 229 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
| 230 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
| ccf0fdd0 PT |
231 | |
| 232 | /* PEX8518 slave I2C interface */ | |
| 233 | #define CONFIG_SYS_I2C_PEX8518_ADDR 0x70 | |
| 234 | ||
| 235 | /* I2C DS1631 temperature sensor */ | |
| 236 | #define CONFIG_SYS_I2C_DS1621_ADDR 0x48 | |
| 237 | #define CONFIG_DTT_DS1621 | |
| 238 | #define CONFIG_DTT_SENSORS { 0 } | |
| 66a8b440 | 239 | #define CONFIG_SYS_I2C_LM90_ADDR 0x4c |
| ccf0fdd0 PT |
240 | |
| 241 | /* I2C EEPROM - AT24C128B */ | |
| 242 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 | |
| 243 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
| 244 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ | |
| 245 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ | |
| 246 | ||
| 247 | /* I2C RTC */ | |
| 248 | #define CONFIG_RTC_M41T11 1 | |
| 249 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
| 250 | #define CONFIG_SYS_M41T11_BASE_YEAR 2000 | |
| 251 | ||
| 252 | /* GPIO/EEPROM/SRAM */ | |
| 253 | #define CONFIG_DS4510 | |
| 254 | #define CONFIG_SYS_I2C_DS4510_ADDR 0x51 | |
| 255 | ||
| 256 | /* GPIO */ | |
| 257 | #define CONFIG_PCA953X | |
| 258 | #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 | |
| 259 | #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c | |
| 260 | #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e | |
| 261 | #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f | |
| 262 | #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 | |
| 263 | ||
| 264 | /* | |
| 265 | * PU = pulled high, PD = pulled low | |
| 266 | * I = input, O = output, IO = input/output | |
| 267 | */ | |
| 268 | /* PCA9557 @ 0x18*/ | |
| 269 | #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */ | |
| 270 | #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */ | |
| 271 | #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */ | |
| 272 | #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */ | |
| 273 | #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */ | |
| 274 | #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */ | |
| 275 | #define CONFIG_SYS_PCA953X_C0_VCORE_VID2 0x40 /* VID2 of ISL6262 */ | |
| 276 | #define CONFIG_SYS_PCA953X_C0_VCORE_VID3 0x80 /* VID3 of ISL6262 */ | |
| 277 | ||
| 278 | /* PCA9557 @ 0x1c*/ | |
| 279 | #define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */ | |
| 280 | #define CONFIG_SYS_PCA953X_XMC0_MVMR0 0x02 /* XMC EEPROM write protect */ | |
| 281 | #define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */ | |
| 282 | #define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */ | |
| 283 | #define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */ | |
| 284 | #define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */ | |
| 285 | #define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */ | |
| 286 | #define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */ | |
| 287 | ||
| 288 | /* PCA9557 @ 0x1e*/ | |
| 289 | #define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */ | |
| 290 | #define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */ | |
| 291 | #define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */ | |
| 292 | #define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */ | |
| 293 | #define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */ | |
| 294 | #define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; tied to VPX P0.GAP */ | |
| 295 | #define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */ | |
| 296 | ||
| 297 | /* PCA9557 @ 0x1f */ | |
| 298 | #define CONFIG_SYS_PCA953X_GPIO_VPX0 0x01 /* PU */ | |
| 299 | #define CONFIG_SYS_PCA953X_GPIO_VPX1 0x02 /* PU */ | |
| 300 | #define CONFIG_SYS_PCA953X_GPIO_VPX2 0x04 /* PU */ | |
| 301 | #define CONFIG_SYS_PCA953X_GPIO_VPX3 0x08 /* PU */ | |
| 302 | #define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL 0x10 /* PD; I2C master source for FRU SEEPROM */ | |
| 303 | ||
| 304 | /* | |
| 305 | * General PCI | |
| 306 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
| 307 | */ | |
| 308 | /* PCIE1 - VPX P1 */ | |
| 9660c5de PT |
309 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 |
| 310 | #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS | |
| ccf0fdd0 | 311 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */ |
| 9660c5de | 312 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
| ccf0fdd0 PT |
313 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000 |
| 314 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ | |
| 315 | ||
| 316 | /* PCIE2 - PEX8518 */ | |
| 9660c5de PT |
317 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 |
| 318 | #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS | |
| ccf0fdd0 | 319 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ |
| 9660c5de | 320 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 |
| ccf0fdd0 PT |
321 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000 |
| 322 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */ | |
| 323 | ||
| 324 | /* | |
| 325 | * Networking options | |
| 326 | */ | |
| 327 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
| 328 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
| ccf0fdd0 PT |
329 | #define CONFIG_TSEC_TBI |
| 330 | #define CONFIG_MII 1 /* MII PHY management */ | |
| 331 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ | |
| 332 | #define CONFIG_ETHPRIME "eTSEC2" | |
| 333 | ||
| 72c96a68 KG |
334 | /* |
| 335 | * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force | |
| 336 | * 1000mbps SGMII link | |
| 337 | */ | |
| 338 | #define CONFIG_TSEC_TBICR_SETTINGS ( \ | |
| 339 | TBICR_PHY_RESET \ | |
| 340 | | TBICR_FULL_DUPLEX \ | |
| 341 | | TBICR_SPEED1_SET \ | |
| 342 | ) | |
| 343 | ||
| ccf0fdd0 PT |
344 | #define CONFIG_TSEC1 1 |
| 345 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
| 346 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 347 | #define TSEC1_PHY_ADDR 1 | |
| 348 | #define TSEC1_PHYIDX 0 | |
| 349 | #define CONFIG_HAS_ETH0 | |
| 350 | ||
| 351 | #define CONFIG_TSEC2 1 | |
| 352 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
| 353 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 354 | #define TSEC2_PHY_ADDR 2 | |
| 355 | #define TSEC2_PHYIDX 0 | |
| 356 | #define CONFIG_HAS_ETH1 | |
| 357 | ||
| 358 | /* | |
| 359 | * Command configuration. | |
| 360 | */ | |
| ccf0fdd0 | 361 | #define CONFIG_CMD_DATE |
| ccf0fdd0 PT |
362 | #define CONFIG_CMD_DS4510 |
| 363 | #define CONFIG_CMD_DS4510_INFO | |
| 364 | #define CONFIG_CMD_DTT | |
| 365 | #define CONFIG_CMD_EEPROM | |
| ccf0fdd0 | 366 | #define CONFIG_CMD_JFFS2 |
| 0a6d0c63 | 367 | #define CONFIG_CMD_NAND |
| ccf0fdd0 PT |
368 | #define CONFIG_CMD_PCA953X |
| 369 | #define CONFIG_CMD_PCA953X_INFO | |
| 370 | #define CONFIG_CMD_PCI | |
| 96d61603 | 371 | #define CONFIG_CMD_PCI_ENUM |
| 199e262e | 372 | #define CONFIG_CMD_REGINFO |
| ccf0fdd0 PT |
373 | |
| 374 | /* | |
| 375 | * Miscellaneous configurable options | |
| 376 | */ | |
| 377 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
| 378 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
| ccf0fdd0 PT |
379 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| 380 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
| 381 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 382 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
| ccf0fdd0 | 383 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
| 5be58f5f | 384 | #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ |
| ccf0fdd0 | 385 | #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ |
| ccf0fdd0 PT |
386 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ |
| 387 | #define CONFIG_PREBOOT /* enable preboot variable */ | |
| ccf0fdd0 PT |
388 | #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ |
| 389 | ||
| 390 | /* | |
| 391 | * For booting Linux, the board info and command line data | |
| 392 | * have to be in the first 16 MB of memory, since this is | |
| 393 | * the maximum mapped by the Linux kernel during initialization. | |
| 394 | */ | |
| 395 | #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ | |
| 39121c08 | 396 | #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ |
| ccf0fdd0 | 397 | |
| ccf0fdd0 PT |
398 | /* |
| 399 | * Environment Configuration | |
| 400 | */ | |
| 401 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
| 402 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ | |
| 403 | #define CONFIG_ENV_SIZE 0x8000 | |
| 404 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024)) | |
| 405 | ||
| 406 | /* | |
| 407 | * Flash memory map: | |
| 408 | * fff80000 - ffffffff Pri U-Boot (512 KB) | |
| 409 | * fff40000 - fff7ffff Pri U-Boot Environment (256 KB) | |
| 410 | * fff00000 - fff3ffff Pri FDT (256KB) | |
| 411 | * fef00000 - ffefffff Pri OS image (16MB) | |
| 412 | * f8000000 - feefffff Pri OS Use/Filesystem (111MB) | |
| 413 | * | |
| 414 | * f7f80000 - f7ffffff Sec U-Boot (512 KB) | |
| 415 | * f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB) | |
| 416 | * f7f00000 - f7f3ffff Sec FDT (256KB) | |
| 417 | * f6f00000 - f7efffff Sec OS image (16MB) | |
| 418 | * f0000000 - f6efffff Sec OS Use/Filesystem (111MB) | |
| 419 | */ | |
| 5368c55d MV |
420 | #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000) |
| 421 | #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f80000) | |
| 422 | #define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000) | |
| 423 | #define CONFIG_FDT2_ENV_ADDR __stringify(0xf7f00000) | |
| 424 | #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000) | |
| 425 | #define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000) | |
| ccf0fdd0 PT |
426 | |
| 427 | #define CONFIG_PROG_UBOOT1 \ | |
| 428 | "$download_cmd $loadaddr $ubootfile; " \ | |
| 429 | "if test $? -eq 0; then " \ | |
| 430 | "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ | |
| 431 | "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ | |
| 432 | "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ | |
| 433 | "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ | |
| 434 | "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ | |
| 435 | "if test $? -ne 0; then " \ | |
| 436 | "echo PROGRAM FAILED; " \ | |
| 437 | "else; " \ | |
| 438 | "echo PROGRAM SUCCEEDED; " \ | |
| 439 | "fi; " \ | |
| 440 | "else; " \ | |
| 441 | "echo DOWNLOAD FAILED; " \ | |
| 442 | "fi;" | |
| 443 | ||
| 444 | #define CONFIG_PROG_UBOOT2 \ | |
| 445 | "$download_cmd $loadaddr $ubootfile; " \ | |
| 446 | "if test $? -eq 0; then " \ | |
| 447 | "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ | |
| 448 | "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ | |
| 449 | "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ | |
| 450 | "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ | |
| 451 | "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ | |
| 452 | "if test $? -ne 0; then " \ | |
| 453 | "echo PROGRAM FAILED; " \ | |
| 454 | "else; " \ | |
| 455 | "echo PROGRAM SUCCEEDED; " \ | |
| 456 | "fi; " \ | |
| 457 | "else; " \ | |
| 458 | "echo DOWNLOAD FAILED; " \ | |
| 459 | "fi;" | |
| 460 | ||
| 461 | #define CONFIG_BOOT_OS_NET \ | |
| 462 | "$download_cmd $osaddr $osfile; " \ | |
| 463 | "if test $? -eq 0; then " \ | |
| 464 | "if test -n $fdtaddr; then " \ | |
| 465 | "$download_cmd $fdtaddr $fdtfile; " \ | |
| 466 | "if test $? -eq 0; then " \ | |
| 467 | "bootm $osaddr - $fdtaddr; " \ | |
| 468 | "else; " \ | |
| 469 | "echo FDT DOWNLOAD FAILED; " \ | |
| 470 | "fi; " \ | |
| 471 | "else; " \ | |
| 472 | "bootm $osaddr; " \ | |
| 473 | "fi; " \ | |
| 474 | "else; " \ | |
| 475 | "echo OS DOWNLOAD FAILED; " \ | |
| 476 | "fi;" | |
| 477 | ||
| 478 | #define CONFIG_PROG_OS1 \ | |
| 479 | "$download_cmd $osaddr $osfile; " \ | |
| 480 | "if test $? -eq 0; then " \ | |
| 481 | "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ | |
| 482 | "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ | |
| 483 | "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ | |
| 484 | "if test $? -ne 0; then " \ | |
| 485 | "echo OS PROGRAM FAILED; " \ | |
| 486 | "else; " \ | |
| 487 | "echo OS PROGRAM SUCCEEDED; " \ | |
| 488 | "fi; " \ | |
| 489 | "else; " \ | |
| 490 | "echo OS DOWNLOAD FAILED; " \ | |
| 491 | "fi;" | |
| 492 | ||
| 493 | #define CONFIG_PROG_OS2 \ | |
| 494 | "$download_cmd $osaddr $osfile; " \ | |
| 495 | "if test $? -eq 0; then " \ | |
| 496 | "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ | |
| 497 | "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ | |
| 498 | "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ | |
| 499 | "if test $? -ne 0; then " \ | |
| 500 | "echo OS PROGRAM FAILED; " \ | |
| 501 | "else; " \ | |
| 502 | "echo OS PROGRAM SUCCEEDED; " \ | |
| 503 | "fi; " \ | |
| 504 | "else; " \ | |
| 505 | "echo OS DOWNLOAD FAILED; " \ | |
| 506 | "fi;" | |
| 507 | ||
| 508 | #define CONFIG_PROG_FDT1 \ | |
| 509 | "$download_cmd $fdtaddr $fdtfile; " \ | |
| 510 | "if test $? -eq 0; then " \ | |
| 511 | "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ | |
| 512 | "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ | |
| 513 | "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ | |
| 514 | "if test $? -ne 0; then " \ | |
| 515 | "echo FDT PROGRAM FAILED; " \ | |
| 516 | "else; " \ | |
| 517 | "echo FDT PROGRAM SUCCEEDED; " \ | |
| 518 | "fi; " \ | |
| 519 | "else; " \ | |
| 520 | "echo FDT DOWNLOAD FAILED; " \ | |
| 521 | "fi;" | |
| 522 | ||
| 523 | #define CONFIG_PROG_FDT2 \ | |
| 524 | "$download_cmd $fdtaddr $fdtfile; " \ | |
| 525 | "if test $? -eq 0; then " \ | |
| 526 | "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ | |
| 527 | "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ | |
| 528 | "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ | |
| 529 | "if test $? -ne 0; then " \ | |
| 530 | "echo FDT PROGRAM FAILED; " \ | |
| 531 | "else; " \ | |
| 532 | "echo FDT PROGRAM SUCCEEDED; " \ | |
| 533 | "fi; " \ | |
| 534 | "else; " \ | |
| 535 | "echo FDT DOWNLOAD FAILED; " \ | |
| 536 | "fi;" | |
| 537 | ||
| 538 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 539 | "autoload=yes\0" \ | |
| 540 | "download_cmd=tftp\0" \ | |
| 541 | "console_args=console=ttyS0,115200\0" \ | |
| 542 | "root_args=root=/dev/nfs rw\0" \ | |
| 543 | "misc_args=ip=on\0" \ | |
| 544 | "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ | |
| 545 | "bootfile=/home/user/file\0" \ | |
| c00ac259 PT |
546 | "osfile=/home/user/board.uImage\0" \ |
| 547 | "fdtfile=/home/user/board.dtb\0" \ | |
| ccf0fdd0 | 548 | "ubootfile=/home/user/u-boot.bin\0" \ |
| b24a4f62 | 549 | "fdtaddr=0x1e00000\0" \ |
| ccf0fdd0 PT |
550 | "osaddr=0x1000000\0" \ |
| 551 | "loadaddr=0x1000000\0" \ | |
| 552 | "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ | |
| 553 | "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ | |
| 554 | "prog_os1="CONFIG_PROG_OS1"\0" \ | |
| 555 | "prog_os2="CONFIG_PROG_OS2"\0" \ | |
| 556 | "prog_fdt1="CONFIG_PROG_FDT1"\0" \ | |
| 557 | "prog_fdt2="CONFIG_PROG_FDT2"\0" \ | |
| 558 | "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ | |
| 559 | "bootcmd_flash1=run set_bootargs; " \ | |
| 560 | "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ | |
| 561 | "bootcmd_flash2=run set_bootargs; " \ | |
| 562 | "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ | |
| 563 | "bootcmd=run bootcmd_flash1\0" | |
| 564 | #endif /* __CONFIG_H */ |