[people/ms/u-boot.git] / include / dt-bindings / clock / rk3399-cru.h

/*
 * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
#define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H

/* core clocks */
#define PLL_APLLL			1
#define PLL_APLLB			2
#define PLL_DPLL			3
#define PLL_CPLL			4
#define PLL_GPLL			5
#define PLL_NPLL			6
#define PLL_VPLL			7
#define ARMCLKL				8
#define ARMCLKB				9

/* sclk gates (special clocks) */
#define SCLK_I2C1			65
#define SCLK_I2C2			66
#define SCLK_I2C3			67
#define SCLK_I2C5			68
#define SCLK_I2C6			69
#define SCLK_I2C7			70
#define SCLK_SPI0			71
#define SCLK_SPI1			72
#define SCLK_SPI2			73
#define SCLK_SPI4			74
#define SCLK_SPI5			75
#define SCLK_SDMMC			76
#define SCLK_SDIO			77
#define SCLK_EMMC			78
#define SCLK_TSADC			79
#define SCLK_SARADC			80
#define SCLK_UART0			81
#define SCLK_UART1			82
#define SCLK_UART2			83
#define SCLK_UART3			84
#define SCLK_SPDIF_8CH			85
#define SCLK_I2S0_8CH			86
#define SCLK_I2S1_8CH			87
#define SCLK_I2S2_8CH			88
#define SCLK_I2S_8CH_OUT		89
#define SCLK_TIMER00			90
#define SCLK_TIMER01			91
#define SCLK_TIMER02			92
#define SCLK_TIMER03			93
#define SCLK_TIMER04			94
#define SCLK_TIMER05			95
#define SCLK_TIMER06			96
#define SCLK_TIMER07			97
#define SCLK_TIMER08			98
#define SCLK_TIMER09			99
#define SCLK_TIMER10			100
#define SCLK_TIMER11			101
#define SCLK_MACREF			102
#define SCLK_MAC_RX			103
#define SCLK_MAC_TX			104
#define SCLK_MAC			105
#define SCLK_MACREF_OUT			106
#define SCLK_VOP0_PWM			107
#define SCLK_VOP1_PWM			108
#define SCLK_RGA_CORE			109
#define SCLK_ISP0			110
#define SCLK_ISP1			111
#define SCLK_HDMI_CEC			112
#define SCLK_HDMI_SFR			113
#define SCLK_DP_CORE			114
#define SCLK_PVTM_CORE_L		115
#define SCLK_PVTM_CORE_B		116
#define SCLK_PVTM_GPU			117
#define SCLK_PVTM_DDR			118
#define SCLK_MIPIDPHY_REF		119
#define SCLK_MIPIDPHY_CFG		120
#define SCLK_HSICPHY			121
#define SCLK_USBPHY480M			122
#define SCLK_USB2PHY0_REF		123
#define SCLK_USB2PHY1_REF		124
#define SCLK_UPHY0_TCPDPHY_REF		125
#define SCLK_UPHY0_TCPDCORE		126
#define SCLK_UPHY1_TCPDPHY_REF		127
#define SCLK_UPHY1_TCPDCORE		128
#define SCLK_USB3OTG0_REF		129
#define SCLK_USB3OTG1_REF		130
#define SCLK_USB3OTG0_SUSPEND		131
#define SCLK_USB3OTG1_SUSPEND		132
#define SCLK_CRYPTO0			133
#define SCLK_CRYPTO1			134
#define SCLK_CCI_TRACE			135
#define SCLK_CS				136
#define SCLK_CIF_OUT			137
#define SCLK_PCIEPHY_REF		138
#define SCLK_PCIE_CORE			139
#define SCLK_M0_PERILP			140
#define SCLK_M0_PERILP_DEC		141
#define SCLK_CM0S			142
#define SCLK_DBG_NOC			143
#define SCLK_DBG_PD_CORE_B		144
#define SCLK_DBG_PD_CORE_L		145
#define SCLK_DFIMON0_TIMER		146
#define SCLK_DFIMON1_TIMER		147
#define SCLK_INTMEM0			148
#define SCLK_INTMEM1			149
#define SCLK_INTMEM2			150
#define SCLK_INTMEM3			151
#define SCLK_INTMEM4			152
#define SCLK_INTMEM5			153
#define SCLK_SDMMC_DRV			154
#define SCLK_SDMMC_SAMPLE		155
#define SCLK_SDIO_DRV			156
#define SCLK_SDIO_SAMPLE		157
#define SCLK_VDU_CORE			158
#define SCLK_VDU_CA			159
#define SCLK_PCIE_PM			160
#define SCLK_SPDIF_REC_DPTX		161
#define SCLK_DPHY_PLL			162
#define SCLK_DPHY_TX0_CFG		163
#define SCLK_DPHY_TX1RX1_CFG		164
#define SCLK_DPHY_RX0_CFG		165
#define SCLK_RMII_SRC			166
#define SCLK_PCIEPHY_REF100M		167
#define SCLK_USBPHY0_480M_SRC		168
#define SCLK_USBPHY1_480M_SRC		169
#define SCLK_DDRCLK			170
#define SCLK_TESTOUT2			171

#define DCLK_VOP0			180
#define DCLK_VOP1			181
#define DCLK_VOP0_DIV			182
#define DCLK_VOP1_DIV			183
#define DCLK_M0_PERILP			184

#define FCLK_CM0S			190

/* aclk gates */
#define ACLK_PERIHP			192
#define ACLK_PERIHP_NOC			193
#define ACLK_PERILP0			194
#define ACLK_PERILP0_NOC		195
#define ACLK_PERF_PCIE			196
#define ACLK_PCIE			197
#define ACLK_INTMEM			198
#define ACLK_TZMA			199
#define ACLK_DCF			200
#define ACLK_CCI			201
#define ACLK_CCI_NOC0			202
#define ACLK_CCI_NOC1			203
#define ACLK_CCI_GRF			204
#define ACLK_CENTER			205
#define ACLK_CENTER_MAIN_NOC		206
#define ACLK_CENTER_PERI_NOC		207
#define ACLK_GPU			208
#define ACLK_PERF_GPU			209
#define ACLK_GPU_GRF			210
#define ACLK_DMAC0_PERILP		211
#define ACLK_DMAC1_PERILP		212
#define ACLK_GMAC			213
#define ACLK_GMAC_NOC			214
#define ACLK_PERF_GMAC			215
#define ACLK_VOP0_NOC			216
#define ACLK_VOP0			217
#define ACLK_VOP1_NOC			218
#define ACLK_VOP1			219
#define ACLK_RGA			220
#define ACLK_RGA_NOC			221
#define ACLK_HDCP			222
#define ACLK_HDCP_NOC			223
#define ACLK_HDCP22			224
#define ACLK_IEP			225
#define ACLK_IEP_NOC			226
#define ACLK_VIO			227
#define ACLK_VIO_NOC			228
#define ACLK_ISP0			229
#define ACLK_ISP1			230
#define ACLK_ISP0_NOC			231
#define ACLK_ISP1_NOC			232
#define ACLK_ISP0_WRAPPER		233
#define ACLK_ISP1_WRAPPER		234
#define ACLK_VCODEC			235
#define ACLK_VCODEC_NOC			236
#define ACLK_VDU			237
#define ACLK_VDU_NOC			238
#define ACLK_PERI			239
#define ACLK_EMMC			240
#define ACLK_EMMC_CORE			241
#define ACLK_EMMC_NOC			242
#define ACLK_EMMC_GRF			243
#define ACLK_USB3			244
#define ACLK_USB3_NOC			245
#define ACLK_USB3OTG0			246
#define ACLK_USB3OTG1			247
#define ACLK_USB3_RKSOC_AXI_PERF	248
#define ACLK_USB3_GRF			249
#define ACLK_GIC			250
#define ACLK_GIC_NOC			251
#define ACLK_GIC_ADB400_CORE_L_2_GIC	252
#define ACLK_GIC_ADB400_CORE_B_2_GIC	253
#define ACLK_GIC_ADB400_GIC_2_CORE_L	254
#define ACLK_GIC_ADB400_GIC_2_CORE_B	255
#define ACLK_CORE_ADB400_CORE_L_2_CCI500 256
#define ACLK_CORE_ADB400_CORE_B_2_CCI500 257
#define ACLK_ADB400M_PD_CORE_L		258
#define ACLK_ADB400M_PD_CORE_B		259
#define ACLK_PERF_CORE_L		260
#define ACLK_PERF_CORE_B		261
#define ACLK_GIC_PRE			262
#define ACLK_VOP0_PRE			263
#define ACLK_VOP1_PRE			264

/* pclk gates */
#define PCLK_PERIHP			320
#define PCLK_PERIHP_NOC			321
#define PCLK_PERILP0			322
#define PCLK_PERILP1			323
#define PCLK_PERILP1_NOC		324
#define PCLK_PERILP_SGRF		325
#define PCLK_PERIHP_GRF			326
#define PCLK_PCIE			327
#define PCLK_SGRF			328
#define PCLK_INTR_ARB			329
#define PCLK_CENTER_MAIN_NOC		330
#define PCLK_CIC			331
#define PCLK_COREDBG_B			332
#define PCLK_COREDBG_L			333
#define PCLK_DBG_CXCS_PD_CORE_B		334
#define PCLK_DCF			335
#define PCLK_GPIO2			336
#define PCLK_GPIO3			337
#define PCLK_GPIO4			338
#define PCLK_GRF			339
#define PCLK_HSICPHY			340
#define PCLK_I2C1			341
#define PCLK_I2C2			342
#define PCLK_I2C3			343
#define PCLK_I2C5			344
#define PCLK_I2C6			345
#define PCLK_I2C7			346
#define PCLK_SPI0			347
#define PCLK_SPI1			348
#define PCLK_SPI2			349
#define PCLK_SPI4			350
#define PCLK_SPI5			351
#define PCLK_UART0			352
#define PCLK_UART1			353
#define PCLK_UART2			354
#define PCLK_UART3			355
#define PCLK_TSADC			356
#define PCLK_SARADC			357
#define PCLK_GMAC			358
#define PCLK_GMAC_NOC			359
#define PCLK_TIMER0			360
#define PCLK_TIMER1			361
#define PCLK_EDP			362
#define PCLK_EDP_NOC			363
#define PCLK_EDP_CTRL			364
#define PCLK_VIO			365
#define PCLK_VIO_NOC			366
#define PCLK_VIO_GRF			367
#define PCLK_MIPI_DSI0			368
#define PCLK_MIPI_DSI1			369
#define PCLK_HDCP			370
#define PCLK_HDCP_NOC			371
#define PCLK_HDMI_CTRL			372
#define PCLK_DP_CTRL			373
#define PCLK_HDCP22			374
#define PCLK_GASKET			375
#define PCLK_DDR			376
#define PCLK_DDR_MON			377
#define PCLK_DDR_SGRF			378
#define PCLK_ISP1_WRAPPER		379
#define PCLK_WDT			380
#define PCLK_EFUSE1024NS		381
#define PCLK_EFUSE1024S			382
#define PCLK_PMU_INTR_ARB		383
#define PCLK_MAILBOX0			384
#define PCLK_USBPHY_MUX_G		385
#define PCLK_UPHY0_TCPHY_G		386
#define PCLK_UPHY0_TCPD_G		387
#define PCLK_UPHY1_TCPHY_G		388
#define PCLK_UPHY1_TCPD_G		389
#define PCLK_ALIVE			390

/* hclk gates */
#define HCLK_PERIHP			448
#define HCLK_PERILP0			449
#define HCLK_PERILP1			450
#define HCLK_PERILP0_NOC		451
#define HCLK_PERILP1_NOC		452
#define HCLK_M0_PERILP			453
#define HCLK_M0_PERILP_NOC		454
#define HCLK_AHB1TOM			455
#define HCLK_HOST0			456
#define HCLK_HOST0_ARB			457
#define HCLK_HOST1			458
#define HCLK_HOST1_ARB			459
#define HCLK_HSIC			460
#define HCLK_SD				461
#define HCLK_SDMMC			462
#define HCLK_SDMMC_NOC			463
#define HCLK_M_CRYPTO0			464
#define HCLK_M_CRYPTO1			465
#define HCLK_S_CRYPTO0			466
#define HCLK_S_CRYPTO1			467
#define HCLK_I2S0_8CH			468
#define HCLK_I2S1_8CH			469
#define HCLK_I2S2_8CH			470
#define HCLK_SPDIF			471
#define HCLK_VOP0_NOC			472
#define HCLK_VOP0			473
#define HCLK_VOP1_NOC			474
#define HCLK_VOP1			475
#define HCLK_ROM			476
#define HCLK_IEP			477
#define HCLK_IEP_NOC			478
#define HCLK_ISP0			479
#define HCLK_ISP1			480
#define HCLK_ISP0_NOC			481
#define HCLK_ISP1_NOC			482
#define HCLK_ISP0_WRAPPER		483
#define HCLK_ISP1_WRAPPER		484
#define HCLK_RGA			485
#define HCLK_RGA_NOC			486
#define HCLK_HDCP			487
#define HCLK_HDCP_NOC			488
#define HCLK_HDCP22			489
#define HCLK_VCODEC			490
#define HCLK_VCODEC_NOC			491
#define HCLK_VDU			492
#define HCLK_VDU_NOC			493
#define HCLK_SDIO			494
#define HCLK_SDIO_NOC			495
#define HCLK_SDIOAUDIO_NOC		496

#define CLK_NR_CLKS			(HCLK_SDIOAUDIO_NOC + 1)

/* pmu-clocks indices */

#define PLL_PPLL			1

#define SCLK_32K_SUSPEND_PMU		2
#define SCLK_SPI3_PMU			3
#define SCLK_TIMER12_PMU		4
#define SCLK_TIMER13_PMU		5
#define SCLK_UART4_PMU			6
#define SCLK_PVTM_PMU			7
#define SCLK_WIFI_PMU			8
#define SCLK_I2C0_PMU			9
#define SCLK_I2C4_PMU			10
#define SCLK_I2C8_PMU			11

#define PCLK_SRC_PMU			19
#define PCLK_PMU			20
#define PCLK_PMUGRF_PMU			21
#define PCLK_INTMEM1_PMU		22
#define PCLK_GPIO0_PMU			23
#define PCLK_GPIO1_PMU			24
#define PCLK_SGRF_PMU			25
#define PCLK_NOC_PMU			26
#define PCLK_I2C0_PMU			27
#define PCLK_I2C4_PMU			28
#define PCLK_I2C8_PMU			29
#define PCLK_RKPWM_PMU			30
#define PCLK_SPI3_PMU			31
#define PCLK_TIMER_PMU			32
#define PCLK_MAILBOX_PMU		33
#define PCLK_UART4_PMU			34
#define PCLK_WDT_M0_PMU			35

#define FCLK_CM0S_SRC_PMU		44
#define FCLK_CM0S_PMU			45
#define SCLK_CM0S_PMU			46
#define HCLK_CM0S_PMU			47
#define DCLK_CM0S_PMU			48
#define PCLK_INTR_ARB_PMU		49
#define HCLK_NOC_PMU			50

#define CLKPMU_NR_CLKS			(HCLK_NOC_PMU + 1)

/* soft-reset indices */

/* cru_softrst_con0 */
#define SRST_CORE_L0			0
#define SRST_CORE_B0			1
#define SRST_CORE_PO_L0			2
#define SRST_CORE_PO_B0			3
#define SRST_L2_L			4
#define SRST_L2_B			5
#define SRST_ADB_L			6
#define SRST_ADB_B			7
#define SRST_A_CCI			8
#define SRST_A_CCIM0_NOC		9
#define SRST_A_CCIM1_NOC		10
#define SRST_DBG_NOC			11

/* cru_softrst_con1 */
#define SRST_CORE_L0_T			16
#define SRST_CORE_L1			17
#define SRST_CORE_L2			18
#define SRST_CORE_L3			19
#define SRST_CORE_PO_L0_T		20
#define SRST_CORE_PO_L1			21
#define SRST_CORE_PO_L2			22
#define SRST_CORE_PO_L3			23
#define SRST_A_ADB400_GIC2COREL		24
#define SRST_A_ADB400_COREL2GIC		25
#define SRST_P_DBG_L			26
#define SRST_L2_L_T			28
#define SRST_ADB_L_T			29
#define SRST_A_RKPERF_L			30
#define SRST_PVTM_CORE_L		31

/* cru_softrst_con2 */
#define SRST_CORE_B0_T			32
#define SRST_CORE_B1			33
#define SRST_CORE_PO_B0_T		36
#define SRST_CORE_PO_B1			37
#define SRST_A_ADB400_GIC2COREB		40
#define SRST_A_ADB400_COREB2GIC		41
#define SRST_P_DBG_B			42
#define SRST_L2_B_T			43
#define SRST_ADB_B_T			45
#define SRST_A_RKPERF_B			46
#define SRST_PVTM_CORE_B		47

/* cru_softrst_con3 */
#define SRST_A_CCI_T			50
#define SRST_A_CCIM0_NOC_T		51
#define SRST_A_CCIM1_NOC_T		52
#define SRST_A_ADB400M_PD_CORE_B_T	53
#define SRST_A_ADB400M_PD_CORE_L_T	54
#define SRST_DBG_NOC_T			55
#define SRST_DBG_CXCS			56
#define SRST_CCI_TRACE			57
#define SRST_P_CCI_GRF			58

/* cru_softrst_con4 */
#define SRST_A_CENTER_MAIN_NOC		64
#define SRST_A_CENTER_PERI_NOC		65
#define SRST_P_CENTER_MAIN		66
#define SRST_P_DDRMON			67
#define SRST_P_CIC			68
#define SRST_P_CENTER_SGRF		69
#define SRST_DDR0_MSCH			70
#define SRST_DDRCFG0_MSCH		71
#define SRST_DDR0			72
#define SRST_DDRPHY0			73
#define SRST_DDR1_MSCH			74
#define SRST_DDRCFG1_MSCH		75
#define SRST_DDR1			76
#define SRST_DDRPHY1			77
#define SRST_DDR_CIC			78
#define SRST_PVTM_DDR			79

/* cru_softrst_con5 */
#define SRST_A_VCODEC_NOC		80
#define SRST_A_VCODEC			81
#define SRST_H_VCODEC_NOC		82
#define SRST_H_VCODEC			83
#define SRST_A_VDU_NOC			88
#define SRST_A_VDU			89
#define SRST_H_VDU_NOC			90
#define SRST_H_VDU			91
#define SRST_VDU_CORE			92
#define SRST_VDU_CA			93

/* cru_softrst_con6 */
#define SRST_A_IEP_NOC			96
#define SRST_A_VOP_IEP			97
#define SRST_A_IEP			98
#define SRST_H_IEP_NOC			99
#define SRST_H_IEP			100
#define SRST_A_RGA_NOC			102
#define SRST_A_RGA			103
#define SRST_H_RGA_NOC			104
#define SRST_H_RGA			105
#define SRST_RGA_CORE			106
#define SRST_EMMC_NOC			108
#define SRST_EMMC			109
#define SRST_EMMC_GRF			110

/* cru_softrst_con7 */
#define SRST_A_PERIHP_NOC		112
#define SRST_P_PERIHP_GRF		113
#define SRST_H_PERIHP_NOC		114
#define SRST_USBHOST0			115
#define SRST_HOSTC0_AUX			116
#define SRST_HOST0_ARB			117
#define SRST_USBHOST1			118
#define SRST_HOSTC1_AUX			119
#define SRST_HOST1_ARB			120
#define SRST_SDIO0			121
#define SRST_SDMMC			122
#define SRST_HSIC			123
#define SRST_HSIC_AUX			124
#define SRST_AHB1TOM			125
#define SRST_P_PERIHP_NOC		126
#define SRST_HSICPHY			127

/* cru_softrst_con8 */
#define SRST_A_PCIE			128
#define SRST_P_PCIE			129
#define SRST_PCIE_CORE			130
#define SRST_PCIE_MGMT			131
#define SRST_PCIE_MGMT_STICKY		132
#define SRST_PCIE_PIPE			133
#define SRST_PCIE_PM			134
#define SRST_PCIEPHY			135
#define SRST_A_GMAC_NOC			136
#define SRST_A_GMAC			137
#define SRST_P_GMAC_NOC			138
#define SRST_P_GMAC_GRF			140
#define SRST_HSICPHY_POR		142
#define SRST_HSICPHY_UTMI		143

/* cru_softrst_con9 */
#define SRST_USB2PHY0_POR		144
#define SRST_USB2PHY0_UTMI_PORT0	145
#define SRST_USB2PHY0_UTMI_PORT1	146
#define SRST_USB2PHY0_EHCIPHY		147
#define SRST_UPHY0_PIPE_L00		148
#define SRST_UPHY0			149
#define SRST_UPHY0_TCPDPWRUP		150
#define SRST_USB2PHY1_POR		152
#define SRST_USB2PHY1_UTMI_PORT0	153
#define SRST_USB2PHY1_UTMI_PORT1	154
#define SRST_USB2PHY1_EHCIPHY		155
#define SRST_UPHY1_PIPE_L00		156
#define SRST_UPHY1			157
#define SRST_UPHY1_TCPDPWRUP		158

/* cru_softrst_con10 */
#define SRST_A_PERILP0_NOC		160
#define SRST_A_DCF			161
#define SRST_GIC500			162
#define SRST_DMAC0_PERILP0		163
#define SRST_DMAC1_PERILP0		164
#define SRST_TZMA			165
#define SRST_INTMEM			166
#define SRST_ADB400_MST0		167
#define SRST_ADB400_MST1		168
#define SRST_ADB400_SLV0		169
#define SRST_ADB400_SLV1		170
#define SRST_H_PERILP0			171
#define SRST_H_PERILP0_NOC		172
#define SRST_ROM			173
#define SRST_CRYPTO_S			174
#define SRST_CRYPTO_M			175

/* cru_softrst_con11 */
#define SRST_P_DCF			176
#define SRST_CM0S_NOC			177
#define SRST_CM0S			178
#define SRST_CM0S_DBG			179
#define SRST_CM0S_PO			180
#define SRST_CRYPTO			181
#define SRST_P_PERILP1_SGRF		182
#define SRST_P_PERILP1_GRF		183
#define SRST_CRYPTO1_S			184
#define SRST_CRYPTO1_M			185
#define SRST_CRYPTO1			186
#define SRST_GIC_NOC			188
#define SRST_SD_NOC			189
#define SRST_SDIOAUDIO_BRG		190

/* cru_softrst_con12 */
#define SRST_H_PERILP1			192
#define SRST_H_PERILP1_NOC		193
#define SRST_H_I2S0_8CH			194
#define SRST_H_I2S1_8CH			195
#define SRST_H_I2S2_8CH			196
#define SRST_H_SPDIF_8CH		197
#define SRST_P_PERILP1_NOC		198
#define SRST_P_EFUSE_1024		199
#define SRST_P_EFUSE_1024S		200
#define SRST_P_I2C0			201
#define SRST_P_I2C1			202
#define SRST_P_I2C2			203
#define SRST_P_I2C3			204
#define SRST_P_I2C4			205
#define SRST_P_I2C5			206
#define SRST_P_MAILBOX0			207

/* cru_softrst_con13 */
#define SRST_P_UART0			208
#define SRST_P_UART1			209
#define SRST_P_UART2			210
#define SRST_P_UART3			211
#define SRST_P_SARADC			212
#define SRST_P_TSADC			213
#define SRST_P_SPI0			214
#define SRST_P_SPI1			215
#define SRST_P_SPI2			216
#define SRST_P_SPI4			217
#define SRST_P_SPI5			218
#define SRST_SPI0			219
#define SRST_SPI1			220
#define SRST_SPI2			221
#define SRST_SPI4			222
#define SRST_SPI5			223

/* cru_softrst_con14 */
#define SRST_I2S0_8CH			224
#define SRST_I2S1_8CH			225
#define SRST_I2S2_8CH			226
#define SRST_SPDIF_8CH			227
#define SRST_UART0			228
#define SRST_UART1			229
#define SRST_UART2			230
#define SRST_UART3			231
#define SRST_TSADC			232
#define SRST_I2C0			233
#define SRST_I2C1			234
#define SRST_I2C2			235
#define SRST_I2C3			236
#define SRST_I2C4			237
#define SRST_I2C5			238
#define SRST_SDIOAUDIO_NOC		239

/* cru_softrst_con15 */
#define SRST_A_VIO_NOC			240
#define SRST_A_HDCP_NOC			241
#define SRST_A_HDCP			242
#define SRST_H_HDCP_NOC			243
#define SRST_H_HDCP			244
#define SRST_P_HDCP_NOC			245
#define SRST_P_HDCP			246
#define SRST_P_HDMI_CTRL		247
#define SRST_P_DP_CTRL			248
#define SRST_S_DP_CTRL			249
#define SRST_C_DP_CTRL			250
#define SRST_P_MIPI_DSI0		251
#define SRST_P_MIPI_DSI1		252
#define SRST_DP_CORE			253
#define SRST_DP_I2S			254

/* cru_softrst_con16 */
#define SRST_GASKET			256
#define SRST_VIO_GRF			258
#define SRST_DPTX_SPDIF_REC		259
#define SRST_HDMI_CTRL			260
#define SRST_HDCP_CTRL			261
#define SRST_A_ISP0_NOC			262
#define SRST_A_ISP1_NOC			263
#define SRST_H_ISP0_NOC			266
#define SRST_H_ISP1_NOC			267
#define SRST_H_ISP0			268
#define SRST_H_ISP1			269
#define SRST_ISP0			270
#define SRST_ISP1			271

/* cru_softrst_con17 */
#define SRST_A_VOP0_NOC			272
#define SRST_A_VOP1_NOC			273
#define SRST_A_VOP0			274
#define SRST_A_VOP1			275
#define SRST_H_VOP0_NOC			276
#define SRST_H_VOP1_NOC			277
#define SRST_H_VOP0			278
#define SRST_H_VOP1			279
#define SRST_D_VOP0			280
#define SRST_D_VOP1			281
#define SRST_VOP0_PWM			282
#define SRST_VOP1_PWM			283
#define SRST_P_EDP_NOC			284
#define SRST_P_EDP_CTRL			285

/* cru_softrst_con18 */
#define SRST_A_GPU			288
#define SRST_A_GPU_NOC			289
#define SRST_A_GPU_GRF			290
#define SRST_PVTM_GPU			291
#define SRST_A_USB3_NOC			292
#define SRST_A_USB3_OTG0		293
#define SRST_A_USB3_OTG1		294
#define SRST_A_USB3_GRF			295
#define SRST_PMU			296

/* cru_softrst_con19 */
#define SRST_P_TIMER0_5			304
#define SRST_TIMER0			305
#define SRST_TIMER1			306
#define SRST_TIMER2			307
#define SRST_TIMER3			308
#define SRST_TIMER4			309
#define SRST_TIMER5			310
#define SRST_P_TIMER6_11		311
#define SRST_TIMER6			312
#define SRST_TIMER7			313
#define SRST_TIMER8			314
#define SRST_TIMER9			315
#define SRST_TIMER10			316
#define SRST_TIMER11			317
#define SRST_P_INTR_ARB_PMU		318
#define SRST_P_ALIVE_SGRF		319

/* cru_softrst_con20 */
#define SRST_P_GPIO2			320
#define SRST_P_GPIO3			321
#define SRST_P_GPIO4			322
#define SRST_P_GRF			323
#define SRST_P_ALIVE_NOC		324
#define SRST_P_WDT0			325
#define SRST_P_WDT1			326
#define SRST_P_INTR_ARB			327
#define SRST_P_UPHY0_DPTX		328
#define SRST_P_UPHY0_APB		330
#define SRST_P_UPHY0_TCPHY		332
#define SRST_P_UPHY1_TCPHY		333
#define SRST_P_UPHY0_TCPDCTRL		334
#define SRST_P_UPHY1_TCPDCTRL		335

/* pmu soft-reset indices */

/* pmu_cru_softrst_con0 */
#define SRST_P_NOC			0
#define SRST_P_INTMEM			1
#define SRST_H_CM0S			2
#define SRST_H_CM0S_NOC			3
#define SRST_DBG_CM0S			4
#define SRST_PO_CM0S			5
#define SRST_P_SPI3			6
#define SRST_SPI3			7
#define SRST_P_TIMER_0_1		8
#define SRST_P_TIMER_0			9
#define SRST_P_TIMER_1			10
#define SRST_P_UART4			11
#define SRST_UART4			12
#define SRST_P_WDT			13

/* pmu_cru_softrst_con1 */
#define SRST_P_I2C6			16
#define SRST_P_I2C7			17
#define SRST_P_I2C8			18
#define SRST_P_MAILBOX			19
#define SRST_P_RKPWM			20
#define SRST_P_PMUGRF			21
#define SRST_P_SGRF			22
#define SRST_P_GPIO0			23
#define SRST_P_GPIO1			24
#define SRST_P_CRU			25
#define SRST_P_INTR			26
#define SRST_PVTM			27
#define SRST_I2C6			28
#define SRST_I2C7			29
#define SRST_I2C8			30

#endif
Commit	Line	Data
777c834f KY	1	/*
	2	* Copyright (c) 2016 Rockchip Electronics Co. Ltd.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
	8	#define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
	9
	10	/* core clocks */
	11	#define PLL_APLLL 1
	12	#define PLL_APLLB 2
	13	#define PLL_DPLL 3
	14	#define PLL_CPLL 4
	15	#define PLL_GPLL 5
	16	#define PLL_NPLL 6
	17	#define PLL_VPLL 7
	18	#define ARMCLKL 8
	19	#define ARMCLKB 9
	20
	21	/* sclk gates (special clocks) */
	22	#define SCLK_I2C1 65
	23	#define SCLK_I2C2 66
	24	#define SCLK_I2C3 67
	25	#define SCLK_I2C5 68
	26	#define SCLK_I2C6 69
	27	#define SCLK_I2C7 70
	28	#define SCLK_SPI0 71
	29	#define SCLK_SPI1 72
	30	#define SCLK_SPI2 73
	31	#define SCLK_SPI4 74
	32	#define SCLK_SPI5 75
	33	#define SCLK_SDMMC 76
	34	#define SCLK_SDIO 77
	35	#define SCLK_EMMC 78
	36	#define SCLK_TSADC 79
	37	#define SCLK_SARADC 80
	38	#define SCLK_UART0 81
	39	#define SCLK_UART1 82
	40	#define SCLK_UART2 83
	41	#define SCLK_UART3 84
	42	#define SCLK_SPDIF_8CH 85
	43	#define SCLK_I2S0_8CH 86
	44	#define SCLK_I2S1_8CH 87
	45	#define SCLK_I2S2_8CH 88
	46	#define SCLK_I2S_8CH_OUT 89
	47	#define SCLK_TIMER00 90
	48	#define SCLK_TIMER01 91
	49	#define SCLK_TIMER02 92
	50	#define SCLK_TIMER03 93
	51	#define SCLK_TIMER04 94
	52	#define SCLK_TIMER05 95
	53	#define SCLK_TIMER06 96
	54	#define SCLK_TIMER07 97
	55	#define SCLK_TIMER08 98
	56	#define SCLK_TIMER09 99
	57	#define SCLK_TIMER10 100
	58	#define SCLK_TIMER11 101
	59	#define SCLK_MACREF 102
	60	#define SCLK_MAC_RX 103
	61	#define SCLK_MAC_TX 104
	62	#define SCLK_MAC 105
	63	#define SCLK_MACREF_OUT 106
	64	#define SCLK_VOP0_PWM 107
65	#define SCLK_VOP1_PWM 108
66	#define SCLK_RGA_CORE 109
67	#define SCLK_ISP0 110
68	#define SCLK_ISP1 111
69	#define SCLK_HDMI_CEC 112
70	#define SCLK_HDMI_SFR 113
71	#define SCLK_DP_CORE 114
72	#define SCLK_PVTM_CORE_L 115
73	#define SCLK_PVTM_CORE_B 116
74	#define SCLK_PVTM_GPU 117
75	#define SCLK_PVTM_DDR 118
76	#define SCLK_MIPIDPHY_REF 119
77	#define SCLK_MIPIDPHY_CFG 120
78	#define SCLK_HSICPHY 121
79	#define SCLK_USBPHY480M 122
80	#define SCLK_USB2PHY0_REF 123
81	#define SCLK_USB2PHY1_REF 124
82	#define SCLK_UPHY0_TCPDPHY_REF 125
83	#define SCLK_UPHY0_TCPDCORE 126
84	#define SCLK_UPHY1_TCPDPHY_REF 127
85	#define SCLK_UPHY1_TCPDCORE 128
86	#define SCLK_USB3OTG0_REF 129
87	#define SCLK_USB3OTG1_REF 130
88	#define SCLK_USB3OTG0_SUSPEND 131
89	#define SCLK_USB3OTG1_SUSPEND 132
90	#define SCLK_CRYPTO0 133
91	#define SCLK_CRYPTO1 134
92	#define SCLK_CCI_TRACE 135
93	#define SCLK_CS 136
94	#define SCLK_CIF_OUT 137
95	#define SCLK_PCIEPHY_REF 138
96	#define SCLK_PCIE_CORE 139
97	#define SCLK_M0_PERILP 140
98	#define SCLK_M0_PERILP_DEC 141
99	#define SCLK_CM0S 142
100	#define SCLK_DBG_NOC 143
101	#define SCLK_DBG_PD_CORE_B 144
102	#define SCLK_DBG_PD_CORE_L 145
103	#define SCLK_DFIMON0_TIMER 146
104	#define SCLK_DFIMON1_TIMER 147
105	#define SCLK_INTMEM0 148
106	#define SCLK_INTMEM1 149
107	#define SCLK_INTMEM2 150
108	#define SCLK_INTMEM3 151
109	#define SCLK_INTMEM4 152
110	#define SCLK_INTMEM5 153
111	#define SCLK_SDMMC_DRV 154
112	#define SCLK_SDMMC_SAMPLE 155
113	#define SCLK_SDIO_DRV 156
114	#define SCLK_SDIO_SAMPLE 157
115	#define SCLK_VDU_CORE 158
116	#define SCLK_VDU_CA 159
117	#define SCLK_PCIE_PM 160
118	#define SCLK_SPDIF_REC_DPTX 161
119	#define SCLK_DPHY_PLL 162
120	#define SCLK_DPHY_TX0_CFG 163
121	#define SCLK_DPHY_TX1RX1_CFG 164
122	#define SCLK_DPHY_RX0_CFG 165
123	#define SCLK_RMII_SRC 166
124	#define SCLK_PCIEPHY_REF100M 167
5ae2fd97 KY	125	#define SCLK_USBPHY0_480M_SRC 168
	126	#define SCLK_USBPHY1_480M_SRC 169
	127	#define SCLK_DDRCLK 170
	128	#define SCLK_TESTOUT2 171
777c834f KY	129
	130	#define DCLK_VOP0 180
	131	#define DCLK_VOP1 181
	132	#define DCLK_VOP0_DIV 182
	133	#define DCLK_VOP1_DIV 183
	134	#define DCLK_M0_PERILP 184
	135
	136	#define FCLK_CM0S 190
	137
	138	/* aclk gates */
	139	#define ACLK_PERIHP 192
	140	#define ACLK_PERIHP_NOC 193
	141	#define ACLK_PERILP0 194
	142	#define ACLK_PERILP0_NOC 195
	143	#define ACLK_PERF_PCIE 196
	144	#define ACLK_PCIE 197
	145	#define ACLK_INTMEM 198
	146	#define ACLK_TZMA 199
	147	#define ACLK_DCF 200
	148	#define ACLK_CCI 201
	149	#define ACLK_CCI_NOC0 202
	150	#define ACLK_CCI_NOC1 203
	151	#define ACLK_CCI_GRF 204
	152	#define ACLK_CENTER 205
	153	#define ACLK_CENTER_MAIN_NOC 206
	154	#define ACLK_CENTER_PERI_NOC 207
	155	#define ACLK_GPU 208
	156	#define ACLK_PERF_GPU 209
	157	#define ACLK_GPU_GRF 210
	158	#define ACLK_DMAC0_PERILP 211
	159	#define ACLK_DMAC1_PERILP 212
	160	#define ACLK_GMAC 213
	161	#define ACLK_GMAC_NOC 214
	162	#define ACLK_PERF_GMAC 215
	163	#define ACLK_VOP0_NOC 216
	164	#define ACLK_VOP0 217
	165	#define ACLK_VOP1_NOC 218
	166	#define ACLK_VOP1 219
	167	#define ACLK_RGA 220
	168	#define ACLK_RGA_NOC 221
	169	#define ACLK_HDCP 222
	170	#define ACLK_HDCP_NOC 223
	171	#define ACLK_HDCP22 224
	172	#define ACLK_IEP 225
	173	#define ACLK_IEP_NOC 226
	174	#define ACLK_VIO 227
	175	#define ACLK_VIO_NOC 228
	176	#define ACLK_ISP0 229
	177	#define ACLK_ISP1 230
	178	#define ACLK_ISP0_NOC 231
	179	#define ACLK_ISP1_NOC 232
	180	#define ACLK_ISP0_WRAPPER 233
	181	#define ACLK_ISP1_WRAPPER 234
	182	#define ACLK_VCODEC 235
	183	#define ACLK_VCODEC_NOC 236
	184	#define ACLK_VDU 237
	185	#define ACLK_VDU_NOC 238
	186	#define ACLK_PERI 239
	187	#define ACLK_EMMC 240
	188	#define ACLK_EMMC_CORE 241
	189	#define ACLK_EMMC_NOC 242
	190	#define ACLK_EMMC_GRF 243
	191	#define ACLK_USB3 244
	192	#define ACLK_USB3_NOC 245
193	#define ACLK_USB3OTG0 246
194	#define ACLK_USB3OTG1 247
195	#define ACLK_USB3_RKSOC_AXI_PERF 248
196	#define ACLK_USB3_GRF 249
197	#define ACLK_GIC 250
198	#define ACLK_GIC_NOC 251
199	#define ACLK_GIC_ADB400_CORE_L_2_GIC 252
200	#define ACLK_GIC_ADB400_CORE_B_2_GIC 253
201	#define ACLK_GIC_ADB400_GIC_2_CORE_L 254
202	#define ACLK_GIC_ADB400_GIC_2_CORE_B 255
203	#define ACLK_CORE_ADB400_CORE_L_2_CCI500 256
204	#define ACLK_CORE_ADB400_CORE_B_2_CCI500 257
205	#define ACLK_ADB400M_PD_CORE_L 258
206	#define ACLK_ADB400M_PD_CORE_B 259
207	#define ACLK_PERF_CORE_L 260
208	#define ACLK_PERF_CORE_B 261
209	#define ACLK_GIC_PRE 262
210	#define ACLK_VOP0_PRE 263
211	#define ACLK_VOP1_PRE 264
212
213	/* pclk gates */
214	#define PCLK_PERIHP 320
215	#define PCLK_PERIHP_NOC 321
216	#define PCLK_PERILP0 322
217	#define PCLK_PERILP1 323
218	#define PCLK_PERILP1_NOC 324
219	#define PCLK_PERILP_SGRF 325
220	#define PCLK_PERIHP_GRF 326
221	#define PCLK_PCIE 327
222	#define PCLK_SGRF 328
223	#define PCLK_INTR_ARB 329
224	#define PCLK_CENTER_MAIN_NOC 330
225	#define PCLK_CIC 331
226	#define PCLK_COREDBG_B 332
227	#define PCLK_COREDBG_L 333
228	#define PCLK_DBG_CXCS_PD_CORE_B 334
229	#define PCLK_DCF 335
230	#define PCLK_GPIO2 336
231	#define PCLK_GPIO3 337
232	#define PCLK_GPIO4 338
233	#define PCLK_GRF 339
234	#define PCLK_HSICPHY 340
235	#define PCLK_I2C1 341
236	#define PCLK_I2C2 342
237	#define PCLK_I2C3 343
238	#define PCLK_I2C5 344
239	#define PCLK_I2C6 345
240	#define PCLK_I2C7 346
241	#define PCLK_SPI0 347
242	#define PCLK_SPI1 348
243	#define PCLK_SPI2 349
244	#define PCLK_SPI4 350
245	#define PCLK_SPI5 351
246	#define PCLK_UART0 352
247	#define PCLK_UART1 353
248	#define PCLK_UART2 354
249	#define PCLK_UART3 355
250	#define PCLK_TSADC 356
251	#define PCLK_SARADC 357
252	#define PCLK_GMAC 358
253	#define PCLK_GMAC_NOC 359
254	#define PCLK_TIMER0 360
255	#define PCLK_TIMER1 361
256	#define PCLK_EDP 362
257	#define PCLK_EDP_NOC 363
258	#define PCLK_EDP_CTRL 364
259	#define PCLK_VIO 365
260	#define PCLK_VIO_NOC 366
261	#define PCLK_VIO_GRF 367
262	#define PCLK_MIPI_DSI0 368
263	#define PCLK_MIPI_DSI1 369
264	#define PCLK_HDCP 370
265	#define PCLK_HDCP_NOC 371
266	#define PCLK_HDMI_CTRL 372
267	#define PCLK_DP_CTRL 373
268	#define PCLK_HDCP22 374
269	#define PCLK_GASKET 375
270	#define PCLK_DDR 376
271	#define PCLK_DDR_MON 377
272	#define PCLK_DDR_SGRF 378
273	#define PCLK_ISP1_WRAPPER 379
274	#define PCLK_WDT 380
275	#define PCLK_EFUSE1024NS 381
276	#define PCLK_EFUSE1024S 382
277	#define PCLK_PMU_INTR_ARB 383
278	#define PCLK_MAILBOX0 384
279	#define PCLK_USBPHY_MUX_G 385
280	#define PCLK_UPHY0_TCPHY_G 386
281	#define PCLK_UPHY0_TCPD_G 387
282	#define PCLK_UPHY1_TCPHY_G 388
283	#define PCLK_UPHY1_TCPD_G 389
284	#define PCLK_ALIVE 390
285
286	/* hclk gates */
287	#define HCLK_PERIHP 448
288	#define HCLK_PERILP0 449
289	#define HCLK_PERILP1 450
290	#define HCLK_PERILP0_NOC 451
291	#define HCLK_PERILP1_NOC 452
292	#define HCLK_M0_PERILP 453
293	#define HCLK_M0_PERILP_NOC 454
294	#define HCLK_AHB1TOM 455
295	#define HCLK_HOST0 456
296	#define HCLK_HOST0_ARB 457
297	#define HCLK_HOST1 458
298	#define HCLK_HOST1_ARB 459
299	#define HCLK_HSIC 460
300	#define HCLK_SD 461
301	#define HCLK_SDMMC 462
302	#define HCLK_SDMMC_NOC 463
303	#define HCLK_M_CRYPTO0 464
304	#define HCLK_M_CRYPTO1 465
305	#define HCLK_S_CRYPTO0 466
306	#define HCLK_S_CRYPTO1 467
307	#define HCLK_I2S0_8CH 468
308	#define HCLK_I2S1_8CH 469
309	#define HCLK_I2S2_8CH 470
310	#define HCLK_SPDIF 471
311	#define HCLK_VOP0_NOC 472
312	#define HCLK_VOP0 473
313	#define HCLK_VOP1_NOC 474
314	#define HCLK_VOP1 475
315	#define HCLK_ROM 476
316	#define HCLK_IEP 477
317	#define HCLK_IEP_NOC 478
318	#define HCLK_ISP0 479
319	#define HCLK_ISP1 480
320	#define HCLK_ISP0_NOC 481
321	#define HCLK_ISP1_NOC 482
322	#define HCLK_ISP0_WRAPPER 483
323	#define HCLK_ISP1_WRAPPER 484
324	#define HCLK_RGA 485
325	#define HCLK_RGA_NOC 486
326	#define HCLK_HDCP 487
327	#define HCLK_HDCP_NOC 488
328	#define HCLK_HDCP22 489
329	#define HCLK_VCODEC 490
330	#define HCLK_VCODEC_NOC 491
331	#define HCLK_VDU 492
332	#define HCLK_VDU_NOC 493
333	#define HCLK_SDIO 494
334	#define HCLK_SDIO_NOC 495
335	#define HCLK_SDIOAUDIO_NOC 496
336
337	#define CLK_NR_CLKS (HCLK_SDIOAUDIO_NOC + 1)
338
339	/* pmu-clocks indices */
340
341	#define PLL_PPLL 1
342
343	#define SCLK_32K_SUSPEND_PMU 2
344	#define SCLK_SPI3_PMU 3
345	#define SCLK_TIMER12_PMU 4
346	#define SCLK_TIMER13_PMU 5
347	#define SCLK_UART4_PMU 6
348	#define SCLK_PVTM_PMU 7
349	#define SCLK_WIFI_PMU 8
350	#define SCLK_I2C0_PMU 9
351	#define SCLK_I2C4_PMU 10
352	#define SCLK_I2C8_PMU 11
353
354	#define PCLK_SRC_PMU 19
355	#define PCLK_PMU 20
356	#define PCLK_PMUGRF_PMU 21
357	#define PCLK_INTMEM1_PMU 22
358	#define PCLK_GPIO0_PMU 23
359	#define PCLK_GPIO1_PMU 24
360	#define PCLK_SGRF_PMU 25
361	#define PCLK_NOC_PMU 26
362	#define PCLK_I2C0_PMU 27
363	#define PCLK_I2C4_PMU 28
364	#define PCLK_I2C8_PMU 29
365	#define PCLK_RKPWM_PMU 30
366	#define PCLK_SPI3_PMU 31
367	#define PCLK_TIMER_PMU 32
368	#define PCLK_MAILBOX_PMU 33
369	#define PCLK_UART4_PMU 34
370	#define PCLK_WDT_M0_PMU 35
371
372	#define FCLK_CM0S_SRC_PMU 44
373	#define FCLK_CM0S_PMU 45
374	#define SCLK_CM0S_PMU 46
375	#define HCLK_CM0S_PMU 47
376	#define DCLK_CM0S_PMU 48
377	#define PCLK_INTR_ARB_PMU 49
378	#define HCLK_NOC_PMU 50
379
380	#define CLKPMU_NR_CLKS (HCLK_NOC_PMU + 1)
381
382	/* soft-reset indices */
383
384	/* cru_softrst_con0 */
385	#define SRST_CORE_L0 0
386	#define SRST_CORE_B0 1
387	#define SRST_CORE_PO_L0 2
388	#define SRST_CORE_PO_B0 3
389	#define SRST_L2_L 4
390	#define SRST_L2_B 5
391	#define SRST_ADB_L 6
392	#define SRST_ADB_B 7
393	#define SRST_A_CCI 8
394	#define SRST_A_CCIM0_NOC 9
395	#define SRST_A_CCIM1_NOC 10
396	#define SRST_DBG_NOC 11
397
398	/* cru_softrst_con1 */
399	#define SRST_CORE_L0_T 16
400	#define SRST_CORE_L1 17
401	#define SRST_CORE_L2 18
402	#define SRST_CORE_L3 19
403	#define SRST_CORE_PO_L0_T 20
404	#define SRST_CORE_PO_L1 21
405	#define SRST_CORE_PO_L2 22
406	#define SRST_CORE_PO_L3 23
407	#define SRST_A_ADB400_GIC2COREL 24
408	#define SRST_A_ADB400_COREL2GIC 25
409	#define SRST_P_DBG_L 26
410	#define SRST_L2_L_T 28
411	#define SRST_ADB_L_T 29
412	#define SRST_A_RKPERF_L 30
413	#define SRST_PVTM_CORE_L 31
414
415	/* cru_softrst_con2 */
416	#define SRST_CORE_B0_T 32
417	#define SRST_CORE_B1 33
418	#define SRST_CORE_PO_B0_T 36
419	#define SRST_CORE_PO_B1 37
420	#define SRST_A_ADB400_GIC2COREB 40
421	#define SRST_A_ADB400_COREB2GIC 41
422	#define SRST_P_DBG_B 42
423	#define SRST_L2_B_T 43
424	#define SRST_ADB_B_T 45
425	#define SRST_A_RKPERF_B 46
426	#define SRST_PVTM_CORE_B 47
427
428	/* cru_softrst_con3 */
429	#define SRST_A_CCI_T 50
430	#define SRST_A_CCIM0_NOC_T 51
431	#define SRST_A_CCIM1_NOC_T 52
432	#define SRST_A_ADB400M_PD_CORE_B_T 53
433	#define SRST_A_ADB400M_PD_CORE_L_T 54
434	#define SRST_DBG_NOC_T 55
435	#define SRST_DBG_CXCS 56
436	#define SRST_CCI_TRACE 57
437	#define SRST_P_CCI_GRF 58
438
439	/* cru_softrst_con4 */
440	#define SRST_A_CENTER_MAIN_NOC 64
441	#define SRST_A_CENTER_PERI_NOC 65
442	#define SRST_P_CENTER_MAIN 66
443	#define SRST_P_DDRMON 67
444	#define SRST_P_CIC 68
445	#define SRST_P_CENTER_SGRF 69
446	#define SRST_DDR0_MSCH 70
447	#define SRST_DDRCFG0_MSCH 71
448	#define SRST_DDR0 72
449	#define SRST_DDRPHY0 73
450	#define SRST_DDR1_MSCH 74
451	#define SRST_DDRCFG1_MSCH 75
452	#define SRST_DDR1 76
453	#define SRST_DDRPHY1 77
454	#define SRST_DDR_CIC 78
455	#define SRST_PVTM_DDR 79
456
457	/* cru_softrst_con5 */
458	#define SRST_A_VCODEC_NOC 80
459	#define SRST_A_VCODEC 81
460	#define SRST_H_VCODEC_NOC 82
461	#define SRST_H_VCODEC 83
462	#define SRST_A_VDU_NOC 88
463	#define SRST_A_VDU 89
464	#define SRST_H_VDU_NOC 90
465	#define SRST_H_VDU 91
466	#define SRST_VDU_CORE 92
467	#define SRST_VDU_CA 93
468
469	/* cru_softrst_con6 */
470	#define SRST_A_IEP_NOC 96
471	#define SRST_A_VOP_IEP 97
472	#define SRST_A_IEP 98
473	#define SRST_H_IEP_NOC 99
474	#define SRST_H_IEP 100
475	#define SRST_A_RGA_NOC 102
476	#define SRST_A_RGA 103
477	#define SRST_H_RGA_NOC 104
478	#define SRST_H_RGA 105
479	#define SRST_RGA_CORE 106
480	#define SRST_EMMC_NOC 108
481	#define SRST_EMMC 109
482	#define SRST_EMMC_GRF 110
483
484	/* cru_softrst_con7 */
485	#define SRST_A_PERIHP_NOC 112
486	#define SRST_P_PERIHP_GRF 113
487	#define SRST_H_PERIHP_NOC 114
488	#define SRST_USBHOST0 115
489	#define SRST_HOSTC0_AUX 116
490	#define SRST_HOST0_ARB 117
491	#define SRST_USBHOST1 118
492	#define SRST_HOSTC1_AUX 119
493	#define SRST_HOST1_ARB 120
494	#define SRST_SDIO0 121
495	#define SRST_SDMMC 122
496	#define SRST_HSIC 123
497	#define SRST_HSIC_AUX 124
498	#define SRST_AHB1TOM 125
499	#define SRST_P_PERIHP_NOC 126
500	#define SRST_HSICPHY 127
501
502	/* cru_softrst_con8 */
503	#define SRST_A_PCIE 128
504	#define SRST_P_PCIE 129
505	#define SRST_PCIE_CORE 130
506	#define SRST_PCIE_MGMT 131
507	#define SRST_PCIE_MGMT_STICKY 132
508	#define SRST_PCIE_PIPE 133
509	#define SRST_PCIE_PM 134
510	#define SRST_PCIEPHY 135
511	#define SRST_A_GMAC_NOC 136
512	#define SRST_A_GMAC 137
513	#define SRST_P_GMAC_NOC 138
514	#define SRST_P_GMAC_GRF 140
515	#define SRST_HSICPHY_POR 142
516	#define SRST_HSICPHY_UTMI 143
517
518	/* cru_softrst_con9 */
519	#define SRST_USB2PHY0_POR 144
520	#define SRST_USB2PHY0_UTMI_PORT0 145
521	#define SRST_USB2PHY0_UTMI_PORT1 146
522	#define SRST_USB2PHY0_EHCIPHY 147
523	#define SRST_UPHY0_PIPE_L00 148
524	#define SRST_UPHY0 149
525	#define SRST_UPHY0_TCPDPWRUP 150
526	#define SRST_USB2PHY1_POR 152
527	#define SRST_USB2PHY1_UTMI_PORT0 153
528	#define SRST_USB2PHY1_UTMI_PORT1 154
529	#define SRST_USB2PHY1_EHCIPHY 155
530	#define SRST_UPHY1_PIPE_L00 156
531	#define SRST_UPHY1 157
532	#define SRST_UPHY1_TCPDPWRUP 158
533
534	/* cru_softrst_con10 */
535	#define SRST_A_PERILP0_NOC 160
536	#define SRST_A_DCF 161
537	#define SRST_GIC500 162
538	#define SRST_DMAC0_PERILP0 163
539	#define SRST_DMAC1_PERILP0 164
540	#define SRST_TZMA 165
541	#define SRST_INTMEM 166
542	#define SRST_ADB400_MST0 167
543	#define SRST_ADB400_MST1 168
544	#define SRST_ADB400_SLV0 169
545	#define SRST_ADB400_SLV1 170
546	#define SRST_H_PERILP0 171
547	#define SRST_H_PERILP0_NOC 172
548	#define SRST_ROM 173
549	#define SRST_CRYPTO_S 174
550	#define SRST_CRYPTO_M 175
551
552	/* cru_softrst_con11 */
553	#define SRST_P_DCF 176
554	#define SRST_CM0S_NOC 177
555	#define SRST_CM0S 178
556	#define SRST_CM0S_DBG 179
557	#define SRST_CM0S_PO 180
558	#define SRST_CRYPTO 181
559	#define SRST_P_PERILP1_SGRF 182
560	#define SRST_P_PERILP1_GRF 183
561	#define SRST_CRYPTO1_S 184
562	#define SRST_CRYPTO1_M 185
563	#define SRST_CRYPTO1 186
564	#define SRST_GIC_NOC 188
565	#define SRST_SD_NOC 189
566	#define SRST_SDIOAUDIO_BRG 190
567
568	/* cru_softrst_con12 */
569	#define SRST_H_PERILP1 192
570	#define SRST_H_PERILP1_NOC 193
571	#define SRST_H_I2S0_8CH 194
572	#define SRST_H_I2S1_8CH 195
573	#define SRST_H_I2S2_8CH 196
574	#define SRST_H_SPDIF_8CH 197
575	#define SRST_P_PERILP1_NOC 198
576	#define SRST_P_EFUSE_1024 199
577	#define SRST_P_EFUSE_1024S 200
578	#define SRST_P_I2C0 201
579	#define SRST_P_I2C1 202
580	#define SRST_P_I2C2 203
581	#define SRST_P_I2C3 204
582	#define SRST_P_I2C4 205
583	#define SRST_P_I2C5 206
584	#define SRST_P_MAILBOX0 207
585
586	/* cru_softrst_con13 */
587	#define SRST_P_UART0 208
588	#define SRST_P_UART1 209
589	#define SRST_P_UART2 210
590	#define SRST_P_UART3 211
591	#define SRST_P_SARADC 212
592	#define SRST_P_TSADC 213
593	#define SRST_P_SPI0 214
594	#define SRST_P_SPI1 215
595	#define SRST_P_SPI2 216
5ae2fd97 KY	596	#define SRST_P_SPI4 217
5ae2fd97 KY	597	#define SRST_P_SPI5 218
777c834f KY	598	#define SRST_SPI0 219
	599	#define SRST_SPI1 220
	600	#define SRST_SPI2 221
5ae2fd97 KY	601	#define SRST_SPI4 222
5ae2fd97 KY	602	#define SRST_SPI5 223
777c834f KY	603
	604	/* cru_softrst_con14 */
	605	#define SRST_I2S0_8CH 224
	606	#define SRST_I2S1_8CH 225
	607	#define SRST_I2S2_8CH 226
	608	#define SRST_SPDIF_8CH 227
	609	#define SRST_UART0 228
	610	#define SRST_UART1 229
	611	#define SRST_UART2 230
	612	#define SRST_UART3 231
	613	#define SRST_TSADC 232
	614	#define SRST_I2C0 233
	615	#define SRST_I2C1 234
	616	#define SRST_I2C2 235
	617	#define SRST_I2C3 236
	618	#define SRST_I2C4 237
	619	#define SRST_I2C5 238
	620	#define SRST_SDIOAUDIO_NOC 239
	621
	622	/* cru_softrst_con15 */
	623	#define SRST_A_VIO_NOC 240
	624	#define SRST_A_HDCP_NOC 241
	625	#define SRST_A_HDCP 242
	626	#define SRST_H_HDCP_NOC 243
	627	#define SRST_H_HDCP 244
	628	#define SRST_P_HDCP_NOC 245
	629	#define SRST_P_HDCP 246
	630	#define SRST_P_HDMI_CTRL 247
	631	#define SRST_P_DP_CTRL 248
	632	#define SRST_S_DP_CTRL 249
	633	#define SRST_C_DP_CTRL 250
	634	#define SRST_P_MIPI_DSI0 251
	635	#define SRST_P_MIPI_DSI1 252
	636	#define SRST_DP_CORE 253
	637	#define SRST_DP_I2S 254
	638
	639	/* cru_softrst_con16 */
	640	#define SRST_GASKET 256
	641	#define SRST_VIO_GRF 258
	642	#define SRST_DPTX_SPDIF_REC 259
	643	#define SRST_HDMI_CTRL 260
	644	#define SRST_HDCP_CTRL 261
	645	#define SRST_A_ISP0_NOC 262
	646	#define SRST_A_ISP1_NOC 263
	647	#define SRST_H_ISP0_NOC 266
	648	#define SRST_H_ISP1_NOC 267
	649	#define SRST_H_ISP0 268
	650	#define SRST_H_ISP1 269
	651	#define SRST_ISP0 270
	652	#define SRST_ISP1 271
	653
	654	/* cru_softrst_con17 */
	655	#define SRST_A_VOP0_NOC 272
	656	#define SRST_A_VOP1_NOC 273
	657	#define SRST_A_VOP0 274
	658	#define SRST_A_VOP1 275
	659	#define SRST_H_VOP0_NOC 276
	660	#define SRST_H_VOP1_NOC 277
	661	#define SRST_H_VOP0 278
	662	#define SRST_H_VOP1 279
	663	#define SRST_D_VOP0 280
	664	#define SRST_D_VOP1 281
	665	#define SRST_VOP0_PWM 282
	666	#define SRST_VOP1_PWM 283
667	#define SRST_P_EDP_NOC 284
668	#define SRST_P_EDP_CTRL 285
669
670	/* cru_softrst_con18 */
671	#define SRST_A_GPU 288
672	#define SRST_A_GPU_NOC 289
673	#define SRST_A_GPU_GRF 290
674	#define SRST_PVTM_GPU 291
675	#define SRST_A_USB3_NOC 292
676	#define SRST_A_USB3_OTG0 293
677	#define SRST_A_USB3_OTG1 294
678	#define SRST_A_USB3_GRF 295
679	#define SRST_PMU 296
680
681	/* cru_softrst_con19 */
682	#define SRST_P_TIMER0_5 304
683	#define SRST_TIMER0 305
684	#define SRST_TIMER1 306
685	#define SRST_TIMER2 307
686	#define SRST_TIMER3 308
687	#define SRST_TIMER4 309
688	#define SRST_TIMER5 310
689	#define SRST_P_TIMER6_11 311
690	#define SRST_TIMER6 312
691	#define SRST_TIMER7 313
692	#define SRST_TIMER8 314
693	#define SRST_TIMER9 315
694	#define SRST_TIMER10 316
695	#define SRST_TIMER11 317
696	#define SRST_P_INTR_ARB_PMU 318
697	#define SRST_P_ALIVE_SGRF 319
698
699	/* cru_softrst_con20 */
700	#define SRST_P_GPIO2 320
701	#define SRST_P_GPIO3 321
702	#define SRST_P_GPIO4 322
703	#define SRST_P_GRF 323
704	#define SRST_P_ALIVE_NOC 324
705	#define SRST_P_WDT0 325
706	#define SRST_P_WDT1 326
707	#define SRST_P_INTR_ARB 327
708	#define SRST_P_UPHY0_DPTX 328
709	#define SRST_P_UPHY0_APB 330
710	#define SRST_P_UPHY0_TCPHY 332
711	#define SRST_P_UPHY1_TCPHY 333
712	#define SRST_P_UPHY0_TCPDCTRL 334
713	#define SRST_P_UPHY1_TCPDCTRL 335
714
715	/* pmu soft-reset indices */
716
717	/* pmu_cru_softrst_con0 */
718	#define SRST_P_NOC 0
719	#define SRST_P_INTMEM 1
720	#define SRST_H_CM0S 2
721	#define SRST_H_CM0S_NOC 3
722	#define SRST_DBG_CM0S 4
723	#define SRST_PO_CM0S 5
5ae2fd97 KY	724	#define SRST_P_SPI3 6
5ae2fd97 KY	725	#define SRST_SPI3 7
777c834f KY	726	#define SRST_P_TIMER_0_1 8
	727	#define SRST_P_TIMER_0 9
	728	#define SRST_P_TIMER_1 10
	729	#define SRST_P_UART4 11
	730	#define SRST_UART4 12
	731	#define SRST_P_WDT 13
	732
	733	/* pmu_cru_softrst_con1 */
	734	#define SRST_P_I2C6 16
	735	#define SRST_P_I2C7 17
	736	#define SRST_P_I2C8 18
	737	#define SRST_P_MAILBOX 19
	738	#define SRST_P_RKPWM 20
	739	#define SRST_P_PMUGRF 21
	740	#define SRST_P_SGRF 22
	741	#define SRST_P_GPIO0 23
	742	#define SRST_P_GPIO1 24
	743	#define SRST_P_CRU 25
	744	#define SRST_P_INTR 26
	745	#define SRST_PVTM 27
	746	#define SRST_I2C6 28
	747	#define SRST_I2C7 29
	748	#define SRST_I2C8 30
	749
	750	#endif