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71665ebf SR |
1 | /* |
2 | * (C) Copyright 2008 | |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <ppc4xx.h> | |
26 | #include <asm/io.h> | |
27 | #include <asm/processor.h> | |
28 | ||
29 | static void wait_init_complete(void) | |
30 | { | |
31 | u32 val; | |
32 | ||
33 | do { | |
34 | mfsdram(SDRAM_MCSTAT, val); | |
35 | } while (!(val & 0x80000000)); | |
36 | } | |
37 | ||
9973e3c6 | 38 | phys_size_t initdram(int board_type) |
71665ebf SR |
39 | { |
40 | /* | |
41 | * Reset the DDR-SDRAM controller. | |
42 | */ | |
43 | mtsdr(SDR0_SRST, (0x80000000 >> 10)); | |
44 | mtsdr(SDR0_SRST, 0x00000000); | |
45 | ||
46 | /* | |
47 | * These values are cloned from a running NOR booting | |
48 | * Canyonlands with SPD-DDR2 detection and calibration | |
49 | * enabled. This will only work for the same memory | |
50 | * configuration as used here: | |
51 | * | |
4f27098e | 52 | * Crucial CT6464AC667.8FB - 512MB SO-DIMM |
71665ebf SR |
53 | * |
54 | */ | |
55 | mtsdram(SDRAM_MCOPT2, 0x00000000); | |
4f27098e | 56 | mtsdram(SDRAM_MCOPT1, 0x05122000); |
71665ebf | 57 | mtsdram(SDRAM_MODT0, 0x01000000); |
4f27098e | 58 | mtsdram(SDRAM_CODT, 0x02800021); |
71665ebf SR |
59 | mtsdram(SDRAM_WRDTR, 0x82000823); |
60 | mtsdram(SDRAM_CLKTR, 0x40000000); | |
61 | mtsdram(SDRAM_MB0CF, 0x00000201); | |
4f27098e | 62 | mtsdram(SDRAM_MB1CF, 0x00000201); |
71665ebf SR |
63 | mtsdram(SDRAM_RTR, 0x06180000); |
64 | mtsdram(SDRAM_SDTR1, 0x80201000); | |
65 | mtsdram(SDRAM_SDTR2, 0x42103243); | |
4f27098e | 66 | mtsdram(SDRAM_SDTR3, 0x0A0D0D16); |
71665ebf SR |
67 | mtsdram(SDRAM_MMODE, 0x00000632); |
68 | mtsdram(SDRAM_MEMODE, 0x00000040); | |
69 | mtsdram(SDRAM_INITPLR0, 0xB5380000); | |
70 | mtsdram(SDRAM_INITPLR1, 0x82100400); | |
71 | mtsdram(SDRAM_INITPLR2, 0x80820000); | |
72 | mtsdram(SDRAM_INITPLR3, 0x80830000); | |
73 | mtsdram(SDRAM_INITPLR4, 0x80810040); | |
74 | mtsdram(SDRAM_INITPLR5, 0x80800532); | |
75 | mtsdram(SDRAM_INITPLR6, 0x82100400); | |
76 | mtsdram(SDRAM_INITPLR7, 0x8A080000); | |
77 | mtsdram(SDRAM_INITPLR8, 0x8A080000); | |
78 | mtsdram(SDRAM_INITPLR9, 0x8A080000); | |
79 | mtsdram(SDRAM_INITPLR10, 0x8A080000); | |
80 | mtsdram(SDRAM_INITPLR11, 0x80000432); | |
81 | mtsdram(SDRAM_INITPLR12, 0x808103C0); | |
82 | mtsdram(SDRAM_INITPLR13, 0x80810040); | |
83 | mtsdram(SDRAM_INITPLR14, 0x00000000); | |
84 | mtsdram(SDRAM_INITPLR15, 0x00000000); | |
85 | ||
86 | mtsdram(SDRAM_MCOPT2, 0x28000000); | |
87 | ||
88 | wait_init_complete(); | |
89 | ||
4f27098e SR |
90 | mtdcr(SDRAM_R0BAS, 0x0000F800); /* MQ0_B0BAS */ |
91 | mtdcr(SDRAM_R1BAS, 0x0400F800); /* MQ0_B1BAS */ | |
71665ebf SR |
92 | |
93 | mtsdram(SDRAM_RDCC, 0x40000000); | |
94 | mtsdram(SDRAM_RQDC, 0x80000038); | |
95 | mtsdram(SDRAM_RFDC, 0x00000257); | |
96 | ||
6d0f6bcf | 97 | return CONFIG_SYS_MBYTES_SDRAM << 20; |
71665ebf | 98 | } |