[people/ms/u-boot.git] / post / cpu / mpc8xx / uart.c

/*
 * (C) Copyright 2002
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>

/*
 * UART test
 *
 * The Serial Management Controllers (SMC) and the Serial Communication
 * Controllers (SCC) listed in ctlr_list array below are tested in
 * the loopback UART mode.
 * The controllers are configured accordingly and several characters
 * are transmitted. The configurable test parameters are:
 *   MIN_PACKET_LENGTH - minimum size of packet to transmit
 *   MAX_PACKET_LENGTH - maximum size of packet to transmit
 *   TEST_NUM - number of tests
 */

#include <post.h>
#if CONFIG_POST & CONFIG_SYS_POST_UART
#if defined(CONFIG_8xx)
#include <commproc.h>
#elif defined(CONFIG_MPC8260)
#include <asm/cpm_8260.h>
#else
#error "Apparently a bad configuration, please fix."
#endif
#include <command.h>
#include <serial.h>

DECLARE_GLOBAL_DATA_PTR;

#define CTLR_SMC 0
#define CTLR_SCC 1

/* The list of controllers to test */
#if defined(CONFIG_MPC823)
static int ctlr_list[][2] =
		{ {CTLR_SMC, 0}, {CTLR_SMC, 1}, {CTLR_SCC, 1} };
#else
static int ctlr_list[][2] = { };
#endif

static struct {
	void (*init) (int index);
	void (*halt) (int index);
	void (*putc) (int index, const char c);
	int (*getc) (int index);
} ctlr_proc[2];

static char *ctlr_name[2] = { "SMC", "SCC" };

static int proff_smc[] = { PROFF_SMC1, PROFF_SMC2 };
static int proff_scc[] =
		{ PROFF_SCC1, PROFF_SCC2, PROFF_SCC3, PROFF_SCC4 };

/*
 * SMC callbacks
 */

static void smc_init (int smc_index)
{
	static int cpm_cr_ch[] = { CPM_CR_CH_SMC1, CPM_CR_CH_SMC2 };

	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
	volatile smc_t *sp;
	volatile smc_uart_t *up;
	volatile cbd_t *tbdf, *rbdf;
	volatile cpm8xx_t *cp = &(im->im_cpm);
	uint dpaddr;

	/* initialize pointers to SMC */

	sp = (smc_t *) & (cp->cp_smc[smc_index]);
	up = (smc_uart_t *) & cp->cp_dparam[proff_smc[smc_index]];

	/* Disable transmitter/receiver.
	 */
	sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);

	/* Enable SDMA.
	 */
	im->im_siu_conf.sc_sdcr = 1;

	/* clear error conditions */
#ifdef	CONFIG_SYS_SDSR
	im->im_sdma.sdma_sdsr = CONFIG_SYS_SDSR;
#else
	im->im_sdma.sdma_sdsr = 0x83;
#endif

	/* clear SDMA interrupt mask */
#ifdef	CONFIG_SYS_SDMR
	im->im_sdma.sdma_sdmr = CONFIG_SYS_SDMR;
#else
	im->im_sdma.sdma_sdmr = 0x00;
#endif

	/* Set the physical address of the host memory buffers in
	 * the buffer descriptors.
	 */
	dpaddr = CPM_POST_BASE;

	/* Allocate space for two buffer descriptors in the DP ram.
	 * For now, this address seems OK, but it may have to
	 * change with newer versions of the firmware.
	 * damm: allocating space after the two buffers for rx/tx data
	 */

	rbdf = (cbd_t *) & cp->cp_dpmem[dpaddr];
	rbdf->cbd_bufaddr = (uint) (rbdf + 2);
	rbdf->cbd_sc = 0;
	tbdf = rbdf + 1;
	tbdf->cbd_bufaddr = ((uint) (rbdf + 2)) + 1;
	tbdf->cbd_sc = 0;

	/* Set up the uart parameters in the parameter ram.
	 */
	up->smc_rbase = dpaddr;
	up->smc_tbase = dpaddr + sizeof (cbd_t);
	up->smc_rfcr = SMC_EB;
	up->smc_tfcr = SMC_EB;

	/* Set UART mode, 8 bit, no parity, one stop.
	 * Enable receive and transmit.
	 * Set local loopback mode.
	 */
	sp->smc_smcmr = smcr_mk_clen (9) | SMCMR_SM_UART | (ushort) 0x0004;

	/* Mask all interrupts and remove anything pending.
	 */
	sp->smc_smcm = 0;
	sp->smc_smce = 0xff;

	/* Set up the baud rate generator.
	 */
	cp->cp_simode = 0x00000000;

	cp->cp_brgc1 =
			(((gd->cpu_clk / 16 / gd->baudrate) -
			  1) << 1) | CPM_BRG_EN;

	/* Make the first buffer the only buffer.
	 */
	tbdf->cbd_sc |= BD_SC_WRAP;
	rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;

	/* Single character receive.
	 */
	up->smc_mrblr = 1;
	up->smc_maxidl = 0;

	/* Initialize Tx/Rx parameters.
	 */

	while (cp->cp_cpcr & CPM_CR_FLG)	/* wait if cp is busy */
		;

	cp->cp_cpcr =
			mk_cr_cmd (cpm_cr_ch[smc_index], CPM_CR_INIT_TRX) | CPM_CR_FLG;

	while (cp->cp_cpcr & CPM_CR_FLG)	/* wait if cp is busy */
		;

	/* Enable transmitter/receiver.
	 */
	sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
}

static void smc_halt(int smc_index)
{
}

static void smc_putc (int smc_index, const char c)
{
	volatile cbd_t *tbdf;
	volatile char *buf;
	volatile smc_uart_t *up;
	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
	volatile cpm8xx_t *cpmp = &(im->im_cpm);

	up = (smc_uart_t *) & cpmp->cp_dparam[proff_smc[smc_index]];

	tbdf = (cbd_t *) & cpmp->cp_dpmem[up->smc_tbase];

	/* Wait for last character to go.
	 */

	buf = (char *) tbdf->cbd_bufaddr;
#if 0
	__asm__ ("eieio");
	while (tbdf->cbd_sc & BD_SC_READY)
		__asm__ ("eieio");
#endif

	*buf = c;
	tbdf->cbd_datlen = 1;
	tbdf->cbd_sc |= BD_SC_READY;
	__asm__ ("eieio");
#if 1
	while (tbdf->cbd_sc & BD_SC_READY)
		__asm__ ("eieio");
#endif
}

static int smc_getc (int smc_index)
{
	volatile cbd_t *rbdf;
	volatile unsigned char *buf;
	volatile smc_uart_t *up;
	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
	volatile cpm8xx_t *cpmp = &(im->im_cpm);
	unsigned char c;
	int i;

	up = (smc_uart_t *) & cpmp->cp_dparam[proff_smc[smc_index]];

	rbdf = (cbd_t *) & cpmp->cp_dpmem[up->smc_rbase];

	/* Wait for character to show up.
	 */
	buf = (unsigned char *) rbdf->cbd_bufaddr;
#if 0
	while (rbdf->cbd_sc & BD_SC_EMPTY);
#else
	for (i = 100; i > 0; i--) {
		if (!(rbdf->cbd_sc & BD_SC_EMPTY))
			break;
		udelay (1000);
	}

	if (i == 0)
		return -1;
#endif
	c = *buf;
	rbdf->cbd_sc |= BD_SC_EMPTY;

	return (c);
}

  /*
   * SCC callbacks
   */

static void scc_init (int scc_index)
{
	static int cpm_cr_ch[] = {
		CPM_CR_CH_SCC1,
		CPM_CR_CH_SCC2,
		CPM_CR_CH_SCC3,
		CPM_CR_CH_SCC4,
	};

	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
	volatile scc_t *sp;
	volatile scc_uart_t *up;
	volatile cbd_t *tbdf, *rbdf;
	volatile cpm8xx_t *cp = &(im->im_cpm);
	uint dpaddr;

	/* initialize pointers to SCC */

	sp = (scc_t *) & (cp->cp_scc[scc_index]);
	up = (scc_uart_t *) & cp->cp_dparam[proff_scc[scc_index]];

	/* Disable transmitter/receiver.
	 */
	sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);

	dpaddr = CPM_POST_BASE;

	/* Enable SDMA.
	 */
	im->im_siu_conf.sc_sdcr = 0x0001;

	/* Set the physical address of the host memory buffers in
	 * the buffer descriptors.
	 */

	rbdf = (cbd_t *) & cp->cp_dpmem[dpaddr];
	rbdf->cbd_bufaddr = (uint) (rbdf + 2);
	rbdf->cbd_sc = 0;
	tbdf = rbdf + 1;
	tbdf->cbd_bufaddr = ((uint) (rbdf + 2)) + 1;
	tbdf->cbd_sc = 0;

	/* Set up the baud rate generator.
	 */
	cp->cp_sicr &= ~(0x000000FF << (8 * scc_index));
	/* no |= needed, since BRG1 is 000 */

	cp->cp_brgc1 =
			(((gd->cpu_clk / 16 / gd->baudrate) -
			  1) << 1) | CPM_BRG_EN;

	/* Set up the uart parameters in the parameter ram.
	 */
	up->scc_genscc.scc_rbase = dpaddr;
	up->scc_genscc.scc_tbase = dpaddr + sizeof (cbd_t);

	/* Initialize Tx/Rx parameters.
	 */
	while (cp->cp_cpcr & CPM_CR_FLG)	/* wait if cp is busy */
		;
	cp->cp_cpcr =
			mk_cr_cmd (cpm_cr_ch[scc_index], CPM_CR_INIT_TRX) | CPM_CR_FLG;

	while (cp->cp_cpcr & CPM_CR_FLG)	/* wait if cp is busy */
		;

	up->scc_genscc.scc_rfcr = SCC_EB | 0x05;
	up->scc_genscc.scc_tfcr = SCC_EB | 0x05;

	up->scc_genscc.scc_mrblr = 1;	/* Single character receive */
	up->scc_maxidl = 0;		/* disable max idle */
	up->scc_brkcr = 1;		/* send one break character on stop TX */
	up->scc_parec = 0;
	up->scc_frmec = 0;
	up->scc_nosec = 0;
	up->scc_brkec = 0;
	up->scc_uaddr1 = 0;
	up->scc_uaddr2 = 0;
	up->scc_toseq = 0;
	up->scc_char1 = 0x8000;
	up->scc_char2 = 0x8000;
	up->scc_char3 = 0x8000;
	up->scc_char4 = 0x8000;
	up->scc_char5 = 0x8000;
	up->scc_char6 = 0x8000;
	up->scc_char7 = 0x8000;
	up->scc_char8 = 0x8000;
	up->scc_rccm = 0xc0ff;

	/* Set low latency / small fifo.
	 */
	sp->scc_gsmrh = SCC_GSMRH_RFW;

	/* Set UART mode
	 */
	sp->scc_gsmrl &= ~0xF;
	sp->scc_gsmrl |= SCC_GSMRL_MODE_UART;

	/* Set local loopback mode.
	 */
	sp->scc_gsmrl &= ~SCC_GSMRL_DIAG_LE;
	sp->scc_gsmrl |= SCC_GSMRL_DIAG_LOOP;

	/* Set clock divider 16 on Tx and Rx
	 */
	sp->scc_gsmrl |= (SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);

	sp->scc_psmr |= SCU_PSMR_CL;

	/* Mask all interrupts and remove anything pending.
	 */
	sp->scc_sccm = 0;
	sp->scc_scce = 0xffff;
	sp->scc_dsr = 0x7e7e;
	sp->scc_psmr = 0x3000;

	/* Make the first buffer the only buffer.
	 */
	tbdf->cbd_sc |= BD_SC_WRAP;
	rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;

	/* Enable transmitter/receiver.
	 */
	sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
}

static void scc_halt(int scc_index)
{
	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
	volatile cpm8xx_t *cp = &(im->im_cpm);
	volatile scc_t *sp = (scc_t *) & (cp->cp_scc[scc_index]);

	sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT | SCC_GSMRL_DIAG_LE);
}

static void scc_putc (int scc_index, const char c)
{
	volatile cbd_t *tbdf;
	volatile char *buf;
	volatile scc_uart_t *up;
	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
	volatile cpm8xx_t *cpmp = &(im->im_cpm);

	up = (scc_uart_t *) & cpmp->cp_dparam[proff_scc[scc_index]];

	tbdf = (cbd_t *) & cpmp->cp_dpmem[up->scc_genscc.scc_tbase];

	/* Wait for last character to go.
	 */

	buf = (char *) tbdf->cbd_bufaddr;
#if 0
	__asm__ ("eieio");
	while (tbdf->cbd_sc & BD_SC_READY)
		__asm__ ("eieio");
#endif

	*buf = c;
	tbdf->cbd_datlen = 1;
	tbdf->cbd_sc |= BD_SC_READY;
	__asm__ ("eieio");
#if 1
	while (tbdf->cbd_sc & BD_SC_READY)
		__asm__ ("eieio");
#endif
}

static int scc_getc (int scc_index)
{
	volatile cbd_t *rbdf;
	volatile unsigned char *buf;
	volatile scc_uart_t *up;
	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
	volatile cpm8xx_t *cpmp = &(im->im_cpm);
	unsigned char c;
	int i;

	up = (scc_uart_t *) & cpmp->cp_dparam[proff_scc[scc_index]];

	rbdf = (cbd_t *) & cpmp->cp_dpmem[up->scc_genscc.scc_rbase];

	/* Wait for character to show up.
	 */
	buf = (unsigned char *) rbdf->cbd_bufaddr;
#if 0
	while (rbdf->cbd_sc & BD_SC_EMPTY);
#else
	for (i = 100; i > 0; i--) {
		if (!(rbdf->cbd_sc & BD_SC_EMPTY))
			break;
		udelay (1000);
	}

	if (i == 0)
		return -1;
#endif
	c = *buf;
	rbdf->cbd_sc |= BD_SC_EMPTY;

	return (c);
}

  /*
   * Test routines
   */

static int test_ctlr (int ctlr, int index)
{
	int res = -1;
	char test_str[] = "*** UART Test String ***\r\n";
	int i;

	ctlr_proc[ctlr].init (index);

	for (i = 0; i < sizeof (test_str) - 1; i++) {
		ctlr_proc[ctlr].putc (index, test_str[i]);
		if (ctlr_proc[ctlr].getc (index) != test_str[i])
			goto Done;
	}

	res = 0;

Done:
	ctlr_proc[ctlr].halt (index);

	if (res != 0) {
		post_log ("uart %s%d test failed\n",
				ctlr_name[ctlr], index + 1);
	}

	return res;
}

int uart_post_test (int flags)
{
	int res = 0;
	int i;

	ctlr_proc[CTLR_SMC].init = smc_init;
	ctlr_proc[CTLR_SMC].halt = smc_halt;
	ctlr_proc[CTLR_SMC].putc = smc_putc;
	ctlr_proc[CTLR_SMC].getc = smc_getc;

	ctlr_proc[CTLR_SCC].init = scc_init;
	ctlr_proc[CTLR_SCC].halt = scc_halt;
	ctlr_proc[CTLR_SCC].putc = scc_putc;
	ctlr_proc[CTLR_SCC].getc = scc_getc;

	for (i = 0; i < ARRAY_SIZE(ctlr_list); i++) {
		if (test_ctlr (ctlr_list[i][0], ctlr_list[i][1]) != 0) {
			res = -1;
		}
	}

#if !defined(CONFIG_8xx_CONS_NONE)
	serial_reinit_all ();
#endif

	return res;
}

#endif /* CONFIG_POST & CONFIG_SYS_POST_UART */
Commit	Line	Data
ad5bb451 WD	1	/*
	2	* (C) Copyright 2002
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
ad5bb451 WD	6	*/
	7
	8	#include <common.h>
	9
	10	/*
	11	* UART test
	12	*
	13	* The Serial Management Controllers (SMC) and the Serial Communication
	14	* Controllers (SCC) listed in ctlr_list array below are tested in
	15	* the loopback UART mode.
	16	* The controllers are configured accordingly and several characters
	17	* are transmitted. The configurable test parameters are:
	18	* MIN_PACKET_LENGTH - minimum size of packet to transmit
	19	* MAX_PACKET_LENGTH - maximum size of packet to transmit
	20	* TEST_NUM - number of tests
	21	*/
	22
ad5bb451	23	#include <post.h>
6d0f6bcf	24	#if CONFIG_POST & CONFIG_SYS_POST_UART
ad5bb451 WD	25	#if defined(CONFIG_8xx)
	26	#include <commproc.h>
	27	#elif defined(CONFIG_MPC8260)
	28	#include <asm/cpm_8260.h>
	29	#else
	30	#error "Apparently a bad configuration, please fix."
	31	#endif
	32	#include <command.h>
	33	#include <serial.h>
	34
	35	DECLARE_GLOBAL_DATA_PTR;
	36
	37	#define CTLR_SMC 0
	38	#define CTLR_SCC 1
	39
	40	/* The list of controllers to test */
	41	#if defined(CONFIG_MPC823)
	42	static int ctlr_list[][2] =
	43	{ {CTLR_SMC, 0}, {CTLR_SMC, 1}, {CTLR_SCC, 1} };
	44	#else
	45	static int ctlr_list[][2] = { };
	46	#endif
	47
ad5bb451 WD	48	static struct {
	49	void (*init) (int index);
	50	void (*halt) (int index);
	51	void (*putc) (int index, const char c);
	52	int (*getc) (int index);
	53	} ctlr_proc[2];
	54
	55	static char *ctlr_name[2] = { "SMC", "SCC" };
	56
	57	static int proff_smc[] = { PROFF_SMC1, PROFF_SMC2 };
	58	static int proff_scc[] =
	59	{ PROFF_SCC1, PROFF_SCC2, PROFF_SCC3, PROFF_SCC4 };
	60
	61	/*
	62	* SMC callbacks
	63	*/
	64
	65	static void smc_init (int smc_index)
	66	{
	67	static int cpm_cr_ch[] = { CPM_CR_CH_SMC1, CPM_CR_CH_SMC2 };
	68
6d0f6bcf	69	volatile immap_t im = (immap_t ) CONFIG_SYS_IMMR;
ad5bb451 WD	70	volatile smc_t *sp;
	71	volatile smc_uart_t *up;
	72	volatile cbd_t tbdf, rbdf;
	73	volatile cpm8xx_t *cp = &(im->im_cpm);
	74	uint dpaddr;
	75
	76	/* initialize pointers to SMC */
	77
	78	sp = (smc_t *) & (cp->cp_smc[smc_index]);
	79	up = (smc_uart_t *) & cp->cp_dparam[proff_smc[smc_index]];
	80
	81	/* Disable transmitter/receiver.
	82	*/
	83	sp->smc_smcmr &= ~(SMCMR_REN \| SMCMR_TEN);
	84
	85	/* Enable SDMA.
	86	*/
	87	im->im_siu_conf.sc_sdcr = 1;
	88
	89	/* clear error conditions */
6d0f6bcf JCPV	90	#ifdef CONFIG_SYS_SDSR
6d0f6bcf JCPV	91	im->im_sdma.sdma_sdsr = CONFIG_SYS_SDSR;
ad5bb451 WD	92	#else
	93	im->im_sdma.sdma_sdsr = 0x83;
	94	#endif
	95
	96	/* clear SDMA interrupt mask */
6d0f6bcf JCPV	97	#ifdef CONFIG_SYS_SDMR
6d0f6bcf JCPV	98	im->im_sdma.sdma_sdmr = CONFIG_SYS_SDMR;
ad5bb451 WD	99	#else
	100	im->im_sdma.sdma_sdmr = 0x00;
	101	#endif
	102
ad5bb451 WD	103	/* Set the physical address of the host memory buffers in
	104	* the buffer descriptors.
	105	*/
ad5bb451	106	dpaddr = CPM_POST_BASE;
ad5bb451 WD	107
	108	/* Allocate space for two buffer descriptors in the DP ram.
	109	* For now, this address seems OK, but it may have to
	110	* change with newer versions of the firmware.
	111	* damm: allocating space after the two buffers for rx/tx data
	112	*/
	113
	114	rbdf = (cbd_t *) & cp->cp_dpmem[dpaddr];
	115	rbdf->cbd_bufaddr = (uint) (rbdf + 2);
	116	rbdf->cbd_sc = 0;
	117	tbdf = rbdf + 1;
	118	tbdf->cbd_bufaddr = ((uint) (rbdf + 2)) + 1;
	119	tbdf->cbd_sc = 0;
	120
	121	/* Set up the uart parameters in the parameter ram.
	122	*/
	123	up->smc_rbase = dpaddr;
	124	up->smc_tbase = dpaddr + sizeof (cbd_t);
	125	up->smc_rfcr = SMC_EB;
	126	up->smc_tfcr = SMC_EB;
	127
ad5bb451 WD	128	/* Set UART mode, 8 bit, no parity, one stop.
	129	* Enable receive and transmit.
	130	* Set local loopback mode.
	131	*/
	132	sp->smc_smcmr = smcr_mk_clen (9) \| SMCMR_SM_UART \| (ushort) 0x0004;
	133
	134	/* Mask all interrupts and remove anything pending.
	135	*/
	136	sp->smc_smcm = 0;
	137	sp->smc_smce = 0xff;
	138
	139	/* Set up the baud rate generator.
	140	*/
	141	cp->cp_simode = 0x00000000;
	142
	143	cp->cp_brgc1 =
	144	(((gd->cpu_clk / 16 / gd->baudrate) -
	145	1) << 1) \| CPM_BRG_EN;
	146
	147	/* Make the first buffer the only buffer.
	148	*/
	149	tbdf->cbd_sc \|= BD_SC_WRAP;
	150	rbdf->cbd_sc \|= BD_SC_EMPTY \| BD_SC_WRAP;
	151
	152	/* Single character receive.
	153	*/
	154	up->smc_mrblr = 1;
	155	up->smc_maxidl = 0;
	156
	157	/* Initialize Tx/Rx parameters.
	158	*/
	159
	160	while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
	161	;
	162
	163	cp->cp_cpcr =
	164	mk_cr_cmd (cpm_cr_ch[smc_index], CPM_CR_INIT_TRX) \| CPM_CR_FLG;
	165
	166	while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
	167	;
	168
	169	/* Enable transmitter/receiver.
	170	*/
	171	sp->smc_smcmr \|= SMCMR_REN \| SMCMR_TEN;
	172	}
	173
	174	static void smc_halt(int smc_index)
	175	{
	176	}
	177
	178	static void smc_putc (int smc_index, const char c)
	179	{
	180	volatile cbd_t *tbdf;
	181	volatile char *buf;
	182	volatile smc_uart_t *up;
6d0f6bcf	183	volatile immap_t im = (immap_t ) CONFIG_SYS_IMMR;
ad5bb451 WD	184	volatile cpm8xx_t *cpmp = &(im->im_cpm);
	185
	186	up = (smc_uart_t *) & cpmp->cp_dparam[proff_smc[smc_index]];
	187
	188	tbdf = (cbd_t *) & cpmp->cp_dpmem[up->smc_tbase];
	189
	190	/* Wait for last character to go.
	191	*/
	192
	193	buf = (char *) tbdf->cbd_bufaddr;
	194	#if 0
	195	__asm__ ("eieio");
	196	while (tbdf->cbd_sc & BD_SC_READY)
	197	__asm__ ("eieio");
	198	#endif
	199
	200	*buf = c;
	201	tbdf->cbd_datlen = 1;
	202	tbdf->cbd_sc \|= BD_SC_READY;
	203	__asm__ ("eieio");
	204	#if 1
	205	while (tbdf->cbd_sc & BD_SC_READY)
	206	__asm__ ("eieio");
	207	#endif
	208	}
	209
	210	static int smc_getc (int smc_index)
	211	{
	212	volatile cbd_t *rbdf;
	213	volatile unsigned char *buf;
	214	volatile smc_uart_t *up;
6d0f6bcf	215	volatile immap_t im = (immap_t ) CONFIG_SYS_IMMR;
ad5bb451 WD	216	volatile cpm8xx_t *cpmp = &(im->im_cpm);
	217	unsigned char c;
	218	int i;
	219
	220	up = (smc_uart_t *) & cpmp->cp_dparam[proff_smc[smc_index]];
	221
	222	rbdf = (cbd_t *) & cpmp->cp_dpmem[up->smc_rbase];
	223
	224	/* Wait for character to show up.
	225	*/
	226	buf = (unsigned char *) rbdf->cbd_bufaddr;
	227	#if 0
	228	while (rbdf->cbd_sc & BD_SC_EMPTY);
	229	#else
	230	for (i = 100; i > 0; i--) {
	231	if (!(rbdf->cbd_sc & BD_SC_EMPTY))
	232	break;
	233	udelay (1000);
	234	}
	235
	236	if (i == 0)
	237	return -1;
	238	#endif
	239	c = *buf;
	240	rbdf->cbd_sc \|= BD_SC_EMPTY;
	241
	242	return (c);
	243	}
	244
	245	/*
	246	* SCC callbacks
	247	*/
	248
	249	static void scc_init (int scc_index)
	250	{
	251	static int cpm_cr_ch[] = {
	252	CPM_CR_CH_SCC1,
	253	CPM_CR_CH_SCC2,
	254	CPM_CR_CH_SCC3,
	255	CPM_CR_CH_SCC4,
	256	};
	257
6d0f6bcf	258	volatile immap_t im = (immap_t ) CONFIG_SYS_IMMR;
ad5bb451 WD	259	volatile scc_t *sp;
	260	volatile scc_uart_t *up;
	261	volatile cbd_t tbdf, rbdf;
	262	volatile cpm8xx_t *cp = &(im->im_cpm);
	263	uint dpaddr;
	264
	265	/* initialize pointers to SCC */
	266
	267	sp = (scc_t *) & (cp->cp_scc[scc_index]);
	268	up = (scc_uart_t *) & cp->cp_dparam[proff_scc[scc_index]];
	269
	270	/* Disable transmitter/receiver.
	271	*/
	272	sp->scc_gsmrl &= ~(SCC_GSMRL_ENR \| SCC_GSMRL_ENT);
	273
ad5bb451	274	dpaddr = CPM_POST_BASE;
ad5bb451 WD	275
	276	/* Enable SDMA.
	277	*/
	278	im->im_siu_conf.sc_sdcr = 0x0001;
	279
	280	/* Set the physical address of the host memory buffers in
	281	* the buffer descriptors.
	282	*/
	283
	284	rbdf = (cbd_t *) & cp->cp_dpmem[dpaddr];
	285	rbdf->cbd_bufaddr = (uint) (rbdf + 2);
	286	rbdf->cbd_sc = 0;
	287	tbdf = rbdf + 1;
	288	tbdf->cbd_bufaddr = ((uint) (rbdf + 2)) + 1;
	289	tbdf->cbd_sc = 0;
	290
	291	/* Set up the baud rate generator.
	292	*/
	293	cp->cp_sicr &= ~(0x000000FF << (8 * scc_index));
	294	/* no \|= needed, since BRG1 is 000 */
	295
	296	cp->cp_brgc1 =
	297	(((gd->cpu_clk / 16 / gd->baudrate) -
	298	1) << 1) \| CPM_BRG_EN;
	299
	300	/* Set up the uart parameters in the parameter ram.
	301	*/
	302	up->scc_genscc.scc_rbase = dpaddr;
	303	up->scc_genscc.scc_tbase = dpaddr + sizeof (cbd_t);
	304
	305	/* Initialize Tx/Rx parameters.
	306	*/
	307	while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
	308	;
	309	cp->cp_cpcr =
	310	mk_cr_cmd (cpm_cr_ch[scc_index], CPM_CR_INIT_TRX) \| CPM_CR_FLG;
	311
	312	while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
	313	;
	314
	315	up->scc_genscc.scc_rfcr = SCC_EB \| 0x05;
	316	up->scc_genscc.scc_tfcr = SCC_EB \| 0x05;
	317
	318	up->scc_genscc.scc_mrblr = 1; /* Single character receive */
	319	up->scc_maxidl = 0; /* disable max idle */
	320	up->scc_brkcr = 1; /* send one break character on stop TX */
	321	up->scc_parec = 0;
	322	up->scc_frmec = 0;
	323	up->scc_nosec = 0;
	324	up->scc_brkec = 0;
	325	up->scc_uaddr1 = 0;
	326	up->scc_uaddr2 = 0;
	327	up->scc_toseq = 0;
	328	up->scc_char1 = 0x8000;
	329	up->scc_char2 = 0x8000;
	330	up->scc_char3 = 0x8000;
	331	up->scc_char4 = 0x8000;
	332	up->scc_char5 = 0x8000;
	333	up->scc_char6 = 0x8000;
	334	up->scc_char7 = 0x8000;
	335	up->scc_char8 = 0x8000;
	336	up->scc_rccm = 0xc0ff;
	337
	338	/* Set low latency / small fifo.
339	*/
340	sp->scc_gsmrh = SCC_GSMRH_RFW;
341
342	/* Set UART mode
343	*/
344	sp->scc_gsmrl &= ~0xF;
345	sp->scc_gsmrl \|= SCC_GSMRL_MODE_UART;
346
347	/* Set local loopback mode.
348	*/
349	sp->scc_gsmrl &= ~SCC_GSMRL_DIAG_LE;
350	sp->scc_gsmrl \|= SCC_GSMRL_DIAG_LOOP;
351
352	/* Set clock divider 16 on Tx and Rx
353	*/
354	sp->scc_gsmrl \|= (SCC_GSMRL_TDCR_16 \| SCC_GSMRL_RDCR_16);
355
356	sp->scc_psmr \|= SCU_PSMR_CL;
357
358	/* Mask all interrupts and remove anything pending.
359	*/
360	sp->scc_sccm = 0;
361	sp->scc_scce = 0xffff;
362	sp->scc_dsr = 0x7e7e;
363	sp->scc_psmr = 0x3000;
364
365	/* Make the first buffer the only buffer.
366	*/
367	tbdf->cbd_sc \|= BD_SC_WRAP;
368	rbdf->cbd_sc \|= BD_SC_EMPTY \| BD_SC_WRAP;
369
370	/* Enable transmitter/receiver.
371	*/
372	sp->scc_gsmrl \|= (SCC_GSMRL_ENR \| SCC_GSMRL_ENT);
373	}
374
375	static void scc_halt(int scc_index)
376	{
6d0f6bcf	377	volatile immap_t im = (immap_t ) CONFIG_SYS_IMMR;
ad5bb451 WD	378	volatile cpm8xx_t *cp = &(im->im_cpm);
	379	volatile scc_t sp = (scc_t ) & (cp->cp_scc[scc_index]);
	380
	381	sp->scc_gsmrl &= ~(SCC_GSMRL_ENR \| SCC_GSMRL_ENT \| SCC_GSMRL_DIAG_LE);
	382	}
	383
	384	static void scc_putc (int scc_index, const char c)
	385	{
	386	volatile cbd_t *tbdf;
	387	volatile char *buf;
	388	volatile scc_uart_t *up;
6d0f6bcf	389	volatile immap_t im = (immap_t ) CONFIG_SYS_IMMR;
ad5bb451 WD	390	volatile cpm8xx_t *cpmp = &(im->im_cpm);
	391
	392	up = (scc_uart_t *) & cpmp->cp_dparam[proff_scc[scc_index]];
	393
	394	tbdf = (cbd_t *) & cpmp->cp_dpmem[up->scc_genscc.scc_tbase];
	395
	396	/* Wait for last character to go.
	397	*/
	398
	399	buf = (char *) tbdf->cbd_bufaddr;
	400	#if 0
	401	__asm__ ("eieio");
	402	while (tbdf->cbd_sc & BD_SC_READY)
	403	__asm__ ("eieio");
	404	#endif
	405
	406	*buf = c;
	407	tbdf->cbd_datlen = 1;
	408	tbdf->cbd_sc \|= BD_SC_READY;
	409	__asm__ ("eieio");
	410	#if 1
	411	while (tbdf->cbd_sc & BD_SC_READY)
	412	__asm__ ("eieio");
	413	#endif
	414	}
	415
	416	static int scc_getc (int scc_index)
	417	{
	418	volatile cbd_t *rbdf;
	419	volatile unsigned char *buf;
	420	volatile scc_uart_t *up;
6d0f6bcf	421	volatile immap_t im = (immap_t ) CONFIG_SYS_IMMR;
ad5bb451 WD	422	volatile cpm8xx_t *cpmp = &(im->im_cpm);
	423	unsigned char c;
	424	int i;
	425
	426	up = (scc_uart_t *) & cpmp->cp_dparam[proff_scc[scc_index]];
	427
	428	rbdf = (cbd_t *) & cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
	429
	430	/* Wait for character to show up.
	431	*/
	432	buf = (unsigned char *) rbdf->cbd_bufaddr;
	433	#if 0
	434	while (rbdf->cbd_sc & BD_SC_EMPTY);
	435	#else
	436	for (i = 100; i > 0; i--) {
	437	if (!(rbdf->cbd_sc & BD_SC_EMPTY))
	438	break;
	439	udelay (1000);
	440	}
	441
	442	if (i == 0)
	443	return -1;
	444	#endif
	445	c = *buf;
	446	rbdf->cbd_sc \|= BD_SC_EMPTY;
	447
	448	return (c);
	449	}
	450
	451	/*
	452	* Test routines
	453	*/
	454
	455	static int test_ctlr (int ctlr, int index)
	456	{
	457	int res = -1;
	458	char test_str[] = "* UART Test String *\r\n";
	459	int i;
	460
	461	ctlr_proc[ctlr].init (index);
	462
	463	for (i = 0; i < sizeof (test_str) - 1; i++) {
	464	ctlr_proc[ctlr].putc (index, test_str[i]);
	465	if (ctlr_proc[ctlr].getc (index) != test_str[i])
	466	goto Done;
	467	}
	468
	469	res = 0;
	470
	471	Done:
	472	ctlr_proc[ctlr].halt (index);
	473
	474	if (res != 0) {
	475	post_log ("uart %s%d test failed\n",
	476	ctlr_name[ctlr], index + 1);
	477	}
	478
	479	return res;
	480	}
	481
	482	int uart_post_test (int flags)
	483	{
	484	int res = 0;
	485	int i;
486
487	ctlr_proc[CTLR_SMC].init = smc_init;
488	ctlr_proc[CTLR_SMC].halt = smc_halt;
489	ctlr_proc[CTLR_SMC].putc = smc_putc;
490	ctlr_proc[CTLR_SMC].getc = smc_getc;
491
492	ctlr_proc[CTLR_SCC].init = scc_init;
493	ctlr_proc[CTLR_SCC].halt = scc_halt;
494	ctlr_proc[CTLR_SCC].putc = scc_putc;
495	ctlr_proc[CTLR_SCC].getc = scc_getc;
496
d2397817	497	for (i = 0; i < ARRAY_SIZE(ctlr_list); i++) {
ad5bb451 WD	498	if (test_ctlr (ctlr_list[i][0], ctlr_list[i][1]) != 0) {
	499	res = -1;
	500	}
	501	}
	502
	503	#if !defined(CONFIG_8xx_CONS_NONE)
	504	serial_reinit_all ();
	505	#endif
	506
	507	return res;
	508	}
	509
6d0f6bcf	510	#endif /* CONFIG_POST & CONFIG_SYS_POST_UART */