| | 1 | /* |
| | 2 | * (C) Copyright 2000-2003 |
| | 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| | 4 | * |
| | 5 | * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. |
| | 6 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
| | 7 | * |
| | 8 | * SPDX-License-Identifier: GPL-2.0+ |
| | 9 | */ |
| | 10 | |
| | 11 | #include <config.h> |
| | 12 | #include <common.h> |
| | 13 | #include <asm/io.h> |
| | 14 | #include <asm/immap.h> |
| | 15 | |
| | 16 | DECLARE_GLOBAL_DATA_PTR; |
| | 17 | |
| | 18 | #if defined(CONFIG_CMD_NAND) |
| | 19 | #include <nand.h> |
| | 20 | #include <linux/mtd/mtd.h> |
| | 21 | |
| | 22 | #define SET_CLE 0x10 |
| | 23 | #define SET_ALE 0x08 |
| | 24 | |
| | 25 | static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) |
| | 26 | { |
| | 27 | struct nand_chip *this = mtdinfo->priv; |
| | 28 | volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR; |
| | 29 | |
| | 30 | if (ctrl & NAND_CTRL_CHANGE) { |
| | 31 | ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; |
| | 32 | |
| | 33 | IO_ADDR_W &= ~(SET_ALE | SET_CLE); |
| | 34 | |
| | 35 | if (ctrl & NAND_NCE) |
| | 36 | *nCE &= 0xFFFB; |
| | 37 | else |
| | 38 | *nCE |= 0x0004; |
| | 39 | |
| | 40 | if (ctrl & NAND_CLE) |
| | 41 | IO_ADDR_W |= SET_CLE; |
| | 42 | if (ctrl & NAND_ALE) |
| | 43 | IO_ADDR_W |= SET_ALE; |
| | 44 | |
| | 45 | this->IO_ADDR_W = (void *)IO_ADDR_W; |
| | 46 | } |
| | 47 | |
| | 48 | if (cmd != NAND_CMD_NONE) |
| | 49 | writeb(cmd, this->IO_ADDR_W); |
| | 50 | } |
| | 51 | |
| | 52 | int board_nand_init(struct nand_chip *nand) |
| | 53 | { |
| | 54 | gpio_t *gpio = (gpio_t *) MMAP_GPIO; |
| | 55 | |
| | 56 | /* |
| | 57 | * set up pin configuration - enabled 2nd output buffer's signals |
| | 58 | * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc) |
| | 59 | * to use nCE signal |
| | 60 | */ |
| | 61 | clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3); |
| | 62 | setbits_8(&gpio->pddr_timer, 0x08); |
| | 63 | setbits_8(&gpio->ppd_timer, 0x08); |
| | 64 | out_8(&gpio->pclrr_timer, 0); |
| | 65 | out_8(&gpio->podr_timer, 0); |
| | 66 | |
| | 67 | nand->chip_delay = 60; |
| | 68 | nand->ecc.mode = NAND_ECC_SOFT; |
| | 69 | nand->cmd_ctrl = nand_hwcontrol; |
| | 70 | |
| | 71 | return 0; |
| | 72 | } |
| | 73 | #endif |
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