Merge branch 'master' of git://www.denx.de/git/u-boot-imx

[people/ms/u-boot.git] / board / aries / m53evk / imximage.cfg

diff --git a/board/aries/m53evk/imximage.cfg b/board/aries/m53evk/imximage.cfg
new file mode 100644 (file)
index 0000000..ec855c8
--- /dev/null
+++ b/board/aries/m53evk/imximage.cfg
@@ -0,0 +1,92 @@
+/*
+ * Aries M53 DRAM init values
+ * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+#include <asm/imx-common/imximage.cfg>
+
+/* image version */
+IMAGE_VERSION  2
+
+
+/* Boot Offset 0x400, valid for both SD and NAND boot. */
+BOOT_OFFSET    FLASH_OFFSET_STANDARD
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *     Addr-type register length (1,2 or 4 bytes)
+ *     Address   absolute address of the register
+ *     value     value to be stored in the register
+ */
+DATA 4 0x53fa86f4 0x00000000    /* GRP_DDRMODE_CTL */
+DATA 4 0x53fa8714 0x00000000    /* GRP_DDRMODE */
+DATA 4 0x53fa86fc 0x00000000    /* GRP_DDRPKE */
+DATA 4 0x53fa8724 0x04000000    /* GRP_DDR_TYPE */
+
+DATA 4 0x53fa872c 0x00300000    /* GRP_B3DS */
+DATA 4 0x53fa8554 0x00300000    /* DRAM_DQM3 */
+DATA 4 0x53fa8558 0x00300040    /* DRAM_SDQS3 */
+
+DATA 4 0x53fa8728 0x00300000    /* GRP_B2DS */
+DATA 4 0x53fa8560 0x00300000    /* DRAM_DQM2 */
+DATA 4 0x53fa8568 0x00300040    /* DRAM_SDQS2 */
+
+DATA 4 0x53fa871c 0x00300000    /* GRP_B1DS */
+DATA 4 0x53fa8594 0x00300000    /* DRAM_DQM1 */
+DATA 4 0x53fa8590 0x00300040    /* DRAM_SDQS1 */
+
+DATA 4 0x53fa8718 0x00300000    /* GRP_B0DS */
+DATA 4 0x53fa8584 0x00300000    /* DRAM_DQM0 */
+DATA 4 0x53fa857c 0x00300040    /* DRAM_SDQS0 */
+
+DATA 4 0x53fa8578 0x00300000    /* DRAM_SDCLK_0 */
+DATA 4 0x53fa8570 0x00300000    /* DRAM_SDCLK_1 */
+
+DATA 4 0x53fa8574 0x00300000    /* DRAM_CAS */
+DATA 4 0x53fa8588 0x00300000    /* DRAM_RAS */
+DATA 4 0x53fa86f0 0x00300000    /* GRP_ADDDS */
+DATA 4 0x53fa8720 0x00300000    /* GRP_CTLDS */
+
+DATA 4 0x53fa8564 0x00300040    /* DRAM_SDODT1 */
+DATA 4 0x53fa8580 0x00300040    /* DRAM_SDODT0 */
+
+/* ESDCTL */
+DATA 4 0x63fd9088 0x32383535
+DATA 4 0x63fd9090 0x40383538
+DATA 4 0x63fd907c 0x0136014d
+DATA 4 0x63fd9080 0x01510141
+
+DATA 4 0x63fd9018 0x00011740
+DATA 4 0x63fd9000 0xc3190000
+DATA 4 0x63fd900c 0x555952e3
+DATA 4 0x63fd9010 0xb68e8b63
+DATA 4 0x63fd9014 0x01ff00db
+DATA 4 0x63fd902c 0x000026d2
+DATA 4 0x63fd9030 0x009f0e21
+DATA 4 0x63fd9008 0x12273030
+DATA 4 0x63fd9004 0x0002002d
+DATA 4 0x63fd901c 0x00008032
+DATA 4 0x63fd901c 0x00008033
+DATA 4 0x63fd901c 0x00028031
+DATA 4 0x63fd901c 0x092080b0
+DATA 4 0x63fd901c 0x04008040
+DATA 4 0x63fd901c 0x0000803a
+DATA 4 0x63fd901c 0x0000803b
+DATA 4 0x63fd901c 0x00028039
+DATA 4 0x63fd901c 0x09208138
+DATA 4 0x63fd901c 0x04008048
+DATA 4 0x63fd9020 0x00001800
+DATA 4 0x63fd9040 0x04b80003
+DATA 4 0x63fd9058 0x00022227
+DATA 4 0x63fd901c 0x00000000