Add GPL-2.0+ SPDX-License-Identifier to source files

[people/ms/u-boot.git] / board / prodrive / pdnb3 / nand.c

diff --git a/board/prodrive/pdnb3/nand.c b/board/prodrive/pdnb3/nand.c
index 1931d64de0c47b67c90eb2209b79814628e1781f..e1d2c630bf3bf97b7e52e6ead3899c2140fdd613 100644 (file)
--- a/board/prodrive/pdnb3/nand.c
+++ b/board/prodrive/pdnb3/nand.c
@@ -2,28 +2,12 @@
  * (C) Copyright 2006
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
 
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#if defined(CONFIG_CMD_NAND)
 
 #include <nand.h>
 
@@ -52,40 +36,26 @@ static struct pdnb3_ndfc_regs *pdnb3_ndfc;
  *
  * There is one NAND devices on the board, a Hynix HY27US08561A (32 MByte).
  */
-static void pdnb3_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+static void pdnb3_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 {
-       switch (cmd) {
-       case NAND_CTL_SETCLE:
-               hwctl |= 0x1;
-               break;
-       case NAND_CTL_CLRCLE:
-               hwctl &= ~0x1;
-               break;
-
-       case NAND_CTL_SETALE:
-               hwctl |= 0x2;
-               break;
-       case NAND_CTL_CLRALE:
-               hwctl &= ~0x2;
-               break;
-
-       case NAND_CTL_SETNCE:
-               break;
-       case NAND_CTL_CLRNCE:
-               writeb(0x00, &(pdnb3_ndfc->term));
-               break;
+       struct nand_chip *this = mtd->priv;
+
+       if (ctrl & NAND_CTRL_CHANGE) {
+               if ( ctrl & NAND_CLE )
+                       hwctl |= 0x1;
+               else
+                       hwctl &= ~0x1;
+               if ( ctrl & NAND_ALE )
+                       hwctl |= 0x2;
+               else
+                       hwctl &= ~0x2;
+               if ( (ctrl & NAND_NCE) != NAND_NCE)
+                       writeb(0x00, &(pdnb3_ndfc->term));
        }
+       if (cmd != NAND_CMD_NONE)
+               writeb(cmd, this->IO_ADDR_W);
 }
 
-static void pdnb3_nand_write_byte(struct mtd_info *mtd, u_char byte)
-{
-       if (hwctl & 0x1)
-               writeb(byte, &(pdnb3_ndfc->cmd));
-       else if (hwctl & 0x2)
-               writeb(byte, &(pdnb3_ndfc->addr));
-       else
-               writeb(byte, &(pdnb3_ndfc->data));
-}
 
 static u_char pdnb3_nand_read_byte(struct mtd_info *mtd)
 {
@@ -110,16 +80,8 @@ static void pdnb3_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 {
        int i;
 
-       if (len % 4) {
-               for (i = 0; i < len; i++)
-                       buf[i] = readb(&(pdnb3_ndfc->data));
-       } else {
-               ulong *ptr = (ulong *)buf;
-               int count = len >> 2;
-
-               for (i = 0; i < count; i++)
-                       *ptr++ = readl(&(pdnb3_ndfc->data));
-       }
+       for (i = 0; i < len; i++)
+               buf[i] = readb(&(pdnb3_ndfc->data));
 }
 
 static int pdnb3_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
@@ -135,12 +97,10 @@ static int pdnb3_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int le
 
 static int pdnb3_nand_dev_ready(struct mtd_info *mtd)
 {
-       volatile u_char val;
-
        /*
         * Blocking read to wait for NAND to be ready
         */
-       val = readb(&(pdnb3_ndfc->wait));
+       readb(&(pdnb3_ndfc->wait));
 
        /*
         * Return always true
@@ -148,24 +108,22 @@ static int pdnb3_nand_dev_ready(struct mtd_info *mtd)
        return 1;
 }
 
-void board_nand_init(struct nand_chip *nand)
+int board_nand_init(struct nand_chip *nand)
 {
-       pdnb3_ndfc = (struct pdnb3_ndfc_regs *)CFG_NAND_BASE;
+       pdnb3_ndfc = (struct pdnb3_ndfc_regs *)CONFIG_SYS_NAND_BASE;
 
-       nand->eccmode = NAND_ECC_SOFT;
+       nand->ecc.mode = NAND_ECC_SOFT;
 
        /* Set address of NAND IO lines (Using Linear Data Access Region) */
        nand->IO_ADDR_R = (void __iomem *) ((ulong) pdnb3_ndfc + 0x4);
        nand->IO_ADDR_W = (void __iomem *) ((ulong) pdnb3_ndfc + 0x4);
        /* Reference hardware control function */
-       nand->hwcontrol  = pdnb3_nand_hwcontrol;
-       /* Set command delay time */
-       nand->hwcontrol  = pdnb3_nand_hwcontrol;
-       nand->write_byte = pdnb3_nand_write_byte;
+       nand->cmd_ctrl   = pdnb3_nand_hwcontrol;
        nand->read_byte  = pdnb3_nand_read_byte;
        nand->write_buf  = pdnb3_nand_write_buf;
        nand->read_buf   = pdnb3_nand_read_buf;
        nand->verify_buf = pdnb3_nand_verify_buf;
        nand->dev_ready  = pdnb3_nand_dev_ready;
+       return 0;
 }
 #endif