rockchip: clk: remove RATE_TO_DIV

[people/ms/u-boot.git] / drivers / clk / rockchip / clk_rk3368.c

diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c
index 9ef5badf56da0fcc540347e4a022c9d402341b12..2be1f572d7212a166cf96680fb26b71464d360ba 100644 (file)
--- a/drivers/clk/rockchip/clk_rk3368.c
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -39,9 +39,6 @@ struct pll_div {
 #define GPLL_HZ                (576 * 1000 * 1000)
 #define CPLL_HZ                (400 * 1000 * 1000)
 
-#define RATE_TO_DIV(input_rate, output_rate) \
-               ((input_rate) / (output_rate) - 1);
-
 #define DIV_TO_RATE(input_rate, div)    ((input_rate) / ((div) + 1))
 
 #define PLL_DIVISORS(hz, _nr, _no) { \