rockchip: clk: update dwmmc clock div

[people/ms/u-boot.git] / drivers / clk / rockchip / clk_rk3399.c

diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 53d2a3f85dad63e43ce17446d326809305bb1e04..ec149c8be80bcf3b78f05cb31c77f9bbb712879d 100644 (file)
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -750,18 +750,21 @@ static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id)
        case HCLK_SDMMC:
        case SCLK_SDMMC:
                con = readl(&cru->clksel_con[16]);
+               /* dwmmc controller have internal div 2 */
+               div = 2;
                break;
        case SCLK_EMMC:
                con = readl(&cru->clksel_con[21]);
+               div = 1;
                break;
        default:
                return -EINVAL;
        }
-       div = (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT;
 
+       div *= (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT;
        if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT
                        == CLK_EMMC_PLL_SEL_24M)
-               return DIV_TO_RATE(24*1000*1000, div);
+               return DIV_TO_RATE(OSC_HZ, div);
        else
                return DIV_TO_RATE(GPLL_HZ, div);
 }
@@ -776,11 +779,12 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
        case HCLK_SDMMC:
        case SCLK_SDMMC:
                /* Select clk_sdmmc source from GPLL by default */
-               src_clk_div = GPLL_HZ / set_rate;
+               /* mmc clock defaulg div 2 internal, provide double in cru */
+               src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate);
 
                if (src_clk_div > 127) {
                        /* use 24MHz source for 400KHz clock */
-                       src_clk_div = 24*1000*1000 / set_rate;
+                       src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate);
                        rk_clrsetreg(&cru->clksel_con[16],
                                     CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
                                     CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |