Merge git://git.denx.de/u-boot-rockchip

[people/ms/u-boot.git] / drivers / clk / rockchip / clk_rk3399.c

diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 42926ba323b25b739544ab57ec5b479bfc1493ff..fb74c441ff9f84f7b151f819c2e588f1661ec45e 100644 (file)
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -997,6 +997,16 @@ static int rk3399_clk_enable(struct clk *clk)
        case HCLK_HOST1:
        case HCLK_HOST1_ARB:
                return 0;
+
+       case SCLK_MAC:
+       case SCLK_MAC_RX:
+       case SCLK_MAC_TX:
+       case SCLK_MACREF:
+       case SCLK_MACREF_OUT:
+       case ACLK_GMAC:
+       case PCLK_GMAC:
+               /* Required to successfully probe the Designware GMAC driver */
+               return 0;
        }
 
        debug("%s: unsupported clk %ld\n", __func__, clk->id);
@@ -1236,6 +1246,8 @@ static ulong rk3399_pmuclk_get_rate(struct clk *clk)
        ulong rate = 0;
 
        switch (clk->id) {
+       case PLL_PPLL:
+               return PPLL_HZ;
        case PCLK_RKPWM_PMU:
                rate = rk3399_pwm_get_clk(priv->pmucru);
                break;
@@ -1257,6 +1269,13 @@ static ulong rk3399_pmuclk_set_rate(struct clk *clk, ulong rate)
        ulong ret = 0;
 
        switch (clk->id) {
+       case PLL_PPLL:
+               /*
+                * This has already been set up and we don't want/need
+                * to change it here.  Accept the request though, as the
+                * device-tree has this in an 'assigned-clocks' list.
+                */
+               return PPLL_HZ;
        case SCLK_I2C0_PMU:
        case SCLK_I2C4_PMU:
        case SCLK_I2C8_PMU: