X-Git-Url: http://git.ipfire.org/?p=people%2Fms%2Fu-boot.git;a=blobdiff_plain;f=drivers%2Fclk%2Frockchip%2Fclk_rk3399.c;fp=drivers%2Fclk%2Frockchip%2Fclk_rk3399.c;h=fb74c441ff9f84f7b151f819c2e588f1661ec45e;hp=8822d3a9a87f81cc8bb41d727d3a622a4cd716e6;hb=434d5a00a4578f826e7e2cef29bf2388dd760a88;hpb=33554fcec99b7c8b57e004fdf18588ce21d85e68

diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 8822d3a9a8..fb74c441ff 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -1246,6 +1246,8 @@ static ulong rk3399_pmuclk_get_rate(struct clk *clk)
 	ulong rate = 0;
 
 	switch (clk->id) {
+	case PLL_PPLL:
+		return PPLL_HZ;
 	case PCLK_RKPWM_PMU:
 		rate = rk3399_pwm_get_clk(priv->pmucru);
 		break;
@@ -1267,6 +1269,13 @@ static ulong rk3399_pmuclk_set_rate(struct clk *clk, ulong rate)
 	ulong ret = 0;
 
 	switch (clk->id) {
+	case PLL_PPLL:
+		/*
+		 * This has already been set up and we don't want/need
+		 * to change it here.  Accept the request though, as the
+		 * device-tree has this in an 'assigned-clocks' list.
+		 */
+		return PPLL_HZ;
 	case SCLK_I2C0_PMU:
 	case SCLK_I2C4_PMU:
 	case SCLK_I2C8_PMU: